Carbon nanotube field-effect transistor (CNTFET)

This book is a structured introduction to how computers truly work, written for students, educators, and curious learners. It covers the foundations of binary and logic gates, the role of the CPU, memory and storage systems, operating systems, networking, and future technologies like quantum computing and artificial intelligence. Complex topics are explained in simple, approachable language to make computing accessible. By blending technical accuracy with clarity, the book aims to inspire a deeper appreciation of the logic and engineering behind modern computers.

For more than 80 years digital computers use the radix-2 or binary computer alphabet as their lowest symbolic and physical representation. This doctrine of computing is presumed in every modern computer. The radix economy theorem derives that radix-3 or ternary is however the optimal radix. Ternary is the first radix in the Multiple-Valued Logic (MVL) family that enables symmetrical arithmetic using the balanced ternary notation. The ongoing challenge is to engineer devices, circuits and systems that can physically represent three logic levels with competitive power, performance, area and cost metrics. For flash storage and communication MVL is already the industry standard, but logic remains binary. Ever since Dennard scaling stopped in 2005, binary computing is struggling to overcome the increasing power wall, memory wall and Electronic Design and Automation (EDA) wall. A unified MVL compute paradigm can theoretically address these challenges, making it a prime candidate for the beyond-CMOS era. This article-based thesis is structured in three parts. In the first part binary computing is discussed. The historical reasoning for this choice as well as the current scaling challenges that impede its future were reviewed. The part concludes with a review of several fundamental and engineering limits that are rarely cited but highly relevant when considering another radix such as Shannon’s noisy channel theorem and Rent’s rule. In the second part ternary computing is discussed. A brief overview of radix-3 theory and literature is presented. A novel radix comparison methodology is proposed to improve fairness. Historical efforts to build ternary computers were reviewed which started in the 1950’s. A categorization of the main benefits of balanced ternary is presented across 7 application domains. The part concludes with an overview of the critique on radix-3. In the third part practical aspects of ternary computing are discussed: multi-stable devices and EDA tooling. For devices, non-volatile ternary memory control with commercially available memristors was studied. A novel open source software tool uMemristorToolbox and hardware platform for multi-state memristor programming were developed. The experiments confirm that ternary memory with memristors is both feasible and low-cost. Lastly, EDA tooling and workflows for ternary logic chips are discussed. The open source software tool Mixed Radix Circuit Synthesizer (MRCS) was developed, the first browserbased EDA tool to design and verify binary, ternary and hybrid (mixed radix) circuits. It features a novel MVL circuit synthesis algorithm with HSPICE and verilog output targeting CMOS and multi-threshold CNTFET. The tool was used to design REBEL-2, a novel balanced ternary CPU with RISC-V-like ISA. Four MRCS designs have been tested on a FPGA and submitted for tape-out using the Openlane ASIC workflow.

The low power and high speed fundamental building blocks are essential to construct arithmetic circuits. Three input Exclusive-OR(XOR) is presented here based on compound gate method. The high performance is achieved by reducing input capacitance, choosing suitable input to propagate and avoiding glitch. The proposed XOR gate requires less number of transistors (i.e. only 8 transistors) and offers 60.62% of power dissipation reduction and 13.71% less propagation delay compared to two level conventional static XOR gate. The simulation is performed based on 32nm technology node(PTM-models) using Hspice Synopsis simulation tool.

An essential reason for implementing multilevel processing systems is to reduce the number of semiconductor elements and hence the complexity of the system. Multilevel processing systems are realized much easier by carbon nanotube field effect transistors (CNTFET) than by MOSFET transistors due to the CNTFET transistors' adjustable threshold voltage capabilities. This paper presents an efficient quaternary full-adder based on CNTFET technology that consists of two half-adder blocks, a quaternary decoder, and a carry generator circuit. The proposed architecture combines the base-two and base-four circuit design techniques to take full advantage of both techniques, namely, simple implementation and low chip area occupation of the entire proposed quaternary full-adder. The proposed structure is evaluated using a Stanford 32nm CNTFET library in HSPICE software. The simulation results for the proposed full-adder structure that utilizes a 0.9-V supply voltage reveal that the power consumption, propagation delay, and energy index are equal to 2.67 μW, 40 ps, and 10.68 aJ, respectively. NOMENCLATURE 1. 2 Chiral vector The diameter Carbon Nanotube (CNT) π π-π junction energy of carbon The flat band voltage The drain to source voltage δ The Drain Induced-Barrier Lowering (DIBIL) coefficient in CNT

Traditionally, binary decision diagram (BDD)-based algorithms are used to synthesize binary logic functions. A BDD can be transformed into circuit implementation by replacing each node in the BDD with a 2:1 multiplexer. Similarly, a ternary decision diagram can be transformed into circuit implementation using 3:1 Multiplexers. In this paper, we present a novel synthesis technique to implement ternary logic circuits using 2:1 multiplexers. Initially a methodology, which transforms a ternary logic function into a ternary-transformed binary decision diagram, is presented. This methodology is the basis for the synthesis algorithm that is used to synthesize various ternary functions using 2:1 multiplexers. Results for various ternary benchmark functions indicate that the proposed algorithm results in circuits that have, on an average 79%, and up to 99% fewer transistors when compared with the most recent 3:1 multiplexer-based algorithm available in the literature. Synthesized circuits have been implemented using carbon-nanotube field-effect transistors and simulated in HSPICE.

Carbon nanotubes have unique features and special properties that offer great potential for nano-electronic devices. Understanding the dependency of temperature and dielectric is essential to optimize the performance of carbon nanotube field effect transistors (CNTFETs).In this study, a numerical simulation model of semiconducting CNTFETs is presented to determine the electrical properties in the ballistic regime. This paper focused on the impact of temperature and dielectric constant to evaluate the input-output characteristic of CNTFET devices. Moreover, the study investigated the changes in threshold voltage as a function of gate dielectric constant and temperature in the nanometer regime. The findings emphasize the importance of integrating temperature and dielectric constant relationships in the design and optimization of CNTFETs, allowing for their effective incorporation into future electronic applications.

Analytical modeling equations for characterizing the threshold voltage (Vth) of carbon nanotube field effect transistor CNTFETs are presented in this study with chirality. The equations have been derived based on the charge and potential distributions existing between the gate and substrate in a CNTFET. The research demonstrates a significant correlation between the chiral vectors of carbon nanotubes (CNTs) and their threshold voltage (Vth)· The findings indicate a high level of coexistence between mathematical and visual simulation methodologies. The findings indicate that the determined threshold voltage (Vth) of a carbon nanotube field-effect transistor (CNTFET) possessing a chiral vector of (7, 2) exhibits a high degree of agreement with the relevant literature.

Gordon Moore, the co-founder of Intel, predicted that the number of transistors would quadruple every two years. As a result, device scaling had to happen. Scientists and researchers quickly learned that silicon MOSFETs had a scaling issue with technology. Carbon nanotube field effect transistors (CNTFET) are now replacing silicon metal oxide semiconductor field effect transistors (MOSFET) as an alternative. However, whereas we have access to precise circuit-level equations for MOSFETs, all we have for carbon nanotubes are model equations. In this research, we seek to model the behavior of the SWCNT-FET under varying conditions of diameter and gate insulator thickness. This would allow for more accurate performance predictions from the device, paving the way for more complicated CNTFET based circuit designs. Variations in mobile charges, drain currents, and gate insulator thickness are among the variables investigated. Simulation results demonstrate that the size of CNT diameter has direct influence on drain current which could be potential replacement of silicon technology for digital applications.

Abstract—This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20 % smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25µm CMOS technology confirms all results obtained from this paper. Keywords—Positive feedback, leakage current, read operation, write operation, dynamic energy consumption. I.

In this paper we compare simulation results on a differential pair circuit using a CNTFET model, already proposed by us, with the result obtained using Stanford model. We study the case of differential pair with differential input and single ended output as core of a 50 GHz amplifier for mm waves band. We consider the case of a CNTFET having a single CNT tube with indices (19,0) and 25 nm long. For this circuit we present result for its main parameters: gain, input impedance, output impedance, noise and distortion. Since the Stanford model includes fixed capacitance, for comparison we applied the same capacitance on our model. Since this capacitances dominate the high frequency cut, results are not much different, except for the lack of noise modelling in the Stanford model.

This paper deals with basic logic circuits using the carbon nanotube field effect transistor (CNTFET). Due to various beneficial properties of carbon nanotubes, these circuits are more efficient than Metal Oxide Field Effect Transistor (MOSFETs). The parameters like power, delay and power delay product of CNTFET based circuits are compared with that of CMOS technologies. Both the simulations are performed in HSPICE software. The CNTFET based circuits provides more power reduction, delay reduction, and Power Delay Product (PDP) reduction when compared with CMOS technologies.

In this work, we have proposed a fully differential 9T SRAM cell with high speed and enhanced data stability for high performance microprocessor application. This cell obtains smaller read delay and enhanced data stability due to two isolated read access mechanisms, which offers up-sizing of read driver during read operation. The performance of this proposed work is also compared against 6T and 9T SRAM cell on the basis of various parameters such as read/write operation delay, data stability, write ability, hold mode leakage power and layout area. As observed in simulation, under VDD variation the proposed design offers 45% (26%) lower read delay than 9T (6T).

Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectronics technology. It operates through one-by-one tunnelling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. Due to nanoscale feature size, ultralow power dissipation, and unique Coulomb blockade oscillation characteristics it may replace Field Effect Transistor FET). SET is very much advantageous than CMOS in few points. And in few points CMOS is advantageous than SET. So it has been seen that Combination of SET and CMOS is very much effective in the nanoscale, low power VLSI circuits. This paper has given a idea to make different sequential circuits using the Hybrid SET-CMOS. The MIB model for SET and BSIM4 model for CMOS are used. The operations of the proposed circuits are verified in Tanner environment. The performances of CMOS and Hybrid SET-CMOS based circuits are compared. The hybrid SET-CMOS circuit is found to consume lesser power than the CMOS based circuit. Further it is established that hybrid SET-CMOS based circuit is much faster compared to CMOS based circuit.

The shift in technology away from silicon complementary metal-oxide semiconductors (CMOS) to novel nanoscale technologies requires new design tools. In this paper, we explore one particular nanotechnology: carbon nanotube transistors that are self-assembled into circuits by using DNA. We develop design tools and demonstrate how to use them to develop circuitry based on this nanotechnology.

Considerable research has considered the design of low-power and high-speed devices. Designing integrated circuits with low-power consumption is an important issue due to the rapid growth of high-speed devices. Embedded static random-access memory (SRAM) units are necessary components in fast mobile computing. Traditional SRAM cells are more energyconsuming and with lower performances. The major constraints in SRAM cells are their reliability and low power. The objectives of the proposed method are to provide a high read stability, low energy consumption, and better writing abilities. A transmission gate-based multi-threshold single-ended Schmitt trigger (ST) 9T SRAM cell in a bit-interleaving structure without a write-back scheme is proposed. Herein, an ST inverter with a single bit-line design is used to attain the high read stability. A negative assist technique is applied to alter the trip voltage of the single-ended ST inverter. The multithreshold complementary metal oxide semiconductor (MTCMOS) technique is adopted to reduce the leakage power in the proposed single-ended TG-ST 9T SRAM cell. The proposed system uses a combination of standard and ST inverters, which results in a large read stability. Compared with the previous ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells, the proposed cell is implemented in Cadence Virtuoso ADE with 45-nm CMOS technology and consumes 35.80%, 42.09%, 31.60%, 12.54%, and 31.60% less energy for read operations and 73.59%, 93.95%, 92.76%, 89.23%, and 85.78% less energy for write operations, respectively.

This paper investigates a novel design of penternary logic gates using carbon nanotube field effect transistors (CNTFETs). CNTFET is a suitable candidate for replacing MOSFET with some useful properties, such as the capability of having the desired threshold voltage by regulating the diameter of the nanotubes. Multiple-valued logic (MVL) such as ternary, quaternary, and penternary is a promising alternative to the binary logic design, because of less complexity, less computational step and reduced chip area. We propose two penternary inverters which are designed in the multiplevalued voltage mode based on CNTFET. In the first proposed design, the resistors are used to implement penternary logic whereas, in the second proposed design, they are replaced with the transistors. Extensive simulation results using HSPICE represent that the two proposed designs reduce significantly the power consumption and delay and sensitivity to process variations as compared to the state-of-the-art penternary logic circuit in the literature.

The exponential increase of leakage currents in a scaled device is an inevitable consequence of MOSFET physics. Unfortunately constant field scaling reaches a performance limit. As the devices scaled down in nanometer regime the threshold voltage is also scaled, consequently the leakage power increases. If the channel length becomes too short, the depletion region from the drain can reach the source side and reduces the barrier for electron injection. In this paper we have analyzed the impact of channel length over threshold voltage of the CNTFET and MOSFET devices. With an analysis of HSPICE simulation results we found that the threshold voltage increases with decreasing channel length over a wide range of channel length in CNTFET that is not possible to get in MOSFET devices. The increase in threshold voltage in nanometer regime leads to reduce the leakage power and hence the CNTFET emerges as a power saving devices.

In the current research, the best property of Carbon Nanotube Field Effect Transistors (CNTFETs) exploited to propose a high performance 4-input 1-output (4 × 1) Multiplexer, using a CMOS-like Pass Transistor Logic (PTL) design style. To enhance a significant reduction in circuit complexity and a corresponding improvement in the performance envelope (power, area and speed) with respect to conventional CMOS equivalent circuit. The operating principles and experimental results for the PTL circuits using both p-FET and n-FET of CNTFETs presented. This property can be used in a multiplexer circuit, which transfers one of several input data to the output according to the control signal values. Results demonstrated that using of CNTFET can be achieved by constructing high performance carbon nanotube-based integrated circuits like logic Multiplexer based on a pass-transistor logic configuration. Further, this circuits can assembly with other circuits based on other Field effect transistors technology like GNR-FETs and improve ALU (Arithmetic Logic Unit) section of many processor ICs in high level of Nano-Scale VLSIs. The simulation results presented, and the power consumption compared with the conventional CMOS designs. The comparison of results approved that the CNTFET based design is capable of efficient power savings and high-speed performance.

SRAM cell design takes a big fraction of the entire power and die area in high performance processors. The overall power consumption in SRAM can be reduced either by decreasing the dynamic or static power. A Charge Recycling (CR) is a very efficient means to reduce the power dissipation in the write cycle of SRAM cell designs. To keep this point in view, this paper represents the simulation of four 64-bit SRAM cell topologies by using Charge Recycling scheme and their comparative analysis on the basis of their average write power consumption. The 64-bit SRAM cell designs are arranged in 8X8 form. Simulation reveals that 64-bit 9T SRAM cell with CR perform better than others in the term of power consumption but if die area and average power consumption both considers, then 64-bit 7T SRAM cell with CR perform well as compared to 64-bit 9T SRAM cell with CR. All the simulations of SRAM cell designs have been carried out on 180nm, 130nm and 100nm CMOS technology at 100 MHz and Vdd = 1.8 V.

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

The exponential increase of leakage currents in a scaled device is an inevitable consequence of MOSFET physics. Unfortunately constant field scaling reaches a performance limit. As the devices scaled down in nanometer regime the threshold voltage is also scaled, consequently the leakage power increases. If the channel length becomes too short, the depletion region from the drain can reach the source side and reduces the barrier for electron injection. In this paper we have analyzed the impact of channel length over threshold voltage of the CNTFET and MOSFET devices. With an analysis of HSPICE simulation results we found that the threshold voltage increases with decreasing channel length over a wide range of channel length in CNTFET that is not possible to get in MOSFET devices. The increase in threshold voltage in nanometer regime leads to reduce the leakage power and hence the CNTFET emerges as a power saving devices.

The cache memory design of microprocessors makes use of Static Random-Access Memory (SRAM) cells. Their efficiency is crucial because they are an integral part of the central computer system. Only 10-15 percent of a modern system on a chip's (SoC) transistors are dedicated to logic, whereas the rest are used for cache memory, increasing the performance strain. On top of that, the AI-reliant nature of today's implantable, portable, as well as wearable electronic equipment highlights the need for a robust SRAM architecture for CIM. Modern mobile communication devices include ample storage space for users' extensive media collections. Here, we adapt the Multi-threshold CMOS design to create a low-power SRAM cell. Power usage and read/write cycle Access Time can be lowered by using CMOS transistors with various threshold voltages. This work proposes a novel approach to reducing leakage in the idle state to cut down on power usage. The power usage of an SRAM cell is affected by the temperature, size of the transistors as well as the voltage used in the test. Data storage is an important function of several electronic components, specifically digital ones. The overall power usage of an SRAM is heavily influenced by leakage current. The research utilized a 1-bit 6T SRAM cell to construct a 1 KB memory array using CMOS technology and 0.6 volts for the supply voltage. In this section, we use deep submicron (130nm, 90nm, and 65nm) CMOS technology and the six-transistor (6T) SRAM cell to analyze how varying topologies impact the performance of a 12T SRAM array.

In this paper, we propose a new design of high-performance ultralow power carbon nanotube field effect transistor (CNTFET)-based nine-transistor static random access memory (SRAM) cell and its implementation using shared bitline (BL) and half-select free techniques. Simulations of the 9T SRAM design, using CNTFET compact model, have presented merits over the silicon-complementary-metal oxide semiconductor (CMOS) SRAM cell in terms of leakage current, power consumption, and stability. Uses of the half-select free technique eliminate the conflict between read and write operations and shared BL technique offers reduced physical layout area and enhanced data access speed. Further, uses of the increased number of tubes or say CNT array in the CNTFET device increases the probability of functionality (>95%) with a high yield SRAM cell.

This paper presents a survey of fault-masking techniques suitable for tolerating short-duration transient upsets in minimum-scale switching devices. Two types of fault masking are considered. The first type, coded dual-modular redundancy (cDMR), represents a family of parity-checking methods suitable for correcting a low rate of transient upsets. The second type, Restorative Feedback (RFB), is a triple-modular solution suitable for compensating a higher rate of transient upsets. We show that cDMR can be used efficiently for crossbar-style logic, but is not efficient in general for all logic styles. By contrast, RFB offers a fixed redundancy, and can be applied in general to any logic circuit. Finally, we propose novel circuits for ternary Muller C implementation based on carbon nanotube FET devices.

Ternary content-addressable memory (TCAM) is a type of associative memory used in many applications for high-speed data searching. We present herein a gate-all-around (GAA) carbon nanotube field-effect transistor (CNTFET)-based selfcontrolled TCAM cell design with a precharge-free match line. We compare the power-delay product (PDP) and static noise margin between the GAA-CNTFET-based traditional and proposed TCAM cell designs at the 11-nm technology node with a supply voltage of 0.8 V. The simulations are performed using the Virtuoso tool for different parameter values with the Stanford University GAA-CNTFET model. The simulation results show that, compared with the traditional design, the proposed design exhibits a significant reduction in power by 51.30%, delay by 17.16%, and PDP by 59.66% for a chiral vector of (20, 16, 0) with two channels. It is observed that the best chirality for the proposed design is (14, 20, 0) for a single channel, but (16, 16, 0) and (20, 16, 0) for a dual channel in terms of power, delay, stability, and PDP.

Carbon nanotube (CNT) field-effect transistors (CNFETs) promise to improve the energy efficiency of very-large-scale integrated (VLSI) systems. However, multiple challenges have prevented VLSI CNFET circuits from being realized, including inherent nanoscale material defects, robust processing for yielding complementary CNFETs (i.e., CNT CMOS: including both PMOS and NMOS CNFETs), and major CNT variations. Here, we summarize techniques that we have recently developed to overcome these outstanding challenges, enabling VLSI CNFET circuits to be experimentally realized today using standard VLSI processing and design flows. Leveraging these techniques, we demonstrate the most complex CNFET circuits and systems todate, including a three-dimensional (3D) imaging system comprising CNFETs fabricated directly on top of a silicon imager, CNT CMOS analog and mixed-signal circuits, 1 kilobit CNFET static random-access memory (SRAM) memory arrays, and a 16bit RISC-V microprocessor built entirely out of CNFETs. CCS CONCEPTS •Hardware~Emerging technologies~Circuit substrates~Carbon based electronics •Hardware~Very large-scale integration design~3D integrated circuits

We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate 1 kbit (1024) 6 transistor (6T) SRAM arrays fabricated with complementary metal-oxide-semiconductor (CMOS) CNFETs (totaling 6144 p-and n-type CNFETs), with all 1024 cells functioning correctly without any per-unit customization. Moreover, we show the first demonstration of CNFET CMOS 10T SRAM cells, capable of operating at highly scaled voltages down to 300 mV. We characterize the CNFET CMOS SRAM and demonstrate robust operation by writing and reading multiple patterns (to both the kbit arrays as well as the 10T SRAM cells), measuring SRAM variations in read, write, and hold margins and repeat cycling of cells. Moreover, due to the low-temperature back-end-of-line (BEOL)-compatible CNT-specific processing, CNFET SRAM enables new opportunities for digital systems, since: 1) CNFET SRAM can be fabricated directly on top of computing logic to realize three-dimensional integrated circuits; and 2) CNFET circuits can utilize metal routing both above and below the CNFET device layer (e.g., as in our demonstration which utilizes buried power rails, whereby the power rails are fabricated underneath the FETs while metal routing is fabricated above the FETs), providing opportunities for further SRAM density scaling. Index Terms-Carbon nanotubes (CNTs), carbon nanotube field-effect transistors (CNFETs), digital logic, static random-access memory (SRAM). I. INTRODUCTION C ARBON nanotube (CNT) field-effect transistors (CNFETs) are a promising emerging nanotechnology for next-generation energy-efficient digital very-large-scaleintegration (VLSI) circuits. Owing to their simultaneously ideal electrostatic control (due to the ultrathin ∼1-nm diameter of a CNT) and high carrier transport [1], [2], it is projected that the CNFETs can improve the energy-delay product (EDP, a metric of energy efficiency) by an order of magnitude versus silicon complementary metal-oxidesemiconductor (CMOS) [3]-[5]. In addition to these EDP benefits, CNFET digital logic has been fabricated at a record scaled 30 nm contacted gate-pitch (CGP, a key metric defining

In this paper, we introduce a 10-transistor static random access memory cell that features an unbalanced read decoupled bit line (RBL) with a 4T read pin for high-speed operation. Based on the stored data bit, the RBL is pre-charged to half the cell's supply voltage and allowed to charge and discharge. The Complementary Data (QB) node is driven by an inverter that connects the RBL to the virtual power rails via a transmission gate during read operation. RBL rises to VDD level for a read of 1 and dumps to ground level for a read of 0. During write mode and standby mode, the virtual power rails have the same RBL precharge level value. During the reading process, these are connected to actual supply levels. Dynamic control of virtual rails significantly reduces RBL leakage. The proposed 12T cell is larger compared to the SRAM 10T and reduces read lag by more than 50% compared to the 10T. The general performance characteristics of the 12T and 10T are similar, and the general designs are designed and implemented at Tanner EDA.

This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided  by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature decreases write mode failure. An access buffer seperates storage node from read access transistor to improve cell stability and prevent data-related leakage in read operation. Applying virtual ground also reduces the leakage. Furthermore, we design the cell control unit. The simulation results at VDD=0.5V exhibit the effectiveness of our proposed cell compared with other counterparts which are suitable for bit interleaving structure. Comparison results on the proposed cell and 6T cell show our cell improved 70% in write power consumption and 90.45% in read power consumption.

A novel 20 nm FinFET based 7T SRAM cell is presented. Proposed 7T SRAM cell involves the breaking-up of feedback between the true storing nodes which enhances the write-ability of the cell at ultra-low voltage power supply without boosted supply and write assist. The read decoupling and feedback cutting makes proposed 7T SRAM cell more robust to process variations in sub-threshold regime. For proposed 7T SRAM cell, the mean and standard-deviation (μ/σ) ratio of hold static noise margin is 31.5% higher than that of conventional iso-area 5T SRAM cell at 0.5 V VDD. The 7T SRAM cell has 66.4% higher μ/σ of read margin as that of 5T SRAM cell at 0.25 V VDD. The write static noise margin of 7T SRAM cell is $50% of VDD for all VDD values whereas 5T SRAM cell fails to write. During write '0', the proposed cell consumes only 0.11 Â power as that of 5T SRAM cell at 0.8 V VDD. The read operation of 7T SRAM cell consumes 0.34 Â lesser power than 5T SRAM cell read operation for all values of bit-line capacitances at 0.2 V VDD. At 0.2 V VDD, the 7T SRAM cell has 0.46 Â lower write '0' delay as that of 5T SRAM cell. The write delay of 7T SRAM cell is 0.32 Â lower as that of 5T SRAM cell at 0.8 V VDD. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low voltage supply without any write assist in 20 nm FinFET technology node.

This paper presents highly efficient three inputs Exclusive-OR/NOR gate (XOR/XNOR) cell. The Exclusive-OR/NOR gate (XOR/XNOR) logic gates are the essential blocks of various embedded arithmetic system such as binary full adder, parity generator/checker, binary comparator, and encryption processor. Many circuits have been proposed on full adder and XOR/XNOR gate design that can be categorised in two categories. First one offers full swing output and second one offers partial swing output. The Systematic Cell Design Methodology is partial swing based logic design method which offers less delay and low power consumption at weak logic '0' and logic '1' generation at output. The proposed design is based on pass transistor logic and transmission gate technology. The proposed design consumes 30%, 38%, 33%, 13% and 48% higher dynamic power than XO4, XO7, XO10, Hybrid and LPHSFA, respectively. While the delay time of proposed design is 40%, 40%, 33%, 75% and 81% lower than XRG1, XRG2, XRG3, Hybrid and LPHSFA, respectively. All simulation results have been obtained by using HSPICE schematic simulator based on TSMC 130nm CMOS technology at 1.2 V supply voltages.

The impact of alpha particle and exposure to cosmic radiation has multifold the existing stability issue associated with modern sub-100 nm SRAM cell design. Noise insertion in the half selected cell of a SRAM array is another serious issue which degrades the stability of a cell as well as waste energy through the half selected cells. The proposed highly stable 8T-SRAM cell takes care of both the above mentioned issues effectively. The cell is capable to be arranged in a bit-interleaving fashion which can then use a conventional error correction code (ECC) to correct the single bit error caused by the exposer to cosmic radiation. Traditionally the read stability and write ability are conflicting to each other and any one of them can be enhanced with sacrificing the other. But the proposed cell enhances both the read stability and the write ability simultaneously. Two other cells namely the 8T differential (8T-DIFF) SRAM and 9T read disturbance free (9T-RDF) SRAM are compared with the proposed SRAM cell which consume 20.1% and 16.2% more energy respectively. The read speed of the proposed SRAM is significantly higher than the 9T-RDF SRAM and marginally higher than the 8T-DIFF SRAM. The write speed of the proposed SRAM is also better than the two compared SRAM.

The paper investigates on the design aspects of different SRAM cells for access time, power consumption and static noise margin. All the designs are made by using standard 90nm CMOS process. Simulations have been done for 6T, 7T, 9T and 10T SRAM cells. 10T SRAM cell shows the best SNM among all the simulated cells. 9T shows least power and least access time. 6T cells stability limits the potential power saving achievable by voltage scaling while proposed 9T cells enhance stability. Layouts are also being made to create as compact a cell as possible. The results are compared with the actual known results and have been found justified.

This paper presents analysis of the Static Noise Margin (SNM), power dissipation, access time and dynamic noise margin of a novel low power proposed 8T Static Random Access Memory (SRAM) cell for read operations. In the proposed structure, two voltage sources are used, one is connected with the bit line and the other is connected with the bitbar line in order to reduce the voltage swing at the output nodes of the bit and the bit bar lines. Simulation results for the read static noise margin, read power dissipation, read access time and dynamic noise margin have been compared to those of other SRAM cells, reported in di erent literatures. It is shown that the proposed SRAM cell has better static noise margin and dissipates less power in comparison to other SRAM cells. Analog and schematic simulations have been done in a 45 nm environment with the help of Microwind 3.1, using the BSimM4 model.

It is seemed that we have to focus to minimize the power due to leakage current through a huge number of transistors and the large memory substance. This dissertation gives 5 Transistors future SoC (System on Chip) devices SRAM concept. Hence SRAM may be utilized in the place of 6 Transistors SRAM. By using DSCH2 and Microwind 2.6K we are designing a layout of SRAM in 2.5µm and 1.5µm technology by using 5 transistors and perform various operations on it. By using Microwind 2.6K software we are designing a layout diagram and checked it through DRC rule checker and after that simulate the layout and do the analysis. It helps to decrease the memory size.

The world’s appetite for abundant-data computing, where a massive amount of structured and unstructured data is analyzed, has increased dramatically. The computational demands of these applications, such as deep learning, far exceed the capabilities of today’s systems, especially for energy-constrained embedded systems (e.g., mobile systems with limited battery capacity). These demands are unlikely to be met by isolated improvements in transistor or memory technologies, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented functionality, performance, and energy efficiency. We show that the projected energy efficiency benefits of domain-specific 3D nanosystems is in the range of 1,000x (quantified using the product of system-level energy consumption and execution time) over today's domain-specific 2D systems with off-chip DR...

This paper presents modeling of devices, system, subsystem for any kind of field and providing the finding of developed optimization technique for simulation of bench mark circuits. The modeling can be adapted for any of device and system in general way but for this research work electronic devices and circuits under consideration. As day by day circuit complexity increases, proportionally simulation time will also increase. The proposed method is based on computational intelligence with backbone by artificial intelligence. The simulation is based upon mathematical model, and processing element consume the time for each fetch, decode and execute so if object under simulation process is complex it will took more time to process. In this regard the AI and CI modeling helps to process without going into direct mathematical modeling of the object. Obvious pre processing of data, data analysis and training required in the process. For the design and analysis software tools like C, python and MATLAB are used. The comparison of simulation time result table is shown for various circuits. It is found that CI and AI will help in simulation in future years.

This paper investigates a novel design of penternary logic gates using carbon nanotube field effect transistors (CNTFETs). CNTFET is a suitable candidate for replacing MOSFET with some useful properties, such as the capability of having the desired threshold voltage by regulating the diameter of the nanotubes. Multiple-valued logic (MVL) such as ternary, quaternary, and penternary is a promising alternative to the binary logic design, because of less complexity, less computational step and reduced chip area. We propose two penternary inverters which are designed in the multiplevalued voltage mode based on CNTFET. In the first proposed design, the resistors are used to implement penternary logic whereas, in the second proposed design, they are replaced with the transistors. Extensive simulation results using HSPICE represent that the two proposed designs reduce significantly the power consumption and delay and sensitivity to process variations as compared to the state-of-the-art penternary logic circuit in the literature.

In the world of IC, the technology scales down to
32nmor below and CMOS has lost its recommendation during
scaling beyond 32nm due to high power consumption and high
leakage current. Scaling triggers Short Channel Effects that
can be hard to conquer. So, FinFET is used because it reduces
the shortchannel effects. FinFET can be used in the nanometre
range. CNTFET is one of the replacements for present CMOS
technology because it can provide a stronger control over the
thin Si body and reduces the short channel effects. As the full
adder is one of the most promising units of the ALU because it
reduces speed and power consumption. The logic style used for
implementation is a Hybrid CMOS (HC) Full adder which
consumes fewer transistors and reduces power. Both
technologies (FinFET and CNTFET) reduces short channel
effects and can be used in nanometre technologies. In this
paper, the main objective is to find out the analysis of the best
efficient devices between FinFET and CNTFET based on the
Hybrid CMOS Full Adder circuit. Here, these are proposed
FinFET based Hybrid CMOS Full Adder and CNTFET based
Hybrid CMOS Full Adder. These new hybrid adder is having
only 10 transistors. The proposed full adder is a CNTFET and
FinFET based design implemented using Synopsys tools in
32nm, 16nm, 10nm technology and calculates Power
consumption, delay, and Power Delay Product (PDP) are
investigated and showed with better result comparison

In this paper, new tunable Schmitt triggers based on double-gate carbon nanotube field effect transistor (DG-CNTFET) are presented. The proposed inverter-based Schmitt triggers work with low supply voltage (0.8 V) and are very suitable for low voltage and low power applications. The adjustment of these Schmitt triggers are easily achieved by placing a DG-CNTFET transistor in the path of the internal and output nodes of the Schmitt triggers and by applying a control voltage to the back gate of the DG-CNTFET transistor without any additional mechanism. Based on the Hspice simulation results in the 32 nm CNTFET process, the proposed Schmitt triggers can consume 19.89 pW and 23.01 pW respectively. Based on the evaluation of the output characteristic curves in terms of input, it was observed that the value of hysteresis in the proposed Schmitt triggers covers 37.5% and 62.5% of the supply voltage value, respectively.

This paper presents a novel 9T static random access memory (SRAM) cell consisting of a single ended isolated read bit line with 2T read port for improving stability and a tail transistor for saving power. In the proposed design owing to the use of separate bitlines, the storing node voltage has not been affected during active mode operation. In the idle (hold) mode the static power dissipation of SRAM cell has been drastically reduced due to the formation of stack between tail transistor and internal latch. The proposed design has been verified by cadence virtuoso tool using UMC 65 nm CMOS technology. It provides a 42% and 34% improvement in write stability when compared to basic 6T and ultralow voltage (UV) 9T SRAM cells respectively. It has been observed that, the read stability is improved by 12% when compared to basic 6T SRAM cell and penalty of 10% when compared to UV 9T SRAM cell. A reduction of 22% in static power dissipation has also been observed in proposed design as compared to basic 6T SRAM cell when designed at same technology. This paper has also been proposed a mathematical modelling for validating the proposed design.

Carbon Nanotube Field Effect Transistor (CNTFET)s are applied instead of silicon transistors to conquer the constraint of MOSFETs in nano-scale, with improving the power consumption and performance. Full adder is one of the basic arithmetic operations to construct large computing systems like multiplication. Due to its widespread application, its optimal design with CNTFET technology is very useful. The contribution here is to propose a high performance CNTFET-based full adder which optimizes the delay and PDP in relation to the previous works in different voltage supply and load capacitance. To show the performance and applicability of this proposed design in large computing systems, three different carry ripple, skip and select adders, all with 4, 8 and 16 size bits are designed and simulated through HSPICE and 32nm CNTFET technology. The obtained results indicate the advantage of this proposed CNTFET-based full adder.

In this article a new design of a current mode full-adder is proposed through the field effect transistors based on carbon nanotubes. The outperformance of the current mode full-adder constructed by CNTFET compared to that of constructed by CMOS is observable in the simulation and comparisons. This circuit operates based on triple input majority function. The simulation is run by HSPICE software according to the model proposed in Stanford University for CNTFETs at 0.65 V power supply voltage. The proposed circuit outperforms compared to the previous current mode full-adders in terms of speed, accuracy and PDP.

Power consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating , transistor down scaling, voltage over scaling, applying modern technology and approximate computing are some candidate means in reducing power consumption. Among these candidates, approximate computing can generate a trade-off between accuracy and powerdelay-area efficiency in error resilient applications. According to Moore's law together with CMOS problems in nano scale regime, modern technologies emerge to solve these problems. Among these recent technologies, CNTFET technology is considered as promissing. As multiplication is frequently applied in multimedia processing, implimenting efficient multipliers constitute critical. Compressors are fundamental elements in reduction tree multipliers and improve their efficiency, thus an improvement in multipliers' performance. A new 12transistor approximate 4:2 compressor is proposed here. This new appropriate compressor, in term of area, power consumption, accuracy and reliability design is more efficient than its existing counterparts.

Side channel attacks exploit physical imperfections of hardware to circumvent security features achieved by mathematically secure protocols and algorithms. This is achieved by monitoring physical quantities, usually power consumption or electromagnetic radiation, which contain information about the secret data. As a countermeasure, several circuit styles have been proposed for designing side-channel resistant logic gates and flip-flops. However, little effort has been made to develop secure memory arrays. An SRAM cell with 8 transistors has been proposed in order to obtain power analysis resistance by using a dual-rail precharge principle, the same technique used in various secure logic styles. In this paper we look into the practical aspects of this cell such as noise margins, layout strategy and read current. In addition, we propose alternative solutions for poweranalysis resistant SRAM. We compare these solutions in terms of data stability, delay and side-channel resistance.

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The suggested circuit in this project is designed for IoT applications employing a modified transmission gate based SRAM cell that eliminates the need for peripheral circuitry during read operations. Biomedical systems that operate in the sub-threshold region with near-perfect efficiency require several kB of embedded memory. SRAMs account for 70% of the die area, which means they consume the most power and consume the most silicon. In the read operation, this topology provides a smaller area, less delay, lower power consumption, and better data stability. The SRAM cell is made of 45nm CMOS and runs at 0.45 V.

Circuit designing has traditionally been amalgamated with CMOS model. However increasing demand of portable electronics and the need to lower the power consumption has led to expeditious progress in low power VLSI design. With the advent of modern CNTFET based technology, customary silicon based CMOS devices are being replaced. The present paper attempts to analyse the performance of CNT based Tristate Buffer and further design a 2X1 Multiplexer (MUX) using the designed CNT Tristate Buffer. Design and simulation of CNT based Tristate Buffer and 2X1 MUX is compared with their conventional MOS counterparts using HSPICE and the analysis has been performed at 45 nm technology node. It is thereby concluded from the results that CNT based Tri State Buffer and Multiplexer are faster, more accurate and less power consuming than conventional MOS Tri State Buffer and Multiplexer.

Detection of cardiac biomarker is crucial in diagnosis of acute myocardial infraction (AMI). According to National Centre for Biotechnology Information (NCBI) increase in Troponin protein beyond the limits in the blood is main cause for cardiac injury. Researchers have designed and implemented precise and accurate Troponin I detection sensors. Output of these sensors is too low to activate read out device for display. Therefore, too low output should be strengthened and further processed by signal conditioning circuit. This Paper proposes design of first block Instrumentation amplifier of signal conditioning circuit using Carbon Nanotube Field Effect Transistors (CNFETs). Proposed instrumentation amplifier designed with CNFETs has very low noise and high performance of 108dB gain with a signal to noise ratio of 116dB. Sensor output is too low in the range of microvolts which is prone to low frequency noise. Proposed circuit reduces noise density to 0.4pV/√Hz.