Design solutions for securing SRAM cell against power analysis

Journal of Cryptographic Engineering, 2015

Electrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit-and a system-level methodology, which helps to reduce the data dependence of the instantaneous power consumption of cryptographic circuits. Accordingly, we define a specific design methodology, which is based on a novel data encoding and on the insertion of an on-chip filter implemented through capacitances in the layout. The new countermeasure, called time-enclosed logic (TEL), is able to hide the data dependence in a very short time interval (in the order of 100 ps in modern submicron technologies), constraining the minimum amount of bandwidth required from the attack setup. As a second and parallel contribution, we present a novel design time metric for validating our design, named frequency energy deviation, which is based on the investigation of the deviation of the frequency patterns of the current traces. By simulating a basic cell template under unbalanced capacitive condition, we show that standard dual-rail precharge logics exhibit a resilient leakage already at lower frequencies, whereas in TEL circuits the data dependence is shifted toward high frequencies. As a case study, we designed a TEL-featured cryptographic circuit using a 65-nm technology node, without any assumption on the routing of the logic gates. Correlation power analy-Electronic supplementary material The online version of this article (

Advances in Cryptology – EUROCRYPT 2011, 2011

Variability is a central issue in deep submicron technologies, in which it becomes increasingly difficult to produce two chips with the same behavior. While the impact of variability is well understood from the microelectronic point of view, very few works investigated its significance for cryptographic implementations. This is an important concern as 65-nanometer and smaller technologies are soon going to equip an increasing number of security-enabled devices. Based on measurements performed on 20 prototype chips of an AES S-box, this paper provides the first comprehensive treatment of variability issues for side-channel attacks. We show that technology scaling implies important changes in terms of physical security. First, common leakage models (e.g. based on the Hamming weight of the manipulated data) are no longer valid as the size of transistors shrinks, even for standard CMOS circuits. This impacts both the evaluation of hardware countermeasures and formal works assuming that independent computations lead to independent leakage. Second, we discuss the consequences of variability for profiled side-channel attacks. We study the extend to which a leakage model that is carefully profiled for one device can lead to successful attacks against another device. We also define the perceived information to quantify this context, which generalizes the notion of mutual information with possibly degraded leakage models. Our results exhibit that existing side-channel attacks are not perfectly suited to this new context. They constitute an important step in better understanding the challenges raised by future technologies for the theory and practice of leakage resilient cryptography.

IEEE Journal of the Electron Devices Society, 2020

One pivotal countermeasure in dealing with side-channel power analysis attacks is to maintain the signal-to-noise ratio of the power readings associated with the target as data-independent and as low as possible, in order to limit the attacker's ability to deduce meaningful information from the target. The following study shows that the MSET (Multiple-State Electrostatically-Formed Nanowire Transistor) device achieves these two desired outcomes by virtue of its low-power characteristics, therefore having an inherent advantage in terms of side channel attacks over prevalent technologies. This advantage is tested with an SRAM cell and a memory register. Using correlation metrics, the correlation coefficient of the Hamming distance to the power dissipation in the register -at the adversary's point of observation -is shown to be close to zero over multiple power traces, when the register is implemented in MSET technology. INDEX TERMS MSET, power-analysis attacks, side-channel attacks, low-power transistors.

2017

Power Analysis Attacks pose serious threats to hardware implementations of cryptographic systems. To retrieve the secret key, the attackers can exploit the mutual information between power consumption and processed data / operations through monitoring the power consumption of the cryptosystems. Field Programmable Gate Arrays (FPGA) have emerged as attractive implementation platforms for providing hardware-like performance and software-like flexibility for cryptosystem developers. These features come at the expense of larger power consumption, which makes FPGAs more vulnerable to power attacks. Different countermeasures have been introduced in the literature, but as they have originally been developed for Application-Specific Integrated Circuits (ASIC), mapping them onto FPGAs degrades their effectiveness. In this work we propose a logic

IEEE Access

Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times. INDEX TERMS Side-channel attacks, differential power analysis, countermeasure, back-gate biasing, FD-SOI, SOTB, RISC-V.

2006

Hardware implementations of cryptographic algorithms may leak some information that can be used to recover cryptographic keys. This work combines reconfigurable techniques with the recently proposed leak resistant arithmetic (LRA) to thwart some side channel attacks (SCA). The introduced architecture outcomes the performance of classical implementation of modular multiplication, for key size exceeding 2048 bits, with a reasonable extra area overhead. Nevertheless, this is not a drawback, but a cost, since the main issue of the proposed architecture is the improved robustness in terms of security.

International Journal of Innovative Technology and Exploring Engineering, 2020

In this digital world, everything is inculcated within technology which increases the importance of memory storage. All the data processed in today’s electronics requires a storage space. The data stored in this memory are extracted & misused which is a serious issue in day today world. This provenly shows that there is a need for enhancement in data security. There are different types of memory storage. Among them portable devices, routers, workstation, personal computer commonly uses SRAM for storage. Due to side-channel leakage power in SRAM, illegal data extraction had become a serious threat.6T SRAM cells are often prone to this power analysis attack [4]. This data attack often happens in standby mode of a memory cell. To provide resiliency to these types of attacks, a symmetric 8T SRAM cell was used which incorporates two more transistors than the conventional 6T cell to significantly reduce the correlation between the stored data and the leakage currents. The main purpose of ...

arXiv (Cornell University), 2022

How to efficiently prevent side-channel attacks (SCAs) on cryptographic implementations and devices has become an important problem in recent years. One of the widely used countermeasures to combat power consumption based SCAs is to inject indiscriminate random noise sequences into the raw leakage traces. However, this method leads to significant increases in the energy consumption which is unaffordable cost for battery powered devices, and ways must be found to reduce the amount of energy in noise generation while keeping the side-channel invisible. In this paper, we propose a practical approach of energy efficient noise generation to prevent SCAs. We first take advantage of sparsity of the information in the leakage traces, and prove the existence of energy efficient noise generation that is optimized in the side channel protection under a given energy consumption budget, and also provide the optimal solution. Compared to the previous approach that also focuses on the energy efficiency, our solution is applicable to all general categories of compression methods. Furthermore, we also propose a practical noise generator design by aggregating the noise generation patterns produced by compression methods from different categories. As a result, the protection method presented in this paper is practically more applicable than previous one. The experimental results also validate the effectiveness of our proposed scheme. • Security and privacy → Tamper-proof and tamper-resistant designs; Embedded systems security.

IEEE Transactions on Very Large Scale Integration Systems, 2018

Power analysis attacks (PAAs), a class of sidechannel attacks based on power consumption measurements, are a major concern in the protection of secret data stored in cryptographic devices. In this paper, we introduce the secure double rate registers (SDRRs) as a registertransfer level (RTL) countermeasure to increase the security of cryptographic devices against PAAs. We exploit the SDRR in a conventional advanced encryption standard (AES)-128 architecture, improving the immunity of the cryptographic hardware to the state-of-the-art PAAs. In the AES-128 exploiting SDRR, the combinational path evaluates random data throughout the entire clock cycle, and the interleaved processing of random and real data ensures the protection of both combinational and sequential logics. Our technique does not require the duplication of the combinational path to process the random data, thus limiting area overhead, unlike previous RTL countermeasures. The proposed approach is validated by means of PAAs based on real measurements on a field-programmable gate array implementation and on a 65-nm CMOS prototype chip. The protected implementation shows a strongly reduced correlation coefficient for the correct key, and more than three orders of magnitude increase in the measurements to disclosure with respect to the unprotected AES-128. Index Terms-Advanced encryption standard (AES), CMOS, correlation power analysis (CPA), differential power analysis (DPA), Internet of Things (IoT), mutual information (MI), power analysis attack (PAA), register-transfer level (RTL) countermeasure, side-channel attack (SCA).

IEEE Access

Side channel attacks have become a major threat to hardware systems. Most modern digital IC designs utilize sequential elements which dominate the information leakage. This paper reports the first unified analysis and comprehensive comparison of known secure flip-flop circuits. We present a device level analysis of the information leakage from these FFs and propose several evaluation metrics to quantify their security. We show that simulated PA attacks that utilize the information evaluated by these metrics at the gate-level extract more information at the module-level.