Figure 10 Simulation setup for comparing read delay time.
Related Figures (12)
Fig. 1. Standard 6T SRAM cell. a) Circuit schematic. b) Stick diagram of a traditional cell layout. c) Stick diagram of a “thin cell” layou Fig. 2. Power-cut cell schematic. Fig. 3. Power-analysis secure cells with shared power-cut transistors. Fig. 5. Distribution of the cut signal in a design using feedback-cut cells. Fig. 7. Butterfly curve of the feedback-cut cell (full line) and the 6T cell (dashed line). Fig. 8. Static noise margin when the cell is not accessed. Fig. 9. Static noise margin during the read access. Fig. 11. Stick diagram of the feedback-cut cell. Feedback-cut cell layout strategy is presented in figure 11. In this layout polysilicon and diffusion lines are printed in only one direction which should reduce transistor mismatch and provide good scalability. This is the preferred technique for small technology nodes. This type of layout is unfortunately not applicable to shared PMOS structure since in this structure it is not allowed to share power-contacts between the cells connected to the same bit-line pair. For this reason, traditional cell layout as shown in | b) should be used. Major disadvan- tage of this strategy is the fact that poly and diffusion lines are printed in both directions which is not suitable for lower technology nodes and will probably result in area overhead. From the side-channel security point of view, disadvantage of the traditional layout strategy is the systematic mismatch between the pull-down and the access transistors. Introduced Fig. 13. Standard deviation over the inputs for different time samples for the power-cut cell during the write cycle. Maximal deviation for the standard SRAM cell is above 354A. For secure SRAM cells this value is lower by four Fig. 12. Standard deviation over the inputs for different time samples for the standard 6T cell during the write cycle. Fig. 15. Standard deviation over the inputs for different time samples for the feedback-cut cell during the write cycle. Fig. 14. Standard deviation over the inputs for different time samples for the shared PMOS structure during the write cycle.
