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Table 1: N-curve analysis of the proposed design at various cell ratios

Table 1 N-curve analysis of the proposed design at various cell ratios

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Figure 1: (a) Schematic and (b) Timing diagrams of the proposed SRAM cell Several SRAM cell d modified ST inverter wi inverters, which reduces section. This section discusses the pro he proposed SRAM cell are given in MTCMOS technique based on a single BL structure, which devices to reduce leakage. The proposed cell has a cross-coup esigns have been investigated to reduce the power, and significant constraints have been considered in the memory portion of the chip as the best possible design pathway, as posed SRAM cell design. The schematic rigs. la and |b. This method adapts the includes a high Vth with nominal Vth ed standard inverter and a single-ended h both having high Vth. In place of a single-pass gate in the literature, a ransmission gate (TP and TN) is used with one enable (EN) transistor connected between the two he unnecessary switching activities d uring hold mode. The TP, TN, and EN all have a nominal Vth. The word lines (WL and WLB) are row-based signals and the WWL is a column-based signal. The WL is connected to the TN and EN gates, the WLB is connected to the TP gate, and the WWL is connected to the source of the feedback transistor (NF).
Figure 1: (a) Schematic and (b) Timing diagrams of the proposed SRAM cell Several SRAM cell d modified ST inverter wi inverters, which reduces section. This section discusses the pro he proposed SRAM cell are given in MTCMOS technique based on a single BL structure, which devices to reduce leakage. The proposed cell has a cross-coup esigns have been investigated to reduce the power, and significant constraints have been considered in the memory portion of the chip as the best possible design pathway, as posed SRAM cell design. The schematic rigs. la and |b. This method adapts the includes a high Vth with nominal Vth ed standard inverter and a single-ended h both having high Vth. In place of a single-pass gate in the literature, a ransmission gate (TP and TN) is used with one enable (EN) transistor connected between the two he unnecessary switching activities d uring hold mode. The TP, TN, and EN all have a nominal Vth. The word lines (WL and WLB) are row-based signals and the WWL is a column-based signal. The WL is connected to the TN and EN gates, the WLB is connected to the TP gate, and the WWL is connected to the source of the feedback transistor (NF).
Figure 2: Read operations in the proposed ST inverter scheme The read operation of the proposed cell is depicted in Fig. 2. The BL is pre-charged to VDD during read operations, the WWL is set to “1,” and the inverter controls node Q. Activating the row- dependent signals (WL and WLB) allows turning on the transmission gate. If Q has zero charge, the BL discharges; otherwise, there is no change in the BL. Disturbances caused by the BL during read operations are the most common cause of read failures. If the storage node is enabled through read disturbances, then the voltage attains the inverter trip voltage. The proposed design addresses this problem by combining a regular inverter and an ST inverter into a cross-coupled structure. Figs. 3a and 3b represent the single-ended modified ST inverter and its DC characteristics, respectively. The ST inverter has a greater trip voltage than the normal inverter when the input changes from logical “0” to logical “1.” The voltage at node Vx increases with the NF transistor, which reduces the strength of PDR1 transistor. As a result, when a read disturbance reaches the storage node, the ST inverter is more resistant to read interruptions compared with an ideal inverter.
Figure 2: Read operations in the proposed ST inverter scheme The read operation of the proposed cell is depicted in Fig. 2. The BL is pre-charged to VDD during read operations, the WWL is set to “1,” and the inverter controls node Q. Activating the row- dependent signals (WL and WLB) allows turning on the transmission gate. If Q has zero charge, the BL discharges; otherwise, there is no change in the BL. Disturbances caused by the BL during read operations are the most common cause of read failures. If the storage node is enabled through read disturbances, then the voltage attains the inverter trip voltage. The proposed design addresses this problem by combining a regular inverter and an ST inverter into a cross-coupled structure. Figs. 3a and 3b represent the single-ended modified ST inverter and its DC characteristics, respectively. The ST inverter has a greater trip voltage than the normal inverter when the input changes from logical “0” to logical “1.” The voltage at node Vx increases with the NF transistor, which reduces the strength of PDR1 transistor. As a result, when a read disturbance reaches the storage node, the ST inverter is more resistant to read interruptions compared with an ideal inverter.
Figure 3: (a) Schematic diagram of the ST inverter and (b) Its DC characteristics at VDD =0.5 V
Figure 3: (a) Schematic diagram of the ST inverter and (b) Its DC characteristics at VDD =0.5 V
Figure 4: Proposed TG-ST 9T static RAM (a) Write-0 and (b) Write-1 operations Write operations are conditional on whether the information to be composed on the SRAM cell isa “1” or “0.” Fig. 4a illustrates the write-0 operation. The column-based signal WWL remains “1” in the write-0 operation, and the write driver sets BL to “0”, WL to “1,” and WLB to “0.” The Q node is pushed to “0” through the turned-on transmission gate, and the ST inverter flips. The proposed SRAM cell cuts off the VDD by disconnecting the pMOS transistor of the standard inverter, which achieves write-0 capability during the write operations.
Figure 4: Proposed TG-ST 9T static RAM (a) Write-0 and (b) Write-1 operations Write operations are conditional on whether the information to be composed on the SRAM cell isa “1” or “0.” Fig. 4a illustrates the write-0 operation. The column-based signal WWL remains “1” in the write-0 operation, and the write driver sets BL to “0”, WL to “1,” and WLB to “0.” The Q node is pushed to “0” through the turned-on transmission gate, and the ST inverter flips. The proposed SRAM cell cuts off the VDD by disconnecting the pMOS transistor of the standard inverter, which achieves write-0 capability during the write operations.
Figure 5: DC characteristics of the negative VWWL given at VDD =0.5 V
Figure 5: DC characteristics of the negative VWWL given at VDD =0.5 V
Table 2: Comparison of N-curve results of various SRAM cell
Table 2: Comparison of N-curve results of various SRAM cell
Figure 6: N-curve analysis of the proposed design at 0.5 V
Figure 6: N-curve analysis of the proposed design at 0.5 V
All selected columns must be controlled in column-based assist techniques, which leads to an increased energy consumption, whereas only one row is selected and controlled in row-based assist techniques to attain a low power. Due to the low-energy in row-based support methods, the row-based boosted VWL is chosen with a boosted WL voltage to ensure the circuit has a 30 stability. The negative VWWL for a 30 write capability of the proposed and ST 9T SRAM cells are shown in Fig. 8, which indicates the proposed method has better results.
All selected columns must be controlled in column-based assist techniques, which leads to an increased energy consumption, whereas only one row is selected and controlled in row-based assist techniques to attain a low power. Due to the low-energy in row-based support methods, the row-based boosted VWL is chosen with a boosted WL voltage to ensure the circuit has a 30 stability. The negative VWWL for a 30 write capability of the proposed and ST 9T SRAM cells are shown in Fig. 8, which indicates the proposed method has better results.
Figure 7: Read delay comparison at various supply voltages
Figure 7: Read delay comparison at various supply voltages
Figure 9: Write-0 and write-1 operational waveforms for (a) The control signals, (b) Selected cells in the storage node, and (c) Column-based cells
Figure 9: Write-0 and write-1 operational waveforms for (a) The control signals, (b) Selected cells in the storage node, and (c) Column-based cells
Table 3: Comparison of SRAM approaches for 45-nm CMOS technologies Tab. 3 indicates that the proposed Multi- Vt TG-ST 9T SRAM cell consumes a read energy of 50.2 nJ whereas the ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells have read energies of 78.2, 86.7, 73.4, 57.4, and 73.4 nJ, respectively. The write energy of the proposed SRAM cell is 6.47 nJ and the ST 9T, ST 11T, 11T, 10T, and 7T SRAM consume 24.5, 107, 89.4, 60.1, and 45.5 nJ, respectively. Similarly, the total energy of the proposed SRAM cell design is 5.39 nJ and those for the ST 9T, ST 11T, 11T, 10T, and 7T SRAM are 24.8, 48.3, 32.1, 25.2, and 32.7 nJ, respectively. Thus, the proposed design has low read and write energies.
Table 3: Comparison of SRAM approaches for 45-nm CMOS technologies Tab. 3 indicates that the proposed Multi- Vt TG-ST 9T SRAM cell consumes a read energy of 50.2 nJ whereas the ST 9T, ST 11T, 11T, 10T, and 7T SRAM cells have read energies of 78.2, 86.7, 73.4, 57.4, and 73.4 nJ, respectively. The write energy of the proposed SRAM cell is 6.47 nJ and the ST 9T, ST 11T, 11T, 10T, and 7T SRAM consume 24.5, 107, 89.4, 60.1, and 45.5 nJ, respectively. Similarly, the total energy of the proposed SRAM cell design is 5.39 nJ and those for the ST 9T, ST 11T, 11T, 10T, and 7T SRAM are 24.8, 48.3, 32.1, 25.2, and 32.7 nJ, respectively. Thus, the proposed design has low read and write energies.
4.6 Comparison at Vdd=0.5 V
4.6 Comparison at Vdd=0.5 V
Table 3: Continued
Table 3: Continued
Related topics:
Materials EngineeringComputer ScienceInterdisciplinary EngineeringNumerical Analysis and Computational MathematicsTransmission Gate.Static random access memory
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