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Fig. 9. The simulation result of QDEC- (a): I, (b): 10, (c): 1, (d): 12b, (e): 12, (): B Fig. 10. The simulation results of the proposed half-adder-(a): A input, B Input, (c): Sum Output, (d): Car output.

Figure 9 The simulation result of QDEC- (a): I, (b): 10, (c): 1, (d): 12b, (e): 12, (): B Fig. 10. The simulation results of the proposed half-adder-(a): A input, B Input, (c): Sum Output, (d): Car output.

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The control signals which are created by a decoder, are applied to the transistors’ gates.
The control signals which are created by a decoder, are applied to the transistors’ gates.
Fig. 2. The initial idea of the quaternary full-adder
Fig. 2. The initial idea of the quaternary full-adder
Fig. 3. The proposed optimized quaternary full-adder
Fig. 3. The proposed optimized quaternary full-adder
TABLE 2 THE LOOK-UP TABLE OF FOUR-LEVEL INVERTERS C. Half-adder's sum and inverse carry output
TABLE 2 THE LOOK-UP TABLE OF FOUR-LEVEL INVERTERS C. Half-adder's sum and inverse carry output
TABLE 3 LOOK-UP TABLE OF THE SUM OUTPUT OF HALF- ADDER Now, to fully describe the operation. be used. Four-level logic is utilized wit VDD/3, 2/3VDD, and VDD volt, whic , the circuit of Fig. 5 can h the voltages equal to 0, h are the same as 0, 1, 2, or 3. Supposing that VDD equals | volt, the circuit equivalent to Fig. 6 can be used to create voltages of 0.3 and 0.6 volts. In the case of the output equal to 0.3 volts, keys K1 and K4 should be in the ON state, and keys K3 and K2 s For the output to be equal to 0.6 volts, be the ON state, and keys K4 and K1 s hould be in the Off state. keys K2 and K3 should hould be disconnected.
TABLE 3 LOOK-UP TABLE OF THE SUM OUTPUT OF HALF- ADDER Now, to fully describe the operation. be used. Four-level logic is utilized wit VDD/3, 2/3VDD, and VDD volt, whic , the circuit of Fig. 5 can h the voltages equal to 0, h are the same as 0, 1, 2, or 3. Supposing that VDD equals | volt, the circuit equivalent to Fig. 6 can be used to create voltages of 0.3 and 0.6 volts. In the case of the output equal to 0.3 volts, keys K1 and K4 should be in the ON state, and keys K3 and K2 s For the output to be equal to 0.6 volts, be the ON state, and keys K4 and K1 s hould be in the Off state. keys K2 and K3 should hould be disconnected.
Fig. 4. a) QDEC - Quaternary Inverter; b) NQI c) IQI d) PQI [28]
Fig. 4. a) QDEC - Quaternary Inverter; b) NQI c) IQI d) PQI [28]
TABLE 4 THE LOOK-UP TABLE OF QUATERNARY SUM, FINAL CARRY, AND CBAR OF THE PROPOSED HALF-ADDER
TABLE 4 THE LOOK-UP TABLE OF QUATERNARY SUM, FINAL CARRY, AND CBAR OF THE PROPOSED HALF-ADDER
Fig. 5. The quaternary full-adder circuit’s sum output realized at CNTFET transistor level [22] In this circuit, the NMOS transistor is used to transfer values 0 and 1, and the PMOS transistor is used for values 2 and 3. The value of their chiral vector is determined using the threshold voltage of each transistor. If we want to calculate the value of the chiral vector for these transistors using Eq. 2 and 3, the value is obtained as n= 7.
Fig. 5. The quaternary full-adder circuit’s sum output realized at CNTFET transistor level [22] In this circuit, the NMOS transistor is used to transfer values 0 and 1, and the PMOS transistor is used for values 2 and 3. The value of their chiral vector is determined using the threshold voltage of each transistor. If we want to calculate the value of the chiral vector for these transistors using Eq. 2 and 3, the value is obtained as n= 7.
Fig. 6. The sum output equivalent circuit The communication-aided adaptive protection methods [8, 9] and modified time-current curves for DOCRs [10] are some of the renorted solutions to modifv the MG protection svcstem
Fig. 6. The sum output equivalent circuit The communication-aided adaptive protection methods [8, 9] and modified time-current curves for DOCRs [10] are some of the renorted solutions to modifv the MG protection svcstem
The values in Table 4 are from 0 to 6 because, based on the quaternary logic's four-level values (i.e., 0, 1, 2, and 3), the maximum sum in the half-adder is 6. This is equal to 12 in the base four, in which digit 1 is carried, and digit 2 is the sum. Fig. 7 shows the transistor-level implementation of the Cbar. Fig. 7. Carry bar output implementation of the proposed half- \dder
The values in Table 4 are from 0 to 6 because, based on the quaternary logic's four-level values (i.e., 0, 1, 2, and 3), the maximum sum in the half-adder is 6. This is equal to 12 in the base four, in which digit 1 is carried, and digit 2 is the sum. Fig. 7 shows the transistor-level implementation of the Cbar. Fig. 7. Carry bar output implementation of the proposed half- \dder
The QDEC block is simulated by Hspice software. The timing diagram of the input and output signals of this block is shown in Fig. 9.
The QDEC block is simulated by Hspice software. The timing diagram of the input and output signals of this block is shown in Fig. 9.
Fig. 8. The Carry generator transistor level circuit (nl1=7, n2=0 or all of Transistor)
Fig. 8. The Carry generator transistor level circuit (nl1=7, n2=0 or all of Transistor)
The proposed half-adder block consists of two circuits for creating Cbar and Sum, and the timing diagram of the input and output signals of this block is shown in Fig. 10. The simulation results show that this circuit consumes 1.3679 microwatts of power for proper operation, while the delay in the signal path is equal to 10 picoseconds. These results show that the PDP (Power Delay Product) index of this block is equal to 0.136 fJ.
The proposed half-adder block consists of two circuits for creating Cbar and Sum, and the timing diagram of the input and output signals of this block is shown in Fig. 10. The simulation results show that this circuit consumes 1.3679 microwatts of power for proper operation, while the delay in the signal path is equal to 10 picoseconds. These results show that the PDP (Power Delay Product) index of this block is equal to 0.136 fJ.
Fig. 11. The simulation results of the final carry generator- (a): Cbar1 output, (b): Cbar2 output, (c): Carry output.
Fig. 11. The simulation results of the final carry generator- (a): Cbar1 output, (b): Cbar2 output, (c): Carry output.
Related topics:
Multiple Valued LogicCarbon nanotube field-effect transistor (CNTFET)
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