JP4998338B2 - Semiconductor device and circuit board - Google Patents

Description

  The present invention relates to a semiconductor device and a circuit board, and more particularly to a semiconductor device in which a semiconductor chip is mounted on a circuit board, and a circuit board on which the semiconductor chip is mounted.

  In recent years, area-mounted semiconductor devices (semiconductor packages) such as BGA (Ball Grid Array) have been widely used. In the case of a BGA type semiconductor device, a semiconductor chip such as an LSI is mounted on one surface side of a predetermined circuit board using a wire, and the semiconductor chip is sealed with a mold resin. Bumps such as solder balls are connected to the other surface side of the circuit board on which the semiconductor chip is mounted, and the semiconductor device is mounted on another substrate such as a mother board via the bumps.

  As a circuit board of such a BGA type semiconductor device, a multilayer wiring circuit board is widely used. On a multilayer wiring circuit board, for example, as a wiring layer, circuit patterns and pads are formed on the front and back surfaces, and a ground plane wiring and a power plane wiring are formed on the inner layer. An insulating layer is provided between each wiring layer, and electrical connection between different wiring layers is performed by a through hole penetrating such an insulating layer.

Conventionally, a semiconductor device or the like in which a semiconductor chip is embedded in the inner layer of a circuit board, another semiconductor chip is mounted on one surface side, and a solder ball is connected to the other surface side has been proposed ( For example, see Patent Document 1.)
JP 2005-142466 A

However, the multilayer wiring circuit board used in the BGA type semiconductor device as described above has the following problems.
That is, when a semiconductor device is reflowed, such as during a solder ball mounting (mounting) process or a mounting process of the semiconductor device on another substrate, the circuit board wiring layer is insulated by heat during the reflow. Local separation occurs between the layers, particularly between the inner plane wiring and the insulating layer in contact with the outside, and the circuit board portion corresponding to the separated portion bulges outward. .

  Such local swelling of the circuit board is likely to occur in a region where the bumps are not densely arranged on the surface side where the bumps are provided. In addition, when the insulating layer between the wiring layers absorbs moisture, such local swelling of the circuit board is more likely to occur.

  The present invention has been made in view of these points, and an object thereof is to provide a semiconductor device in which the occurrence of local swelling of a circuit board to be used is suppressed. Another object of the present invention is to provide a circuit board that suppresses the occurrence of local swelling.

  According to an aspect of the present invention, a circuit board having a multilayer wiring and a semiconductor chip mounted on the circuit board, the circuit board includes a first region in which the semiconductor chip is disposed, and the first circuit board. A second region outside the first region and provided with a plurality of pads wire-bonded to the semiconductor chip on a surface side on which the semiconductor chip is disposed; and between the first region and the second region And a through-hole provided in the third region so as to penetrate through a plurality of layers. The circuit board includes at least two layers of plain wiring in an inner layer of the circuit board. The hole is electrically connected to any of the plane wirings, or is not electrically connected to any of the plane wirings, and the through-holes in the third region of at least one of the plane wirings are not connected. A plurality of openings are provided in the formation region, and a plurality of bumps are selectively provided outside the third region on the side of the circuit board opposite to the surface on which the semiconductor chip is disposed. A semiconductor device is provided.
  According to another aspect of the present invention, in a multilayer wiring circuit board, the first region in which the semiconductor chip is disposed and the surface side on which the semiconductor chip is disposed outside the first region. A second region provided with a plurality of first pads to be wire-bonded to a semiconductor chip; a third region between the first region and the second region; and a plurality of layers penetrating the third region. Provided with at least two layers of plain wiring in the inner layer, and the through hole is electrically connected to any of the plane wirings, or not electrically connected to any of the plane wirings. A plurality of openings are provided in a region where the through hole is not formed in the third region of at least one of the plane wirings, and is on the side opposite to the surface on which the semiconductor chip is disposed. Te, optionally outside the third region, the circuit board having a plurality of second pads plurality of bumps are connected respectively are provided are provided.

According to the above circuit board, the third region between the first region in which the semiconductor chip is disposed and the second region in which pads for electrically connecting the semiconductor chip and the circuit substrate are formed. Due to the through hole provided in the inner layer, peeling of the inner layer can be suppressed.

  The disclosed semiconductor device and circuit board can effectively suppress the occurrence of local swelling of the circuit board.

Hereinafter, it will be described in detail with reference to the drawings.
First, the first embodiment will be described.
FIG. 1 is a schematic cross-sectional view of a semiconductor device.

A semiconductor device 10 shown in FIG. 1 has a configuration in which a semiconductor chip 30 such as an LSI is mounted on a circuit board 20.
The semiconductor chip 30 is fixed to a die area at the center of one main surface side of the circuit board 20 by using a die bond film 40 and is electrically connected to the circuit board 20 by a plurality of gold (Au) wires 50. The semiconductor chip 30 mounted on the circuit board 20 in this way is sealed with a mold resin 60 on the mounting surface side. The semiconductor chip 30 can also be fixed to the die area using a paste-like adhesive (including a conductive material) in the die bond area.

  A plurality of solder balls 70 are connected as bumps to the main surface side opposite to the mounting surface side of the semiconductor chip 30 of the circuit board 20. The semiconductor device 10 is connected to another substrate such as a mother board through these solder balls 70.

Here, the circuit board 20 has a structure including four wiring layers.
The first wiring layer (first wiring layer) 21 is formed closest to the mounting surface of the semiconductor chip 30, and the die area 21 a of the semiconductor chip 30, the circuit pattern 21 b, and the semiconductor chip 30 by the Au wire 50. The wire bonding pad 21c is configured.

  The inner wiring layer (second wiring layer) 22 and the third wiring layer (third wiring layer) 23 both constitute a plain wiring. Here, the second wiring layer 22 is a plane wiring (ground plane wiring) 22a connected to the ground potential, and the third wiring layer 23 is a plane wiring (power plane wiring) 23a connected to the power supply potential.

The fourth wiring layer (fourth wiring layer) 24 is formed closest to the connection surface of the solder ball 70, and constitutes a connection pad 24 a for the solder ball 70.
The front and back surfaces of the circuit board 20 are covered with a solder resist 25 except for a part of the circuit pattern 21b and the pads 21c and 24a.

  In such a circuit board 20, a predetermined core layer 26 is formed between the second wiring layer 22 and the third wiring layer 23, and between the first wiring layer 21 and the second wiring layer 22, The third wiring layer 23 and the fourth wiring layer 24 are constituted by prepreg layers 27 and 28, respectively. Of the first wiring layer 21, the second wiring layer 22, the third wiring layer 23, and the fourth wiring layer 24, electrical connection between different layers is performed by one or two layers of the core layer 26 and the prepreg layers 27 and 28. This is performed by a through hole 29a formed through the above.

  Solder balls 70 are selectively arranged densely in a central portion 20a including a region where the semiconductor chip 30 is disposed and in a peripheral portion 20c including a region (pad forming region) where a wire bonding pad 21c is formed. Has been. For example, the solder ball 70 in the central portion 20a can be used mainly as a thermal ball and ground connection terminal for the heat dissipation of the semiconductor chip 30, and the solder ball 70 in the peripheral portion 20c is mainly for signal input / output to the semiconductor chip 30. It can be used as a terminal. The solder ball 70 is not disposed in the region including the intermediate portion 20b between the central portion 20a and the peripheral portion 20c.

  In addition to the through holes 29a formed mainly in the central portion 20a and the peripheral portion 20c, the circuit board 20 includes the first wiring layer 21 to the intermediate portion 20b in a region where the solder balls 70 are not densely arranged. A through hole 29b reaching the four wiring layers 24 is formed. The through hole 29b plays a role of suppressing swelling generated when the circuit board 20 is heated. Details regarding the swelling generated in the circuit board 20 will be described later.

  Although shown in a simplified manner in FIG. 1, each of the through holes 29a and 29b has a structure in which a side peripheral surface is made of metal and a resin (for example, solder resist 25) is filled in a columnar shape at the center. Alternatively, the entire structure may be a columnar metal.

The circuit board 20 and the semiconductor device 10 having the above-described configuration are formed, for example, according to the following flow.
FIG. 2 is a diagram showing an example of a schematic flow of forming a circuit board.

  First, the ground plane wiring 22a of the second wiring layer 22 and the power plane wiring 23a of the third wiring layer 23 are formed on the core layer 26 using, for example, copper (Cu) (step S1).

  Next, the prepreg layers 27 and 28 are bonded to both surfaces of the core layer 26 on which the ground plane wiring 22a and the power plane wiring 23a are formed (step S2). In that case, the ground plane wiring 22a and the power plane wiring 23a formed in the core layer 26 are blackened, and then the prepreg layers 27 and 28 are arranged on both surfaces of the core layer 26 and pressed. By bonding to the core layer 26.

Next, a predetermined number of holes are drilled at predetermined positions where the through holes 29a and 29b are to be formed (step S3). This drilling can be performed by drilling, for example.
Next, a Cu film is formed on the sidewalls of the holes and the surfaces of the prepreg layers 27 and 28 (step S4). For example, an electroless Cu plating process is first performed to form a thin seed Cu film on the entire surface of the substrate including the sidewall of the hole, and then an electrolytic Cu plating process is performed to form a Cu film having a predetermined thickness on the seed Cu film. . For example, a Cu film is formed inside the hole leaving a cavity in the center. Thereby, the through holes 29a and 29b are formed.

  Next, the Cu film formed on the prepreg layers 27 and 28 is patterned (step S5). Thereby, the pattern of the first wiring layer 21 is formed on the prepreg layer 27, and the pattern of the fourth wiring layer 24 is formed on the prepreg layer 28.

  Next, the solder resist 25 is filled in the hollow portions of the through holes 29a and 29b, and a pattern of the solder resist 25 is formed also in a predetermined region on the front and back surfaces (step S6). Thereby, the pads 21c of the first wiring layer 21, the pads 24a of the fourth wiring layer 24, and the like exposed from the solder resist 25 are formed on the front and back surfaces.

  Next, SR coating is applied to the exposed surface of the solder resist 25 (step S7), and nickel (Ni) / Au plating treatment is applied to the exposed surface of the Cu film (pads 21c and 24a) (step S8).

  After that, the external shape processing (step S9) and the inspection for selecting good / defective products are performed (step S10). Before this inspection, a moisture absorption process under a predetermined condition for the circuit board 20 and a heat treatment at a temperature corresponding to a reflow temperature of a solder ball 70 described later are performed as necessary. When the circuit board 20 is shipped as a product, after this inspection, the non-defective product is packed in a predetermined form and shipped.

The circuit board 20 is normally formed continuously for the parts used for the plurality of semiconductor devices 10, and is individually cut after the semiconductor chip 30 is mounted.
In the formation flow, the diameters of the through holes 29a and 29b (the diameters of the holes at the time of drilling) can be the same size or different sizes.

  Further, when forming the Cu film in step S4, the inside of the hole may be filled with the Cu film without leaving a cavity in the center of the hole. In this case, the solder resist 25 is formed only on the front and back surfaces of the circuit board 20.

  Further, at the time of the Ni / Au plating process in step S8, the Ni / Au plating is selectively performed on the Cu film in a predetermined area, and after the process, the Cu film outside the predetermined area is etched back to form a final pattern. It may be formed on the prepreg layers 27 and 28. Here, an example of a method for forming the circuit board 20 that performs such etch-back will be described with reference to FIGS. 3 to 8 separately. Here, the steps from the formation of the ground plane wiring and the power plane wiring to the core layer as illustrated in FIGS. 1 and 2, the bonding of the prepreg layer to the core layer, and the drilling of each of these layers Description of the above will be omitted, and examples of subsequent steps will be described.

  3 to 8 are explanatory views of a circuit board forming process for performing etch back, in which FIG. 3 is a schematic cross-sectional view of the main part of the electroless plating process, and FIG. 4 is a schematic cross-sectional view of the main part of the electroplating process. 5 is a schematic cross-sectional view of the main part of the etching process, FIG. 6 is a schematic cross-sectional view of the main part of the resist forming process, FIG. 7 is a schematic cross-sectional view of the main part of the Ni / Au plating process, and FIG. It is a cross-sectional schematic diagram.

  For the substrate on which the hole 85 is formed by forming the ground plane wiring 81 and the power plane wiring 82 to the core layer 80, bonding the prepreg layers 83 and 84 to the core layer 80, and drilling the respective layers. First, as shown in FIG. 3, an electroless plating process is performed to form a seed Cu film 86 on the side walls of the holes 85 and the surfaces of the prepreg layers 83 and 84.

  Next, as shown in FIG. 4, after a resist 87 is formed in a predetermined region, an electrolytic plating process is performed to form a Cu film 88 on the seed Cu film 86. Here, the Cu film 88 is formed leaving a cavity at the center of the hole 85.

  Next, after removing the resist 87, etching (microetching) is performed, and as shown in FIG. 5, the unnecessary portion of the Cu film 88 and the seed Cu film 86 are removed, and the basic structure of the pattern is formed on the prepreg layers 83 and 84. Form.

  Next, as shown in FIG. 6, a liquid solder resist 89 is formed by a technique such as printing to form a pattern of the solder resist 89 on the front and back surfaces of the substrate, and the solder resist 89 is formed in the cavity remaining in the hole 85. Fill. Subsequently, as shown in FIG. 6, a resist 90 is formed so as to cover a portion to be removed by an etch back described later in the pattern formed on the prepreg layers 83 and 84. This resist 90 is formed in order to prevent Ni / Au plating from being formed in a portion that is removed by etch back during the next Ni / Au plating process.

  Then, after the formation of the resist 90, as shown in FIG. 7, Ni / Au plating is performed, and Ni is deposited on the exposed Cu film 88 on the prepreg layers 83 and 84, which is not covered with the resist 90. / Au plating film 91 is formed.

  Finally, the resist 90 is removed, and etch back is performed as shown in FIG. 8 to remove the portion of the Cu film 88 covered with the resist 90 from the Cu film 88 on the prepreg layers 83 and 84. A final pattern is formed on the prepreg layers 83 and 84.

When performing etch back, the circuit board 20 having the configuration shown in FIG. 1 may be formed according to the flow shown in this example.
The semiconductor device 10 using the circuit board 20 formed as described above can be formed, for example, according to the flow shown in FIGS.

  FIG. 9 is a diagram showing an example of a schematic flow of forming a semiconductor device. 10 to 17 are explanatory views of the semiconductor device forming process, FIG. 10 is a schematic cross-sectional view of the main part of the dicing process, FIG. 11 is a schematic cross-sectional view of the main part of the die bonding process, and FIG. 13 is a schematic cross-sectional view of the main part of the sealing process, FIG. 14 is a schematic cross-sectional view of the main part of the ball mounting process, FIG. 15 is a schematic cross-sectional view of the main part of the reflow process, and FIG. FIG. 17 is an explanatory diagram of a pre-shipment process, and is a schematic cross-sectional view of the relevant part of the process.

  First, after affixing the die bond film 40 to the wafer 92 on which the plurality of semiconductor chips 30 are formed, as shown in FIG. 10, dicing is performed using a dicer 93 to separate the semiconductor chips 30 (step S20). .

  Next, as shown in FIG. 11, each semiconductor chip 30 is bonded and fixed (die-bonded) to each die area of the circuit board 20 before cutting formed as described above via a die-bonding film 40 (step S21). ).

  Next, as shown in FIG. 12, the semiconductor chip 30 and the circuit board 20 are connected (wire bonded) by the Au wire 50 (step S22), and then, as shown in FIG. Sealing is performed (step S23).

  Next, as shown in FIG. 14, for example, a flux (not shown) is applied, and then solder balls 70 are placed (mounted) on the pads exposed on the side opposite to the mounting surface of the semiconductor chip 30 (step S24). . Then, as shown in FIG. 15, reflow is performed at a predetermined temperature to weld the solder balls 70 to the pads (step S25). When a flux is applied, cleaning for removing the flux is usually performed after this welding.

Next, as shown in FIG. 16, the circuit board 20 is cut (step S26). As a result, individual semiconductor devices 10 are formed.
Thereafter, each semiconductor device 10 undergoes a predetermined inspection for selecting non-defective / defective products. As shown in FIG. 17, the non-defective products are packed in a predetermined shipping tray 94 (step S27), and a predetermined stamp 95 is provided. Then (step S28), packing and shipping (step S29).

  As described above, since the through hole 29b is formed in the intermediate portion 20b of the circuit board 20, the circuit board 20 is not swollen even if it is heated during reflow after the solder ball 70 is mounted. Occurrence can be suppressed. Here, the swelling that occurs when the through hole 29b is not formed in the intermediate portion 20b will be described in more detail.

  When a semiconductor device having a configuration similar to that shown in FIG. 1 is configured using a circuit board in which the through hole 29b is not formed as described above, a solder ball mounting process or other semiconductor device is provided. When the semiconductor device is reflowed during the mounting process on the substrate, the circuit substrate is swollen by heat during the reflow.

18A and 18B are electron micrographs of a circuit board, in which FIG. 18A is a plane on the solder ball connecting surface side, FIG. 18B is a part in the XX cross section of FIG. It is a part in a YY cross section.
Here, the semiconductor device 100 is configured using the circuit board 110 in which the through hole for suppressing the occurrence of the swelling of the circuit board is not formed, and the semiconductor device 100 is heated at a predetermined temperature. The circuit board 110 used has four wiring layers, and the second wiring layer and the third wiring layer are a ground plane wiring and a power plane wiring, respectively. Between the second wiring layer and the third wiring layer is a core layer, between the first wiring layer and the second wiring layer, and between the third wiring layer and the fourth wiring layer is a prepreg layer. A semiconductor chip is mounted on the first wiring layer side using a die bond film and an Au wire and sealed with a mold resin, and a solder ball 120 is connected to the fourth wiring layer side to constitute the semiconductor device 100.

  When the semiconductor device 100 using such a circuit board 110 is heated, as shown in FIG. 18A, particularly the solder balls 120 on the solder ball 120 connecting surface side of the circuit board 110 are formed. A bulge 130 was generated in a non-existing region. Looking at the cross section of the location where the bulge 130 occurs, as shown in FIGS. 18B and 18C, the fourth wiring layer 111 of the circuit board 110, and the third wiring layer 112 and the fourth wiring layer 111 are It was found that the prepreg layer 113 in the meantime swelled to the connection surface side of the solder ball 120.

The result of investigating the swelling generated on the circuit board with the circuit board alone without mounting the semiconductor chip will be described with reference to FIGS.
19A and 19B are schematic plan views of the circuit board before cutting, where FIG. 19A is a diagram showing a semiconductor chip mounting surface side, and FIG. 19B is a diagram showing a solder ball connection surface side.

  As shown in FIG. 19A, the circuit board 140 has a die area 141 in which a semiconductor chip is disposed and a pad formation region 142 in which a plurality of pads 142a are formed on the semiconductor chip mounting surface side. Yes. As shown in FIG. 19B, a plurality of pads 143 to which solder balls are connected are formed on the opposite surface.

  The circuit board 140 is a four-layer wiring circuit board having the same configuration as the circuit board 110 used in the semiconductor device 100 shown in FIG. That is, the semiconductor chip connection pads 142a and the like are formed in the first wiring layer, and the solder ball connection pads 143 are formed in the fourth wiring layer. The second wiring layer and the third wiring layer in the inner layer are a ground plane wiring and a power plane wiring, respectively. Further, the space between the second wiring layer and the third wiring layer is a core layer, and the space between the first wiring layer and the second wiring layer and the space between the third wiring layer and the fourth wiring layer are prepreg layers. It is. A through hole for suppressing the occurrence of swelling of the circuit board 140 is not formed.

  The circuit board 140 having such a configuration was boiled for 2 hours, then heated from room temperature to 280 ° C. and then cooled again to room temperature. After this moisture absorption and heating / cooling treatment, occurrence of swelling was confirmed on both the semiconductor chip mounting surface side and the solder ball connection surface side of the circuit board 140.

FIG. 20 schematically shows electron micrographs obtained at two different locations on the circuit board after moisture absorption and heating / cooling treatment.
As shown in FIGS. 20A and 20B, the circuit board 140 that has been subjected to moisture absorption and heating / cooling processing as described above has a second wiring layer 145 of ground plane wiring and power plane wiring as shown in FIGS. A core layer 148 is provided between the third wiring layer 146 and the prepreg layer 149 between the first wiring layer 144 and the second wiring layer 145 and between the third wiring layer 146 and the fourth wiring layer 147. , 150 are provided. Predetermined regions of the first wiring layer 144 and the fourth wiring layer 147 are covered with a solder resist 153.

  Looking at the cross section of the circuit board 140 after moisture absorption and heating / cooling treatment, as shown in FIGS. 20A and 20B, the ground plane wiring of the second wiring layer 145 and the prepreg layer 149 are separated. The peeled portion 151 and the peeled portion 152 where the power plane wiring of the third wiring layer 146 and the prepreg layer 150 were peeled off were confirmed. Such peeling was not observed between the second wiring layer 145 and the third wiring layer 146 and the core layer 148.

By the way, the circuit board is warped due to the influence of the difference in thermal expansion coefficient between the constituent materials during heating and cooling.
FIG. 21 is an example of the measurement result of the warp of the circuit board generated during heating.

  When a circuit board in which a through hole for suppressing swelling is not formed is heated from room temperature RT to 250 ° C. and then cooled down to room temperature RT again, during the heating / cooling, the circuit board is shown in FIG. As shown, warping occurs.

  Due to the stress when such warping occurs, peeling occurs between the plane wiring and the prepreg layer having relatively weak adhesion and a large contact area, and the circuit board portion corresponding to the peeled portion Swelling occurs. In particular, when the circuit board absorbs moisture prior to heating / cooling, such peeling and swelling are more likely to occur.

  For this reason, in the circuit board 140 shown in FIG. 19, after predetermined processing, as shown in FIG. 20, between the second wiring layer 145 and the prepreg layer 149, and the third wiring layer 146, as shown in FIG. 20. It can be said that peeling portions 151 and 152 are generated between the prepreg layer 150 and the prepreg layer 150, respectively, and the circuit board 140 is swollen.

  However, as shown in FIG. 18, when the semiconductor device 100 is configured using the circuit board 110 having the same configuration, the swelling 130 is selectively generated on the connection surface side of the solder ball 120. This is because the semiconductor chip, the die bond film and the mold resin exist on the opposite surface side, that is, the semiconductor chip mounting surface side, so that the peeling between the second wiring layer and the prepreg layer is suppressed, and the semiconductor chip mounting surface side swells. This is because the occurrence of this is suppressed. On the other hand, on the connection surface side of the solder balls 120, a bulge 130 is generated, particularly in a region where the solder balls 120 are not densely arranged.

  From the above knowledge, in the semiconductor device 10 shown in FIG. 1, the through hole 29b reaching from the first wiring layer 21 to the fourth wiring layer 24 into the intermediate portion 20b in the region where the solder balls 70 are not densely arranged. And the occurrence of swelling of the circuit board 20 is suppressed. By forming the through hole 29b in the intermediate portion 20b, the core layer 26 on which the second wiring layer 22 and the third wiring layer 23 are formed and the prepreg layers 27 and 28 are more firmly connected through the through hole 29b. It will be. As a result, the occurrence of swelling of the circuit board 20 around the area where the solder balls 70 are not densely arranged is effectively suppressed.

  Thus, the through hole 29b formed to suppress the occurrence of swelling of the circuit board 20 can be formed in various electrical connection forms with the internal wiring. For example, the through hole 29 b in the circuit board 20 can be formed in a state of being electrically connected to the power plane wiring 23 a of the third wiring layer 23.

FIG. 22 is a schematic plan view of power plane wiring.
In FIG. 22, a large number of through holes 29a are formed in the central portion 20a and the peripheral portion 20c. A plurality of through holes 29b are formed in the intermediate portion 20b between the central portion 20a and the peripheral portion 20c in the region where the solder balls 70 are not densely arranged. In FIG. 22, a white portion indicates a portion where the power plane wiring 23 a is not formed in the third wiring layer 23.

  The through hole 29a can be formed by being electrically connected to the power plane wiring 23a of the third wiring layer 23 as shown in FIG. In this case, the through hole 29b may be configured to be electrically connected to the first wiring layer 21 or the fourth wiring layer 24 as necessary in addition to the third wiring layer 23.

In addition, the through hole 29 b that suppresses the occurrence of swelling of the circuit board 20 can be formed in a state of being electrically connected to the ground plane wiring 22 a of the second wiring layer 22.
FIG. 23 is a schematic plan view of ground plane wiring.

  In FIG. 23, a plurality of through holes 29b for suppressing the occurrence of swelling of the circuit board 20 are formed in the same area as in the case of FIG. 22 in the ground plane wiring 22a of the second wiring layer 22. In FIG. 23, white portions indicate portions where the ground plane wiring 22 a is not formed in the second wiring layer 22.

  The through hole 29a can be formed by being electrically connected to the ground plane wiring 22a of the second wiring layer 22, as shown in FIG. In this case, the through hole 29b may be configured to be electrically connected to the first wiring layer 21 or the fourth wiring layer 24 as necessary in addition to the second wiring layer 22.

  Further, the through hole 29b that suppresses the occurrence of the swelling of the circuit board 20 is configured not to be electrically connected to either the ground plane wiring 22a of the second wiring layer 22 or the power plane wiring 23a of the third wiring layer 23. You can also

FIG. 24 is a schematic plan view of another power plane wiring.
In FIG. 24, a plurality of through holes 29b for suppressing the occurrence of swelling of the circuit board 20 are formed in the same region as in FIG. 22 in a state where they are not electrically connected to the power plane wiring 23a. . In FIG. 24, the white portions indicate the portions where the power plane wiring 23 a is not formed in the third wiring layer 23.

  The through hole 29b is formed in the second wiring layer 22 in an electrically unconnected state with the ground plane wiring 22a, as shown in FIG. Thus, the through hole 29a can be formed in a state where it is not electrically connected to either the second wiring layer 22 or the third wiring layer 23. In this case, the through hole 29b may be configured to be electrically connected to the first wiring layer 21 or the fourth wiring layer 24 as necessary.

  In addition, a through-hole 29b that suppresses the occurrence of swelling of the circuit board 20 and a non-conductor in which the conductor portion of the ground plane wiring 22a of the second wiring layer or the power plane wiring 23a of the third wiring layer 23 is removed in a mesh shape. A part can also be formed.

FIG. 25 is a schematic plan view of a power plane wiring in which a mesh-like non-conductive portion is formed.
In FIG. 25, a plurality of through holes 29b are formed in the same area as in FIG. 22 of the power plane wiring 23a of the third wiring layer 23, and a plurality of non-conductor portions 23b are formed in a mesh shape. . The non-conductive portion 23b functions as an anchor that is filled with the resin component when the prepreg layer 28 is attached to the core layer 26 in the process of forming the circuit board 20, and connects the prepreg layer 28 and the core layer 26 more strongly. To do. Further, the non-conductor portion 23b also serves as a path for releasing moisture contained in the circuit board 20 to the outside.

  As shown in FIG. 25, by forming such a non-conductive portion 23b together with the through hole 29b, the occurrence of swelling of the circuit board 20 can be effectively suppressed. In addition, a plurality of mesh-like non-conductor portions similar to the above may be formed on the ground plane wiring 22a of the second wiring layer 22 in place of or together with the power plane wiring 23a of the third wiring layer 23. This can effectively suppress the occurrence of swelling of the circuit board 20.

  Next, a second embodiment will be described. In the description of the second embodiment, the same or equivalent elements as those described in the first embodiment are denoted by the same reference numerals.

FIG. 26 is a schematic plan view of power plane wiring on a circuit board included in the semiconductor device of the second embodiment.
As shown in FIG. 26, the circuit board 20 of the semiconductor device 10 of the second embodiment has a power plane wiring 23a in the intermediate portion 20b between the central portion 20a and the peripheral portion 20c, as shown in FIG. The non-conductor portion 23c is formed by being deleted over a wide range. As in FIG. 22, in FIG. 26, the white portion indicates the portion where the power plane wiring 23 a is not formed in the third wiring layer 23.

  Even when the non-conductor portion 23c is formed as shown in FIG. 26, the same effect as the case where the through hole 29b is formed can be obtained. That is, the non-conductive portion 23 c is filled with the resin component when the prepreg layer 28 is attached to the core layer 26 in the process of forming the circuit board 20. Thereby, the non-conductor portion 23 c functions as an anchor that firmly connects the prepreg layer 28 and the core layer 26. As a result, peeling between the prepreg layer 28 and the power plane wiring 23a is suppressed, and the occurrence of swelling of the circuit board 20 is suppressed.

  Further, instead of the power plane wiring 23a of the third wiring layer 23 or together with the power plane wiring 23a, if the same non-conductive portion is formed on the ground plane wiring 22a of the second wiring layer 22, the prepreg layer 27 and Separation from the ground plane wiring 22a can be suppressed, and the occurrence of swelling of the circuit board 20 can be effectively suppressed.

  However, when the semiconductor device 10 is configured using the circuit board 20 on which such a non-conductor portion 23c is formed, based on the knowledge shown in FIGS. 18 to 21, the solder ball 70 is connected to the connection surface side. In order to suppress the occurrence of swelling, it is desirable to form the non-conductor portion 23c in the power plane wiring 23a of the third wiring layer 23 at least near the connection surface side of the solder ball 70.

  The non-conductor portion 23c and the like formed on the power plane wiring 23a and the ground plane wiring 22a are not only one pattern formed continuously as shown in FIG. 26, but also a plurality of patterns (for example, FIG. 26 non-conductor portions 23c are discontinuous at each of the three corner portions.

  22 to 26, the lines dividing the power plane wiring 23a or the ground plane wiring 22a into nine indicate the boundaries of the central portion 20a, the intermediate portion 20b, or the peripheral portion 20c of the circuit board 20. It is not a thing.

  In the above description, a circuit board having four wiring layers is described as an example of a multilayer wiring circuit board. However, a circuit board having four or more wiring layers, for example, a ground plane wiring and a power plane wiring are used. In a circuit board or the like of 6-layer wiring provided with two layers, the same problem of peeling and swelling occurs. In such a multilayer wiring circuit board, as described above, a through hole is formed in the intermediate portion between the central portion and the peripheral portion, a non-conductive portion is formed in a mesh shape together with the through hole, or the intermediate portion It is possible to suppress the occurrence of peeling and swelling by forming a non-conductor portion in which the pattern of the plane wiring is deleted in a wider range.

Regarding the embodiment described above, the following additional notes are further disclosed.
(Appendix 1) Circuit board with multilayer wiring,
A semiconductor chip mounted on the circuit board;
Have
The circuit board is
A first region in which the semiconductor chip is disposed;
A second region outside the first region and formed with a plurality of pads used for electrical connection with the semiconductor chip;
A third region between the first region and the second region;
A through hole formed through the plurality of layers in the third region;
A semiconductor device comprising:

  (Supplementary note 2) The supplementary note 1, wherein a plurality of bumps are selectively arranged outside the region corresponding to the third region on the side opposite to the arrangement surface side of the semiconductor chip. Semiconductor device.

(Supplementary Note 3) The circuit board includes at least two layers of plain wiring in an inner layer,
The semiconductor device according to appendix 1 or 2, wherein the through hole is electrically connected to one of the plane wirings.

(Supplementary Note 4) The circuit board includes at least two layers of plain wiring in an inner layer,
The semiconductor device according to appendix 1 or 2, wherein the through hole is not electrically connected to any of the plane wirings.

(Supplementary Note 5) The circuit board includes at least two layers of plain wiring in an inner layer,
The semiconductor device according to appendix 1 or 2, wherein a plurality of openings are formed in a region where the through hole is not formed in a region corresponding to the third region of at least one of the plane wirings.

  (Supplementary note 6) The semiconductor device according to any one of supplementary notes 1 to 5, wherein the semiconductor chip is electrically connected to the circuit board by wire bonding with the pad.

(Additional remark 7) The said semiconductor chip is sealed in the mounting surface side of the said circuit board, The semiconductor device in any one of Additional remark 1 to 6 characterized by the above-mentioned.
(Appendix 8) A multilayer wiring circuit board;
A semiconductor chip mounted on the circuit board;
Have
The circuit board is
A first region in which the semiconductor chip is disposed;
A second region outside the first region and formed with a plurality of pads used for electrical connection with the semiconductor chip;
A third region between the first region and the second region;
At least two layers of plain wiring formed in the inner layer;
A non-conductor portion formed linearly in a region corresponding to the third region in the plane wiring;
A semiconductor device comprising:

  (Supplementary note 9) The supplementary note 8, wherein a plurality of bumps are selectively arranged outside the region corresponding to the third region on the side opposite to the arrangement surface side of the semiconductor chip. Semiconductor device.

(Supplementary note 10) The semiconductor device according to Supplementary note 8 or 9, wherein the semiconductor chip is electrically connected to the circuit board by wire bonding with the pad.
(Additional remark 11) The said semiconductor chip is sealed in the mounting surface side of the said circuit board, The semiconductor device in any one of Additional remark 8 to 10 characterized by the above-mentioned.

(Additional remark 12) In the circuit board of multilayer wiring,
A first region in which a semiconductor chip is disposed;
A second region outside the first region and formed with a plurality of pads used for electrical connection with the semiconductor chip;
A third region between the first region and the second region;
A through hole formed through the plurality of layers in the third region;
A circuit board comprising:

  (Supplementary note 13) The circuit according to Supplementary note 12, wherein a plurality of bumps are selectively disposed outside the region corresponding to the third region on the side opposite to the placement surface side of the semiconductor chip. substrate.

(Supplementary Note 14) The inner layer has at least two layers of plain wiring,
14. The circuit board according to appendix 12 or 13, wherein the through hole is electrically connected to one of the plane wirings.

(Supplementary Note 15) The inner layer includes at least two layers of plain wiring,
14. The circuit board according to appendix 12 or 13, wherein the through hole is not electrically connected to any of the plane wirings.

(Supplementary Note 16) The inner layer includes at least two layers of plain wiring,
14. The circuit board according to appendix 12 or 13, wherein a plurality of openings are formed in a region where the through hole is not formed in a region corresponding to the third region of at least one of the plane wirings.

It is a cross-sectional schematic diagram of a semiconductor device. It is a figure which shows an example of the outline of the formation flow of a circuit board. It is a principal part cross-sectional schematic diagram of an electroless-plating process. It is a principal part cross-sectional schematic diagram of an electroplating process. It is a principal part cross-sectional schematic diagram of an etching process. It is a principal part cross-sectional schematic diagram of a resist formation process. It is a principal part cross-sectional schematic diagram of a Ni / Au plating process. It is a principal part cross-sectional schematic diagram of an etch-back process. It is a figure which shows an example of the outline of the formation flow of a semiconductor device. It is a principal part cross-sectional schematic diagram of a dicing process. It is a principal part cross-sectional schematic diagram of a die-bonding process. It is a principal part cross-sectional schematic diagram of a wire bond process. It is a principal part cross-sectional schematic diagram of a sealing process. It is a principal part cross-sectional schematic diagram of a ball mounting process. It is a principal part cross-sectional schematic diagram of a reflow process. It is a principal part cross-sectional schematic diagram of a board | substrate cutting process. It is explanatory drawing of the process before shipment. It is the electron micrograph of a circuit board, (A) is a plane by the side of a solder ball connection side, (B) is a part in the XX section of (A), (C) is YY of (A). It is a part in a cross section. It is a plane schematic diagram of the circuit board before cutting, (A) is a figure showing a semiconductor chip mounting surface side, and (B) is a figure showing a solder ball connection surface side. The electron micrographs obtained at two different places on the circuit board after moisture absorption and heating / cooling treatment are schematically shown. It is an example of the measurement result of the curvature of the circuit board which generate | occur | produces at the time of a heating. It is a plane schematic diagram of power plane wiring. It is a plane schematic diagram of ground plane wiring. It is a plane schematic diagram of another power plane wiring. It is a plane schematic diagram of the power plane wiring which formed the mesh-like nonconductor part. It is a plane schematic diagram of the power plane wiring of the circuit board which the semiconductor device of 2nd Embodiment has.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,100 Semiconductor device 20,110,140 Circuit board 20a Center part 20b Middle part 20c Peripheral part 21,144 First wiring layer 21a Arrangement area 21b Circuit pattern 21c, 24a, 142a, 143 Pad 22, 145 Second wiring layer 22a , 81 Ground plane wiring 23, 112, 146 Third wiring layer 23a, 82 Power plane wiring 23b, 23c Non-conductive portion 24, 111, 147 Fourth wiring layer 25, 89, 153 Solder resist 26, 80, 148 Core layer 27 , 28, 83, 84, 113, 149, 150 Prepreg layer 29a, 29b Through hole 30 Semiconductor chip 40 Die bond film 50 Au wire 60 Mold resin 70, 120 Solder ball 85 Hole 86 Seed Cu film 87, 90 Resist 88 Cu film 9 Ni / Au plating film 92 wafer 93 dicer 94 shipping tray 95 seal 130 blister 141 die area 142 pad forming region 151, 152 separated portion

Claims (5)

A multilayer wiring circuit board;
A semiconductor chip mounted on the circuit board;
Have
The circuit board is
A first region in which the semiconductor chip is disposed ;
A second region outside the first region , wherein a plurality of pads wire-bonded to the semiconductor chip are provided on a surface side where the semiconductor chip is disposed ;
A third region between the first region and the second region;
A through hole provided through the plurality of layers in the third region;
I have a,
The circuit board includes at least two layers of plain wiring in an inner layer of the circuit board,
The through hole is electrically connected to one of the plane wirings,
A plurality of openings are provided in a region where the through hole is not formed in the third region of at least one of the plane wirings,
A plurality of bumps are selectively provided outside the third region on the surface of the circuit board opposite to the surface on which the semiconductor chip is disposed.
A semiconductor device.   A multilayer wiring circuit board;
  A semiconductor chip mounted on the circuit board;
  Have
  The circuit board is
  A first region in which the semiconductor chip is disposed;
  A second region outside the first region, wherein a plurality of pads wire-bonded to the semiconductor chip are provided on a surface side where the semiconductor chip is disposed;
  A third region between the first region and the second region;
  A through hole provided through the plurality of layers in the third region;
  Have
  The circuit board includes at least two layers of plain wiring in an inner layer of the circuit board,
  The through hole is not electrically connected to any of the plane wirings,
  A plurality of openings are provided in a region where the through hole is not formed in the third region of at least one of the plane wirings,
  A plurality of bumps are selectively provided outside the third region on the surface of the circuit board opposite to the surface on which the semiconductor chip is disposed.
  A semiconductor device.   The semiconductor device according to claim 1, wherein the semiconductor chip is sealed with a resin on the circuit board. In circuit boards with multilayer wiring,
A first region in which a semiconductor chip is disposed;
A second region provided outside the first region and provided with a plurality of first pads wire-bonded to the semiconductor chip on a surface side where the semiconductor chip is disposed ;
A third region between the first region and the second region;
A through hole provided through the plurality of layers in the third region;
I have a,
The inner layer has at least two layers of plain wiring,
The through hole is electrically connected to one of the plane wirings,
A plurality of openings are provided in a region where the through hole is not formed in the third region of at least one of the plane wirings,
A plurality of second pads to which a plurality of bumps are respectively connected are provided on the side opposite to the surface on which the semiconductor chip is disposed, and selectively outside the third region.
A circuit board characterized by that.   In circuit boards with multilayer wiring,
  A first region in which a semiconductor chip is disposed;
  A second region provided outside the first region and provided with a plurality of first pads wire-bonded to the semiconductor chip on a surface side where the semiconductor chip is disposed;
  A third region between the first region and the second region;
  A through hole provided through the plurality of layers in the third region;
  Have
  The inner layer has at least two layers of plain wiring,
  The through hole is not electrically connected to any of the plane wirings,
  A plurality of openings are provided in a region where the through hole is not formed in the third region of at least one of the plane wirings,
  A plurality of second pads to which a plurality of bumps are respectively connected are provided on the side opposite to the surface on which the semiconductor chip is disposed, and selectively outside the third region.
  A circuit board characterized by that.

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