WO2025120086A1 - Component package having a hybrid semiconductor chip - Google Patents

Abstract

The invention relates to a component package, in particular a laser package, comprising a first semiconductor chip having a first main face and a second main face opposite the first. The first semiconductor chip comprises a first layer, which is adjacent to the first main face and comprises a photonically integrated element, wherein the first layer has at least one light in-coupling surface, at least one light out-coupling surface, and at least one waveguide connecting the at least one light in-coupling surface and the at least one light out-coupling surface. The first semiconductor chip also comprises a second layer, which is adjacent to the second main face and comprises an integrated circuit that is decoupled from the photonically integrated element, and a large number of contact pads on the second main face, which are provided for connection to a substrate, in particular a PCB or a second semiconductor chip. The component package also comprises a first optoelectronic component, in particular a laser chip, which is designed to emit light of a first wavelength from at least one first emission surface, wherein the at least one first emission surface is arranged opposite the at least one light in-coupling surface.

Description

Component package with a hybrid semiconductor chip

The present application claims priority from German patent application No. 10 2023 134 453 . 6 of December 8, 2023, the disclosure of which is hereby incorporated by reference into the present application.

The present invention relates to a component package with a hybrid semiconductor chip, which comprises a photonically integrated element and an integrated circuit.

BACKGROUND

Laser packages play an important role in the development of electronic devices and systems designed to project/emit laser light. In particular, in the field of virtual reality (VR) and augmented reality (AR), laser packages play an important role in things like smart glasses or so-called AR or VR glasses, where they are used to generate holographic images to provide the user with an immersive experience. In the past, laser packages were mainly used in industrial applications where size and weight are not particularly critical. However, they are now increasingly used in consumer devices such as AR and VR glasses. It is therefore crucial that manufacturers develop smaller laser packages and associated driver circuits suitable for these applications.

However, the size of these components, especially in combination with a driver circuit to power the laser package, has so far been a challenge for use in AR and VR headsets. Current laser packages combined with a driver circuit to power the laser package are too large to be discreetly integrated into AR and VR headsets. This poses a problem for developers and manufacturers, as they require smaller components to reduce the size and weight of the headsets. There is therefore a need to provide a laser package comprising associated driver electronics with which at least some of the problems mentioned above can be eliminated.

SUMMARY OF THE INVENTION

This need is met by the subject matter of the independent patent claims. Further developments and embodiments of the proposed principle are specified in the subclaims.

To solve the problem mentioned, the inventor proposes an integrated component package with a hybrid semiconductor chip which, on the one hand, comprises a photonically integrated element and an integrated circuit. In addition, the component package comprises an optoelectronic component, in particular a laser, which is arranged and designed to couple laser light into the photonically integrated element and, in particular, to be controlled by means of the integrated circuit. By means of the photonically integrated element, for example, light emitted by the optoelectronic component can be guided and, for example, a plurality of adjacent emission points emitted by the optoelectronic component can be brought closer together so that the emission points are as close to one another as possible when they exit the photonically integrated element. The hybrid design of the semiconductor chip, so that it fulfills multiple functions, serves to increase the integration of the component package and enables a very compact and closely spaced arrangement of the integrated circuit and optoelectronic component, eliminating the need for (long) wire connections between the integrated circuit and the optoelectronic component. This makes it possible, for example, to keep the system impedance low in the analog high-frequency range, thus enabling faster switching speeds/control speeds of the optoelectronic component. According to a first aspect, a component package, in particular a laser package, is provided. The component package comprises a first semiconductor chip with a first main side and an opposite second main side. The first semiconductor chip comprises a first layer adjacent to the first main side, which comprises a photonic integrated element or a photonic integrated circuit (PIC), and a second layer adjacent to the second main side, which comprises an integrated circuit (IC), such as an application-specific integrated circuit (ASIC), which is decoupled from the photonic integrated element.

The first layer or the photonically integrated element has at least one light coupling surface, at least one light output surface, and at least one optical fiber connecting the at least one light coupling surface and the at least one light output surface. In particular, the photonically integrated element can be designed to process and/or guide light coupled in via the at least one light coupling surface and subsequently to output it via the at least one light output surface.

A plurality of contact pads are formed on the second main side of the first semiconductor chip, in particular in the form of a ball grid array (BGA), which is intended for connection to a carrier, in particular a PCB, or a second semiconductor chip. Such a design enables SMD assembly of the first semiconductor chip, since the connections are located compactly on the underside of the semiconductor chip.

The component package also comprises a first optoelectronic component, in particular a laser chip, which is designed to emit light of a first wavelength from at least one first emission surface. The first optoelectronic component is arranged relative to the first semiconductor chip in such a way that the at least one first emission surface of the first optoelectronic component the at least one light coupling surface is opposite the first layer of the first semiconductor chip.

According to some aspects, the contact pads are in the form of small solder balls that are arranged next to one another in a grid of columns and rows (array). These balls are melted during reflow soldering in a soldering oven and connect to contact pads or contact areas on, for example, a carrier or another semiconductor chip. This design represents a solution to the problem of accommodating a very large number of connections on a component. This also means that the first semiconductor chip can be removed (desoldered) from the carrier without being damaged, even if it is soldered over the entire surface, e.g. with hot air. The first semiconductor chip can then be freed from the old solder balls (deballed), cleaned, and re-beaded with new solder balls. It can then be soldered again onto a new carrier or semiconductor chip. For example, when repairing a component package, a defective semiconductor chip can be replaced.

According to some aspects, the first semiconductor chip has a cavity or recess in which the first optoelectronic component is at least partially arranged. In particular, the at least one light coupling surface is arranged in a side surface of the first semiconductor chip formed by the cavity or recess. For example, the at least one light coupling surface can lie in a side surface of the first semiconductor chip that is formed by the cavity or recess or is formed by producing the cavity or recess.

The fact that the first optoelectronic component is arranged at least partially in the cavity or recess of the first semiconductor chip can be understood in particular in such a way that the first optoelectronic component is arranged completely, i.e. to the full extent, in the cavity or recess of the first semiconductor chip, or projects regionally beyond the cavity or recess, but is arranged at least partially in the cavity or recess. According to some aspects, the first optoelectronic component is arranged on a bottom of the cavity or recess. The bottom of the cavity or recess can be formed, in particular, by a surface of the first semiconductor chip arranged opposite an opening of the cavity or recess. In particular, the bottom of the cavity can be formed by a surface of the first semiconductor chip that is substantially parallel to the first or second main side.

According to some aspects, the first optoelectronic component is arranged on a submount. For example, the first optoelectronic component can be arranged on a submount that is arranged adjacent to the first semiconductor chip. However, the submount can also be arranged on the first main side of the first semiconductor chip, in particular in such a way that the first optoelectronic component is arranged at least partially in the cavity or recess of the first semiconductor chip. For this purpose, the submount with the first optoelectronic component arranged thereon can be arranged on the first main side of the first semiconductor chip in such a way that the first optoelectronic component points in the direction of the first semiconductor chip and projects into the cavity or recess of the first semiconductor chip.

Such a submount may be provided, for example, to provide a heat sink and/or an electrical supply for the first optoelectronic component, and/or to provide a further semiconductor chip that provides further functionality of the component package. Such a semiconductor chip may, for example, comprise at least one layer with an integrated circuit.

According to some aspects, the component package further comprises a second optoelectronic component, in particular a laser chip, which is arranged on the first main side and which is designed to emit light of a second wavelength from at least one second emission surface. In particular, the second optoelectronic component is arranged on the first main side in such a way that the at least a second emission surface and the at least one light output surface of the first layer of the first semiconductor chip are arranged adjacent to one another. The first semiconductor chip can in particular serve as a submount for the second optoelectronic component and can be arranged such that the at least one second emission surface and the at least one light output surface of the first layer of the first semiconductor chip are arranged as closely as possible to one another. In particular, a distance perpendicular to the first main side between the at least one second emission surface and the at least one light output surface can be less than 50 pm, less than 25 pm, or less than 10 pm. In particular, the second emission surface and the at least one light output surface of the first layer can lie essentially in a common plane or at least in two planes that are only insignificantly spaced from one another.

The light having the first wavelength emitted by the first optoelectronic component may, in particular, differ from the light having the second wavelength emitted by the second optoelectronic component. For example, the light having the first wavelength may be red light, and the light having the second wavelength may be green or blue light. However, this is merely an example, and each may just as well be light of a different wavelength.

The at least one second emission surface of the second optoelectronic component and the at least one light output surface of the first layer of the first semiconductor chip can in particular each form an emission surface or an emission point of light of a corresponding wavelength of the component package. The emission points of all optoelectronic components and thus of the light of all wavelengths can in particular be arranged in close proximity to one another. This creates a virtual point light source, so to speak. The proximity of the emission points enables a simplification of possible downstream optical element(s), which for example enable collimation of all emission points by just one optical element. According to some aspects, the first optoelectronic component is designed to emit light substantially of the first wavelength from at least two first emission surfaces, wherein the at least two first emission surfaces are spaced apart from one another by a first distance. In particular, the first optoelectronic component can be formed by an edge-emitting laser chip which has one or more laser ridges or laser resonators, each with a laser facet located at the end of the resonator. A laser chip with a plurality of laser ridges or laser resonators can in particular be referred to as a multi-ridge laser. All laser ridges can be individually controllable in order to enable desired colors and gray levels when generating an image with multiple pixels using the component package.

According to some aspects, the at least two first emission surfaces are each arranged opposite an associated light coupling surface of the first layer. The first layer can also have at least two light output surfaces and a light guide connecting the at least two light input surfaces and the at least two light output surfaces, wherein the at least two light output surfaces are spaced apart from one another by a second distance. The first distance can essentially correspond to the second distance, or the second distance can be smaller than the first distance. In particular, it can be advantageous for the second distance to be smaller than the first distance. In particular, light-generating structures of the first optoelectronic component, such as a plurality of laser bars, can be spaced apart from one another by a first distance in such a way that excessive heating of the first optoelectronic component during its intended use is prevented. At the same time, the light emitted from the first emission surfaces spaced apart by the first distance can be directed by means of the first layer or the photonically integrated element in such a way that the light is coupled out of the light output surfaces spaced apart by a smaller second distance. Accordingly, the distance between light-generating structures of the first optoelectronic component can be reduced to improve heat dissipation and increase the efficiency of the first optoelectronic component. be chosen larger, while the emission points emitted by the light of the first optoelectronic component can be located close together by the photonically integrated element.

According to some aspects, the second optoelectronic component is designed to emit light substantially of the second wavelength from at least two second emission surfaces. The at least two second emission surfaces can be spaced apart from one another by a third distance, wherein in particular the third and the second distance are substantially identical. In the case of the second optoelectronic component, for example, a cooling problem as described for the first optoelectronic component may not represent a significant limitation, so that a closer arrangement of light-generating structures of the second optoelectronic component and thus of the second emission surfaces is less problematic and a merging of the emission points is not necessary. Rather, a close arrangement of the emission points generated by means of the second optoelectronic component can already be achieved by a closer arrangement of the light-generating structures of the second optoelectronic component and thus of the second emission surfaces.

According to some aspects, the component package further comprises a third optoelectronic component, in particular a laser chip, which is arranged on the first main side adjacent to the second optoelectronic component or in the cavity or recess adjacent to the first optoelectronic component. The third optoelectronic component is in particular designed to emit light of a third wavelength from at least one third emission surface, which can differ from the first and the second wavelength. For example, the first, second and third optoelectronic components can be designed to emit light in the colors red, green and blue and accordingly form an RGB package. However, it is also possible for the first, second and third optoelectronic components to emit light of a different wavelength or each to emit light of substantially the same wavelength. According to some aspects, the first optoelectronic component is further away from the second and third optoelectronic components than a distance between the second and third optoelectronic components. This can be selected in particular such that the emission properties of the first optoelectronic component can be more dependent on the heating of the first optoelectronic component compared to the second and third optoelectronic components. Accordingly, it can be desirable to arrange the first optoelectronic component further away from the second and third optoelectronic components, such that the emission properties of the first optoelectronic component are not influenced or not significantly influenced by heating of the second and third optoelectronic components.

According to some aspects, the first layer or the photonically integrated element as well as the optoelectronic component(s) can be designed such that the light of the emitted wavelength(s) has the same emission pattern. In particular, the first layer or the photonically integrated element as well as the optoelectronic component(s) can be designed to emit light through the light output surface(s) or emission surface(s) that has a substantially identical slow and fast axis divergence. This can be particularly advantageous in order to avoid color fringes after a combination of light of different wavelengths in, for example, a laser beam scanning system (LBS).

According to some aspects, the first semiconductor chip has a plurality of first vias, in particular silicon vias, which connect at least the first and/or second and/or third optoelectronic component to the integrated circuit and/or to at least one of the plurality of contact pads. In particular, the first semiconductor chip can have a plurality of TSVs (Through Silicon Vias) in order to connect the first and/or second and/or third optoelectronic component, for example in the form of a flip-chip laser chip, to the integrated circuit and/or to at least one of the plurality of contact pads. By means of such By contacting the first and/or second and/or third optoelectronic component, an electrical interface between the first semiconductor chip and the first and/or second and/or third optoelectronic component can be realized without wire connections. This helps to reduce the impedance of the component package and enables efficient high-frequency modulation of the optoelectronic component(s).

According to some aspects, the component package further comprises a second semiconductor chip on which the first semiconductor chip is arranged. The second semiconductor chip has at least one layer comprising an integrated circuit that is electrically coupled to the first semiconductor chip. The second semiconductor chip can have a multiplicity of second vias, in particular silicon vias, which connect the integrated circuit of the second semiconductor chip to a multiplicity of contact areas on one or more main sides of the second semiconductor chip. For example, the first semiconductor chip or contact pads of the first semiconductor chip can be arranged on the contact areas or a subset of the contact areas and can be electrically connected to them.

The first semiconductor chip can, in particular, be stacked on a further semiconductor chip comprising an integrated circuit, wherein the further semiconductor chip has driver functions and is connected to the first semiconductor chip. The second semiconductor chip can, for example, serve as a base plate for the first semiconductor chip and the optoelectronic component(s).

According to some aspects, the component package further comprises a hermetic encapsulation, in particular a hermetically sealing cap, which is arranged on the second semiconductor chip. In particular, a hermetically sealed cavity can be formed by an inorganic cap on the second semiconductor chip, in which the first semiconductor chip and the optoelectronic component(s) can be arranged. The hermetically sealing cap can in particular be used for the The wavelength emitted by the optoelectronic component(s) must be transparent or translucent on at least one side, which is used to extract the light from the component package. Both a lateral emitting configuration, i.e. in the direction of the main propagation direction of the second semiconductor chip, and an upward emitting configuration, i.e. in a direction perpendicular to a main side of the second semiconductor chip, are possible.

According to some aspects, the component package further comprises a carrier, in particular a PCB, on which the first and/or second semiconductor chip are arranged.

According to some aspects, the component package further comprises a plurality of first passive electrical components, such as resistors, thermistors (NTC), ESD protection diodes, capacitors and/or inductors, which are arranged on the second semiconductor chip and/or on the carrier and are each electrically connected to the second semiconductor chip and/or the carrier.

According to some aspects, the component package further comprises a plurality of bond wires that electrically connect the carrier to contact pads of the second semiconductor chip and/or to contact pads on the first main side of the first semiconductor chip. Such bond wires can be provided in addition to or as an alternative to the first and second vias. For example, passive electrical components and/or the optoelectronic component(s) can be electrically connected to the first semiconductor chip and/or the carrier by means of additional bond wires or merely by means of bond wires.

According to some aspects, the component package further comprises a third semiconductor chip and/or at least one second passive electrical component, such as a resistor, a capacitor and/or an inductor, which is integrated into the carrier, in particular on a side opposite the first semiconductor chip. This additionally allows the space requirement in the lateral direction of a Such component packages can be greatly reduced compared to individual components arranged side by side.

According to some aspects, the component package further comprises a plurality of third vias, in particular metallic vias, through the carrier, which electrically contact the third semiconductor chip and/or the at least one second passive electrical component. By means of the third vias, the second semiconductor chip and/or the at least one second passive electrical component can be electrically connected to the first semiconductor chip in a space-saving manner, for example. The second semiconductor chip can be designed according to the aspects of the first semiconductor chip and in particular can comprise at least one layer with an integrated circuit which is electrically connected to at least parts of the third vias.

According to some aspects, the second semiconductor chip comprises at least two layers arranged one above the other, each containing an integrated circuit. The second semiconductor chip can comprise correspondingly stacked layers, each containing an integrated circuit. Between the layers there can be, for example, an intermediate or compensating layer through which fourth vias run, which electrically couple the layers arranged one above the other, each containing an integrated circuit. In particular, the fourth vias can therefore also be called IC-IC vias. For example, such an arrangement can also result from two separate integrated circuits being stacked on top of one another with their active area facing one another, and an intermediate or compensating layer being arranged between the two circuits.

According to some aspects, the component package further comprises an optical element, in particular a lens, which is arranged on the second semiconductor chip downstream of the first semiconductor chip in the light emission direction of the first optoelectronic component. By arranging the optical element on the second semiconductor chip, on which the first semiconductor chip or the first optoelectronic component, thermal stresses within the component package can have no or only a minimal negative effect on the position of the optical element relative to the first semiconductor chip or the first optoelectronic component. This can be due, among other things, to the fact that the optical element is arranged on the same continuous material as the first semiconductor chip or the first optoelectronic component and also to the fact that the second semiconductor chip can have a relatively high rigidity and thus provides an optical bench with high rigidity and low GTE for the arrangement of the first semiconductor chip or first optoelectronic component and optical element. In addition, by placing the optical element and the first semiconductor chip or first optoelectronic component on the second semiconductor chip, the space requirement in the lateral direction of such a component package can be greatly reduced compared to individual components arranged next to one another.

The first semiconductor chip can in particular serve as a submount for light emitted from the at least one light output surface and from emission surfaces of further optoelectronic components. This can be advantageous, for example, in combination with an optical element arranged downstream of the at least one light output surface and emission surfaces in the light emission direction, since an increase can prevent or at least reduce so-called beam clipping of the emitted light. In addition, it also allows greater flexibility in selecting the optical element with regard to, for example, size, optical properties and material, as well as greater flexibility with regard to the arrangement of the optical element with regard to the distance between the optical element and the first semiconductor chip.

According to some aspects, the first semiconductor chip comprises a substrate layer made of a semiconductor material, in particular Si, which is free of an integrated circuit. Furthermore, the first semiconductor chip may comprise a leveling layer that, for example, levels out unevenness within or on the first and/or second main side. According to some aspects, the component package further comprises a heat sink which is arranged on the first and/or second semiconductor chip and/or the carrier. It is also conceivable that the component package additionally or alternatively comprises a heat extraction layer which is arranged between the first semiconductor chip and the optoelectronic component(s) and/or between the first semiconductor chip and the second semiconductor chip and/or between the second semiconductor chip and the carrier and/or between the layers of the first semiconductor chip. Such a heat sink and/or such a heat extraction layer can in particular be designed to store and/or dissipate heat generated during operation of the component package in order to prevent overheating and the associated change in the operating conditions of the component package or, in extreme cases, even failure of the component package.

BRIEF DESCRIPTION OF THE DRAWINGS

Further aspects and embodiments according to the proposed principle will become apparent with reference to the various embodiments and examples which will be described in detail in conjunction with the accompanying drawings.

Figures 1A to 1C show a side, a top and a front view of a component package according to some aspects of the proposed principle;

Figures 2A to 6C show side, top and front views of another component package according to some aspects of the proposed principle; and

Figures 7A to 8B show side views and top views of another component package according to some aspects of the proposed principle.

DETAILED DESCRIPTION The following embodiments and examples show various aspects and their combinations according to the proposed principle. The embodiments and examples are not always to scale. Likewise, various elements can be shown enlarged or reduced in size to emphasize individual aspects. It goes without saying that the individual aspects and features of the embodiments and examples shown in the figures can be combined with one another without thereby impairing the inventive principle. Some aspects have a regular structure or shape. It should be noted that in practice slight deviations from the ideal shape can occur without, however, contradicting the inventive idea.

Furthermore, the individual figures, features, and aspects are not necessarily shown in the correct size, and the proportions between the individual elements may not always be correct. Some aspects and features are emphasized by being shown larger. However, terms such as "top", "above", "below", "below", "larger", "smaller", and the like are correctly represented in relation to the elements in the figures. This makes it possible to infer such relationships between the elements from the illustrations.

Figures 1A to 1C show a first embodiment of a component package 1 according to some aspects of the proposed principle. The component package comprises a first semiconductor chip 2a with a first main side 3a and a second main side 3b opposite the first. The first semiconductor chip 2a has a first layer 10a adjacent to the first main side 3a, which comprises a photonically integrated element, wherein the first layer 10a has light coupling surfaces 13a, light output surfaces 13c, and light guides 13b connecting the light coupling surfaces 13a and the light output surfaces 13c. The first semiconductor chip 2a also has a second layer 10b adjacent to the second main side 3b, which comprises an integrated circuit. The integrated circuit is decoupled from the photonically integrated element and serves to control the Component packages, in particular optoelectronic component(s) of the component package.

On the second main side 3b of the first semiconductor chip 2a, a plurality of contact pads 4 are formed in the form of a ball grid arrangement, which are provided for connection to, for example, a carrier, in particular a PCB, or a second semiconductor chip.

The component package 1 also comprises a first optoelectronic component 5a, in particular a laser chip, which is designed to emit light of a first wavelength from a plurality of first emission surfaces 12a. In the illustrated case, the optoelectronic component 5a is arranged adjacent to the first semiconductor chip 2a on a submount 15 such that the first emission surfaces 12a are opposite the light coupling surfaces 13a of the photonically integrated element.

The core of the invention is the hybrid-designed first semiconductor chip 2a, which, on the one hand, provides a photonically integrated element by means of which light coupled into the light coupling surfaces 13a can be guided and/or processed, while the first semiconductor chip additionally provides an integrated circuit that serves to control the component package. Accordingly, this results in a compact system by means of which light emitted by the first optoelectronic component 5a can be emitted at a different location and optionally with a different emission pattern.

In the illustrated case, the first optoelectronic component 5a is designed as an edge-emitting laser chip with three laser ridges (represented by the dash-dot line), which is designed to couple laser light of essentially the same wavelength into light coupling surfaces of the photonically integrated element via three emission surfaces 12a. The photonically integrated element is then designed to guide the coupled-in light along the light guides 13b and to couple it out again at the light coupling surfaces 13c. For example, the photonically integrated element can be designed to It may be possible to combine light coupled in at a greater distance from one another so that it is coupled out via three very closely spaced light coupling surfaces 13c, thus resulting in a virtual point light source (shown in Figure 4B). This may be particularly advantageous if the emission points located close to one another are to be deflected by means of a small optical system, for example in order to provide an LBS system. In this case, it may be particularly advantageous if the individual laser resonators can be controlled individually.

The number of laser bridges or emission surfaces, light coupling surfaces, light guides and light output surfaces is to be understood as exemplary and can vary in any direction.

Figures 2A to 2C show a further embodiment of a component package 1 according to some aspects of the proposed principle. The first optoelectronic component 5a is not arranged on a separate submount 15 but on the bottom 3d of a cavity 8 in the first semiconductor chip 2a. The light coupling surfaces 13a are arranged in a side surface 3c which is formed by the cavity. In addition, the cavity 8 has a depth such that the emission surfaces 12a and the light coupling surfaces 13a lie opposite one another.

The embodiment shown has the advantage that the first optoelectronic component 5a is arranged directly on the first semiconductor chip 2a and can be electrically connected to the integrated circuit by means of first vias 9a. This eliminates the need for conductor tracks for contacting the first optoelectronic component 5a, thereby reducing the impedance of the component package and enabling faster switching frequencies (e.g., 0.2 GHz) of the first optoelectronic component 5a to be realized.

Figures 3A to 3C show a further embodiment of a component package 1 according to some aspects of the proposed principle. The first optoelectronic component 5a is not in a cavity, but on the bottom 3d of a rearwardly open recess 8 in the first semiconductor chip 2a. In addition, the first semiconductor chip 2a is at least partially electrically connected to the integrated circuit by means of a conductor track 11. The first optoelectronic component 5a can accordingly also be designed so that it can be contacted vertically, so that electrical contact must be provided separately from a side opposite the base 3d. The embodiment shown in Figures 3A to 3C is intended in particular to suggest by way of example the design options for the individual elements covered by the application, which elements can be combined with one another in any embodiment. It should also be understood that the application is not intended to be limited to the design options shown, but that these merely indicate exemplary design options.

Figures 4A to 4C show a further embodiment of a component package 1 according to some aspects of the proposed principle. The component package 1 comprises, in addition to the first optoelectronic component 5a, a second and a third optoelectronic component 5b, 5c, which are arranged adjacent to one another on the first main side 3a of the first semiconductor chip 2a. The second and third optoelectronic components 5b, 5c are designed to emit light of a second and third wavelength through second and third emission surfaces 12b, 12c, respectively. In addition, the second and third optoelectronic components 5b, 5c are arranged on an edge region of the first semiconductor chip 2a and, in particular, are essentially flush with a side surface of the first semiconductor chip 2a. This has the consequence that the emission surfaces 12b, 12c lie essentially in the same plane as the light output surfaces 13c of the photonically integrated element, and that so-called beam clipping of the light L emitted by the optoelectronic components is prevented or at least reduced. The second and third optoelectronic components 5b, 5c are also designed and arranged on the first main side 3a of the first semiconductor chip 2a in such a way that the emission surfaces 12b, 12c and the light output surfaces 13c of the photonically integrated element lie very close to one another and This results in a virtual point light source. This can be particularly advantageous if the emission points located close to one another are to be redirected using a small optic, for example to provide an LBS system.

The photonically integrated element and the optoelectronic components can in particular be designed and arranged such that the emission surfaces 12b, 12c and the light output surfaces 13c of the photonically integrated element are spaced from one another in a direction perpendicular to the first main side 3a of the first semiconductor chip 2a, i.e. in the vertical direction, by a distance of less than 50 pm or less than 25 pm. In addition, the photonically integrated element and the optoelectronic components can in particular be designed and arranged such that the emission surfaces 12b, 12c and the light output surfaces 13c of the photonically integrated element are also spaced from one another in the horizontal direction by a distance of less than 50 pm or less than 25 pm. The associated emission surfaces 12b, 12c and light output surfaces 13c of an optoelectronic component or of the photonically integrated element can in particular be spaced apart by a distance of less than 10 pm or less than 5 pm.

The second and third optoelectronic components 5b, 5c can also be electrically connected to the integrated circuit by means of first vias 9a. This eliminates the need for conductor tracks for contacting the second and third optoelectronic components 5b, 5c, thereby reducing the impedance of the component package and enabling faster switching frequencies (e.g., 0.2 GHz) of the optoelectronic components to be realized.

As already mentioned, Figure 4B also shows a possible functionality of the photonically integrated element, according to which the photonically integrated element can be designed to combine light coupled in at a greater distance from one another, so that it is coupled out via three very closely spaced light coupling surfaces 13c, thus resulting in a virtual point light source. This can be particularly advantageous for laser bars of the The first optoelectronic component 5a can be designed further apart from one another in order to better dissipate heat during their intended use. At the same time, however, thanks to the photonically integrated element, the final emission points can still be very close to one another.

Figures 5A to 5C show a further embodiment of a component package 1 according to some aspects of the proposed principle. In comparison to the embodiment shown in Figures 4A to 4C, only the second optoelectronic component 5b is arranged on the first main side 3a of the first semiconductor chip 2a, and the third optoelectronic component 5c is arranged on the bottom 3d of the cavity 8 next to the first optoelectronic component 5a. The photonically integrated element accordingly has further light coupling surfaces 13a, light coupling surfaces 13c, and light guides 13b connecting the light coupling surfaces 13a and the light coupling surfaces 13c in order to guide the light emitted by the second optoelectronic component 5b.

However, the number and arrangement of the optoelectronic components is to be understood merely as an example, and more or fewer optoelectronic components than those shown can also be provided and arranged in any number on the first main side 3a of the first semiconductor chip 2a and/or on the bottom 3d of the cavity 8 or recess next to the first optoelectronic component 5a. Preferably, however, the optoelectronic components and the photonically integrated element are designed and arranged such that the emission points of the light emitted by the component package are as close to one another as possible.

Figures 6A to 6C show a further embodiment of a component package 1 according to some aspects of the proposed principle. In comparison to the embodiments shown in Figures 2A to 5C, the first optoelectronic component 5a is not arranged on the bottom 3d of a cavity or recess in the first semiconductor chip, but is arranged by means of a submount 15 on the first main side 3a of the first semiconductor chip 2a in such a way that the first optoelectronic component 5a projects into the cavity 8, but does not necessarily touch the bottom 3d of the cavity. The submount 15 can serve, on the one hand, for electrically contacting the first optoelectronic component 5a and for cooling the first optoelectronic component 5a during its operation.

For this purpose, as also shown in Figures 7a and 8A, the submount 15 can be electrically coupled to the integrated circuit of the first semiconductor chip 2a by means of first vias 9a. Contacting of the first optoelectronic component 5a can, for example, be effected solely via the submount 15, or a contacting option can also be provided between the base 3d of the cavity 8 and the first optoelectronic component 5a.

By means of a configuration as shown, the submount 15 or contact paths integrated therein can be in direct contact with the laser bars of the first optoelectronic component 5a in order to ensure optimal heat dissipation of the first optoelectronic component 5a during its operation.

Figures 7A and 7B show a further embodiment of a component package 1 according to some aspects of the proposed principle. The component package 1 comprises a carrier 6 on which a second semiconductor chip 2b is arranged. On the second semiconductor chip 2c there is in turn arranged a first semiconductor chip 2a which has a first layer 10a comprising a photonically integrated element and a second layer 10b comprising an integrated circuit. In addition, the component package 1 has a first optoelectronic component 5a which is arranged on the first semiconductor chip 2a or integrated therein in such a way that light coupled out from first emission surfaces 12a is coupled into light coupling surfaces 13a of the photonically integrated element. In addition, the component package 1 has a second and a third optoelectronic component 5b, 5c, which are arranged on a first main side 3a on the first semiconductor chip 2a and which are designed to emit light via second and third emission surfaces 12b, 12c. In the illustrated case, the component package 1 is designed, in particular, to emit light L of the colors red, green, and blue, or any color that can be mixed therewith, by means of the optoelectronic components 5a, 5b, 5c. In particular, the module arranged on the second semiconductor chip 2b, comprising the first semiconductor chip 2a and the optoelectronic component(s), can be designed according to one of the aforementioned embodiments.

The said module is covered on the second semiconductor chip 2b by means of a hermetically sealing cap 17 which, together with the second semiconductor chip, forms a hermetically sealed cavity in which the module is arranged. The cap is designed to be transparent to the light emitted by the optoelectronic component(s), so that the light L can pass through the cap without being substantially influenced by it. The cap can be particularly advantageous for increasing the service life of the optoelectronic component(s) during operation of the component package 1 by preventing foreign bodies from settling on the emission surfaces of the optoelectronic component(s). In order to be able to form a hermetically sealed cavity with the second semiconductor chip 2b, a connecting region can be provided between the cap 17 and the second semiconductor chip 2b, which connecting region is free of organic material and exerts a sealing effect between the cap 17 and the second semiconductor chip 2b. In addition, the second semiconductor chip 2b or a surface of the second semiconductor chip located within the hermetically sealed cavity can also be free of organic material in order to prevent particles of the organic material from settling on the emission surfaces of the optoelectronic component(s) and leading to degradation thereof.

The second semiconductor chip 2b has a layer with an integrated circuit 8, which is electrically connected to the carrier 6 for its power supply. The layer with the integrated circuit is indicated by the dashed line. An electrical connection to the carrier 6 can be made via second vias 9b directly or via bonding wires 11. In addition, the second semiconductor chip has on a main side facing the first semiconductor chip Contact surfaces 16 which are at least partially in electrical contact with the contact pads 4 of the first semiconductor chip 2a. Furthermore, first passive electrical components 18a are arranged on the second semiconductor chip 2b and on the carrier 6, which are each electrically connected to the second semiconductor chip 2b and to the carrier 6 and contribute partial functionality to the operation of the component package 1. The term "operation of the integrated component package" is to be understood as meaning both an electrical supply and a signaling control of the component package. The positioning and number of the first passive electrical components 18a and the bond wires 11, as well as the contact surfaces, are to be understood as examples and can vary depending on the design and application of the component package 1. By using bonding wires 11 alternatively or in addition to vias 9b through the second semiconductor chip 2b, the design and implementation of the second semiconductor chip 2b itself can be simplified, since no or at least fewer vias through the second semiconductor chip 2b are necessary.

By stacking the carrier 6, the second semiconductor chip 2b, the first semiconductor chip 2a, the optoelectronic components, and the passive electrical components 18a, it is possible to design the component package 1 in the most space-saving way possible compared to a design in which the individual components are arranged side by side and must be electrically connected to one another by laterally extending contact lines. Furthermore, such an integrated module can be installed and connected in a designated application easily and without any further complex subsequent processes.

The component package 1 also has a third semiconductor chip 2c and second passive electrical components 18b, which are integrated into the carrier 6 on a side opposite the first semiconductor chip 2a. The carrier 6 has recesses in which the components or the semiconductor chip are arranged. In addition, third vias 9c are provided through the carrier, by means of which an electrical contact is passed through the carrier 6 in order to connect the third semiconductor chip 2c and the second passive electrical components 18b from the side facing the first semiconductor chip 2a. Such an arrangement allows the space requirement of the component package 1 to be further reduced in the lateral direction.

Figures 8a and 8B show an embodiment of a component package 1 which additionally comprises an optical element 14. The optical element 14 is arranged downstream of the first semiconductor chip 2a or the optoelectronic components in the light emission direction L on the second semiconductor chip 2b. The optical element 14 can in particular be a passive optical element such as one or more lenses which shape, scatter or deflect/redirect the light emitted by the optoelectronic components. However, it is also conceivable for the optical element 14 to be formed by an active optical element which actively shapes, scatters or in particular deflects/redirects the light emitted by the optoelectronic components. For example, the optical element 14 can also be formed by a prism which deflects the emitted light in a direction perpendicular to the second semiconductor chip 2b.

By arranging the optical element 14 on the second semiconductor chip 2b, on which the first semiconductor chip and the optoelectronic components are also arranged, thermal stresses within the component package 1 can have no or only a minimal negative effect on the position of the optical element 14 relative to the optoelectronic components. This can be due, among other things, to the fact that the optical element 14 is arranged on the same continuous material as the first semiconductor chip 2a or the optoelectronic components and also to the fact that the second semiconductor chip 2b can have a relatively high rigidity and thus provides an optical bench with high rigidity and low GTE for the arrangement of optoelectronic components and optical element 14. In addition, by placing the optical element 14 and the optoelectronic components on the second semiconductor chip chip 2b the space requirement in the lateral direction of such a component package 1 can be greatly reduced compared to individual components arranged next to one another.

LIST OF REFERENCE SYMBOLS

1 component package

2a, 2b, 2c semiconductor chip

3a, 3b main page

3c side surface

4 contact pad

5a, 5b, 5c optoelectronic component

6 carriers

7a, 7b passive electrical component

8 Cavity

9a, 9b, 9c through-hole plating

10a, 10b Location

11 Bonding wire

12a, 12b, 12c emission surface

13a Coupling area

13b Fiber optic cable

13c From coupling area

14 optical element

15 submounts

16 Contact area

17 cap

18a, 18b passive electrical component

L Light

Claims

PATENT CLAIMS 1. Component package (1), in particular a laser package, comprising: a first semiconductor chip (2a) with a first main side (3a) and a second main side (3b) opposite the first, o which has a first layer (10a) adjacent to the first main side (3a), which comprises a photonically integrated element, wherein the first layer (10a) has at least one light coupling surface (13a), at least one light coupling surface (13c), and at least one light guide (13b) connecting the at least one light coupling surface (13a) and the at least one light coupling surface (13c), o which has a second layer (10b) adjacent to the second main side (3b), which comprises an integrated circuit which is decoupled from the photonically integrated element, o in which a plurality of contact pads (4) are formed on the second main side (3b) and are designed for connection to a carrier (6), in particular a PCB, or a second Semiconductor chip (2b) is provided; and a first optoelectronic component (5a), in particular a laser chip, which is designed to emit light of a first wavelength from at least one first emission surface (12a), wherein the at least one first emission surface (12a) is arranged opposite the at least one light coupling surface (13a). 2. Component package according to claim 1, wherein the first semiconductor chip (2a) has a cavity (8) or recess in which the first optoelectronic component (5a) is at least partially arranged, and wherein in particular the at least one light coupling surface (13a) is arranged in a side surface (3c) of the first semiconductor chip (2a) formed by the cavity (8) or recess. 3. Component package according to claim 2, wherein the first optoelectronic component (5a) is arranged on a bottom (3d) of the cavity (8) or recess. 4. Component package according to claim 1 or 2, wherein the first optoelectronic component (5a) is arranged on a submount (15). 5. Component package according to claim 4, wherein the submount (15) is arranged on the first main side (3a) of the first semiconductor chip (2a), in particular such that the first optoelectronic component (5a) is arranged at least partially in the cavity (8) or recess of the first semiconductor chip (2a). 6. Component package according to one of the preceding claims, further comprising a second optoelectronic component (5b), in particular a laser chip, which is arranged on the first main side (3a) and which is designed to emit light of a second wavelength from at least one second emission surface (12b). 7. Component package according to claim 6, wherein the at least one second emission surface (12b) and the at least one light output surface (13c) are arranged adjacent to one another, in particular with a distance of less than 50 pm or less than 25 pm. 8. Component package according to one of the preceding claims, wherein at least the first optoelectronic component (5a) is designed to emit light substantially of the first wavelength from at least two first emission surfaces (12a), wherein the at least two first emission surfaces (12a) are spaced apart from one another by a first distance. 9. Component package according to claim 8, wherein the at least two first emission surfaces (12a) are each opposite an associated light coupling surface (13a) of the first layer (10a), wherein the first layer (10a) has at least two light coupling surfaces (13c) and a light guide (13b) connecting the at least two light coupling surfaces (13a) and the at least two light coupling surfaces (13c), and wherein the at least two light coupling surfaces (13c) are spaced apart from one another by a second distance. 10. The component package of claim 9, wherein the second distance is smaller than the first distance. 11. Component package according to claim 9 or 10, wherein the second optoelectronic component (5b) is designed to emit light substantially of the second wavelength from at least two second emission surfaces (12b), wherein the at least two second emission surfaces (12b) are spaced apart from one another by a third distance, and wherein in particular the third and the second distance are substantially identical. 12. Component package according to one of the preceding claims, further comprising a third optoelectronic component (5c), in particular a laser chip, which is arranged on the first main side (3a) adjacent to the second optoelectronic component (5b) or in the cavity (8) or recess adjacent to the first optoelectronic component (5a), and which is designed to emit light of a third wavelength from at least one third emission surface (12c), wherein in particular the first, second and third optoelectronic components (5a, 5b, 5c) are designed to emit light with the colors red, green and blue. 13. Component package according to one of the preceding claims, wherein the first semiconductor chip (2a) has a plurality of first vias (9a), in particular silicon vias, which connect at least the first optoelectronic component (5a) to the integrated circuit and/or to at least one of the plurality of contact pads (4). 14. The component package according to any one of the preceding claims, further comprising a second semiconductor chip (2b) on which the first semiconductor chip (2a) is arranged, wherein the second semiconductor chip (2b) comprises an integrated circuit electrically coupled to the first semiconductor chip (2a). 15. Component package according to claim 14, wherein the second semiconductor chip (2b) has a plurality of second vias (9b), in particular silicon vias, which connect the integrated circuit to a plurality of contact surfaces (16) on a main side of the second semiconductor chip (2b). 16. Component package according to one of the preceding claims, further comprising a hermetic encapsulation, in particular a hermetically sealing cap (17) arranged on the second semiconductor chip (2b). 17. Component package according to one of the preceding claims, further comprising a carrier (6), in particular a PCB, on which the first and/or second semiconductor chip (2a, 2b) are arranged. 18. The component package according to claim 17, further comprising a plurality of bonding wires (11) which electrically connect the carrier (6) to contact surfaces (16) of the second semiconductor chip (2b) and/or to contact surfaces (16) on the first main side (3a) of the first semiconductor chip (2a). 19. Component package according to one of claims 17 or 18, further comprising a third semiconductor chip (2c) and/or at least one passive electrical component (18b) which is integrated into the carrier (6), in particular on a side opposite the first semiconductor chip (2a). 20. Component package according to one of the preceding claims, further comprising a plurality of passive electrical components (18a) which are arranged on the second semiconductor chip (2b) and/or on the carrier (6) and are each electrically connected to the second semiconductor chip (2a) and/or the carrier (6). 21. Component package according to one of the preceding claims, further comprising an optical element (14), in particular a lens, which is arranged on the second semiconductor chip (2b) downstream of the first semiconductor chip (2a) in the light emission direction of the first optoelectronic component (5a).