WO2025120086A1 - Boîtier de composant ayant une puce semi-conductrice hybride - Google Patents

Boîtier de composant ayant une puce semi-conductrice hybride Download PDF

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Publication number
WO2025120086A1
WO2025120086A1 PCT/EP2024/084926 EP2024084926W WO2025120086A1 WO 2025120086 A1 WO2025120086 A1 WO 2025120086A1 EP 2024084926 W EP2024084926 W EP 2024084926W WO 2025120086 A1 WO2025120086 A1 WO 2025120086A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
component
component package
light
package according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/EP2024/084926
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German (de)
English (en)
Inventor
Joerg Erich Sorg
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Ams Osram International GmbH
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Ams Osram International GmbH
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Filing date
Publication date
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Publication of WO2025120086A1 publication Critical patent/WO2025120086A1/fr
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • G02B6/4245—Mounting of the opto-electronic elements
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/426—Details of housings mounting, engaging or coupling of the package to a board, a frame or a panel
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/023—Mount members, e.g. sub-mount members
    • H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/023—Mount members, e.g. sub-mount members
    • H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
    • H01S5/02326—Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/0234—Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4256—Details of housings
    • G02B6/4257—Details of housings having a supporting carrier or a mounting substrate or a mounting plate
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G02B6/428—Electrical aspects containing printed circuit boards [PCB]

Definitions

  • the present invention relates to a component package with a hybrid semiconductor chip, which comprises a photonically integrated element and an integrated circuit.
  • Laser packages play an important role in the development of electronic devices and systems designed to project/emit laser light.
  • laser packages play an important role in things like smart glasses or so-called AR or VR glasses, where they are used to generate holographic images to provide the user with an immersive experience.
  • VR virtual reality
  • AR augmented reality
  • laser packages were mainly used in industrial applications where size and weight are not particularly critical. However, they are now increasingly used in consumer devices such as AR and VR glasses. It is therefore crucial that manufacturers develop smaller laser packages and associated driver circuits suitable for these applications.
  • the inventor proposes an integrated component package with a hybrid semiconductor chip which, on the one hand, comprises a photonically integrated element and an integrated circuit.
  • the component package comprises an optoelectronic component, in particular a laser, which is arranged and designed to couple laser light into the photonically integrated element and, in particular, to be controlled by means of the integrated circuit.
  • the photonically integrated element for example, light emitted by the optoelectronic component can be guided and, for example, a plurality of adjacent emission points emitted by the optoelectronic component can be brought closer together so that the emission points are as close to one another as possible when they exit the photonically integrated element.
  • a component package in particular a laser package, is provided.
  • the component package comprises a first semiconductor chip with a first main side and an opposite second main side.
  • the first semiconductor chip comprises a first layer adjacent to the first main side, which comprises a photonic integrated element or a photonic integrated circuit (PIC), and a second layer adjacent to the second main side, which comprises an integrated circuit (IC), such as an application-specific integrated circuit (ASIC), which is decoupled from the photonic integrated element.
  • PIC photonic integrated element
  • ASIC application-specific integrated circuit
  • the first layer or the photonically integrated element has at least one light coupling surface, at least one light output surface, and at least one optical fiber connecting the at least one light coupling surface and the at least one light output surface.
  • the photonically integrated element can be designed to process and/or guide light coupled in via the at least one light coupling surface and subsequently to output it via the at least one light output surface.
  • a plurality of contact pads are formed on the second main side of the first semiconductor chip, in particular in the form of a ball grid array (BGA), which is intended for connection to a carrier, in particular a PCB, or a second semiconductor chip.
  • BGA ball grid array
  • Such a design enables SMD assembly of the first semiconductor chip, since the connections are located compactly on the underside of the semiconductor chip.
  • the component package also comprises a first optoelectronic component, in particular a laser chip, which is designed to emit light of a first wavelength from at least one first emission surface.
  • the first optoelectronic component is arranged relative to the first semiconductor chip in such a way that the at least one first emission surface of the first optoelectronic component the at least one light coupling surface is opposite the first layer of the first semiconductor chip.
  • the contact pads are in the form of small solder balls that are arranged next to one another in a grid of columns and rows (array). These balls are melted during reflow soldering in a soldering oven and connect to contact pads or contact areas on, for example, a carrier or another semiconductor chip.
  • This design represents a solution to the problem of accommodating a very large number of connections on a component.
  • the first semiconductor chip can be removed (desoldered) from the carrier without being damaged, even if it is soldered over the entire surface, e.g. with hot air.
  • the first semiconductor chip can then be freed from the old solder balls (deballed), cleaned, and re-beaded with new solder balls. It can then be soldered again onto a new carrier or semiconductor chip. For example, when repairing a component package, a defective semiconductor chip can be replaced.
  • the first semiconductor chip has a cavity or recess in which the first optoelectronic component is at least partially arranged.
  • the at least one light coupling surface is arranged in a side surface of the first semiconductor chip formed by the cavity or recess.
  • the at least one light coupling surface can lie in a side surface of the first semiconductor chip that is formed by the cavity or recess or is formed by producing the cavity or recess.
  • the fact that the first optoelectronic component is arranged at least partially in the cavity or recess of the first semiconductor chip can be understood in particular in such a way that the first optoelectronic component is arranged completely, i.e. to the full extent, in the cavity or recess of the first semiconductor chip, or projects regionally beyond the cavity or recess, but is arranged at least partially in the cavity or recess.
  • the first optoelectronic component is arranged on a bottom of the cavity or recess.
  • the bottom of the cavity or recess can be formed, in particular, by a surface of the first semiconductor chip arranged opposite an opening of the cavity or recess.
  • the bottom of the cavity can be formed by a surface of the first semiconductor chip that is substantially parallel to the first or second main side.
  • the first optoelectronic component is arranged on a submount.
  • the first optoelectronic component can be arranged on a submount that is arranged adjacent to the first semiconductor chip.
  • the submount can also be arranged on the first main side of the first semiconductor chip, in particular in such a way that the first optoelectronic component is arranged at least partially in the cavity or recess of the first semiconductor chip.
  • the submount with the first optoelectronic component arranged thereon can be arranged on the first main side of the first semiconductor chip in such a way that the first optoelectronic component points in the direction of the first semiconductor chip and projects into the cavity or recess of the first semiconductor chip.
  • Such a submount may be provided, for example, to provide a heat sink and/or an electrical supply for the first optoelectronic component, and/or to provide a further semiconductor chip that provides further functionality of the component package.
  • a semiconductor chip may, for example, comprise at least one layer with an integrated circuit.
  • the component package further comprises a second optoelectronic component, in particular a laser chip, which is arranged on the first main side and which is designed to emit light of a second wavelength from at least one second emission surface.
  • the second optoelectronic component is arranged on the first main side in such a way that the at least a second emission surface and the at least one light output surface of the first layer of the first semiconductor chip are arranged adjacent to one another.
  • the first semiconductor chip can in particular serve as a submount for the second optoelectronic component and can be arranged such that the at least one second emission surface and the at least one light output surface of the first layer of the first semiconductor chip are arranged as closely as possible to one another.
  • a distance perpendicular to the first main side between the at least one second emission surface and the at least one light output surface can be less than 50 pm, less than 25 pm, or less than 10 pm.
  • the second emission surface and the at least one light output surface of the first layer can lie essentially in a common plane or at least in two planes that are only insignificantly spaced from one another.
  • the light having the first wavelength emitted by the first optoelectronic component may, in particular, differ from the light having the second wavelength emitted by the second optoelectronic component.
  • the light having the first wavelength may be red light
  • the light having the second wavelength may be green or blue light.
  • each may just as well be light of a different wavelength.
  • the at least one second emission surface of the second optoelectronic component and the at least one light output surface of the first layer of the first semiconductor chip can in particular each form an emission surface or an emission point of light of a corresponding wavelength of the component package.
  • the emission points of all optoelectronic components and thus of the light of all wavelengths can in particular be arranged in close proximity to one another. This creates a virtual point light source, so to speak.
  • the proximity of the emission points enables a simplification of possible downstream optical element(s), which for example enable collimation of all emission points by just one optical element.
  • the first optoelectronic component is designed to emit light substantially of the first wavelength from at least two first emission surfaces, wherein the at least two first emission surfaces are spaced apart from one another by a first distance.
  • the first optoelectronic component can be formed by an edge-emitting laser chip which has one or more laser ridges or laser resonators, each with a laser facet located at the end of the resonator.
  • a laser chip with a plurality of laser ridges or laser resonators can in particular be referred to as a multi-ridge laser. All laser ridges can be individually controllable in order to enable desired colors and gray levels when generating an image with multiple pixels using the component package.
  • the at least two first emission surfaces are each arranged opposite an associated light coupling surface of the first layer.
  • the first layer can also have at least two light output surfaces and a light guide connecting the at least two light input surfaces and the at least two light output surfaces, wherein the at least two light output surfaces are spaced apart from one another by a second distance.
  • the first distance can essentially correspond to the second distance, or the second distance can be smaller than the first distance. In particular, it can be advantageous for the second distance to be smaller than the first distance.
  • light-generating structures of the first optoelectronic component such as a plurality of laser bars, can be spaced apart from one another by a first distance in such a way that excessive heating of the first optoelectronic component during its intended use is prevented.
  • the light emitted from the first emission surfaces spaced apart by the first distance can be directed by means of the first layer or the photonically integrated element in such a way that the light is coupled out of the light output surfaces spaced apart by a smaller second distance.
  • the distance between light-generating structures of the first optoelectronic component can be reduced to improve heat dissipation and increase the efficiency of the first optoelectronic component. be chosen larger, while the emission points emitted by the light of the first optoelectronic component can be located close together by the photonically integrated element.
  • the second optoelectronic component is designed to emit light substantially of the second wavelength from at least two second emission surfaces.
  • the at least two second emission surfaces can be spaced apart from one another by a third distance, wherein in particular the third and the second distance are substantially identical.
  • a cooling problem as described for the first optoelectronic component may not represent a significant limitation, so that a closer arrangement of light-generating structures of the second optoelectronic component and thus of the second emission surfaces is less problematic and a merging of the emission points is not necessary. Rather, a close arrangement of the emission points generated by means of the second optoelectronic component can already be achieved by a closer arrangement of the light-generating structures of the second optoelectronic component and thus of the second emission surfaces.
  • the component package further comprises a third optoelectronic component, in particular a laser chip, which is arranged on the first main side adjacent to the second optoelectronic component or in the cavity or recess adjacent to the first optoelectronic component.
  • the third optoelectronic component is in particular designed to emit light of a third wavelength from at least one third emission surface, which can differ from the first and the second wavelength.
  • the first, second and third optoelectronic components can be designed to emit light in the colors red, green and blue and accordingly form an RGB package.
  • the first optoelectronic component is further away from the second and third optoelectronic components than a distance between the second and third optoelectronic components.
  • This can be selected in particular such that the emission properties of the first optoelectronic component can be more dependent on the heating of the first optoelectronic component compared to the second and third optoelectronic components. Accordingly, it can be desirable to arrange the first optoelectronic component further away from the second and third optoelectronic components, such that the emission properties of the first optoelectronic component are not influenced or not significantly influenced by heating of the second and third optoelectronic components.
  • the first layer or the photonically integrated element as well as the optoelectronic component(s) can be designed such that the light of the emitted wavelength(s) has the same emission pattern.
  • the first layer or the photonically integrated element as well as the optoelectronic component(s) can be designed to emit light through the light output surface(s) or emission surface(s) that has a substantially identical slow and fast axis divergence. This can be particularly advantageous in order to avoid color fringes after a combination of light of different wavelengths in, for example, a laser beam scanning system (LBS).
  • LBS laser beam scanning system
  • the first semiconductor chip has a plurality of first vias, in particular silicon vias, which connect at least the first and/or second and/or third optoelectronic component to the integrated circuit and/or to at least one of the plurality of contact pads.
  • the first semiconductor chip can have a plurality of TSVs (Through Silicon Vias) in order to connect the first and/or second and/or third optoelectronic component, for example in the form of a flip-chip laser chip, to the integrated circuit and/or to at least one of the plurality of contact pads.
  • an electrical interface between the first semiconductor chip and the first and/or second and/or third optoelectronic component can be realized without wire connections. This helps to reduce the impedance of the component package and enables efficient high-frequency modulation of the optoelectronic component(s).
  • the component package further comprises a second semiconductor chip on which the first semiconductor chip is arranged.
  • the second semiconductor chip has at least one layer comprising an integrated circuit that is electrically coupled to the first semiconductor chip.
  • the second semiconductor chip can have a multiplicity of second vias, in particular silicon vias, which connect the integrated circuit of the second semiconductor chip to a multiplicity of contact areas on one or more main sides of the second semiconductor chip.
  • the first semiconductor chip or contact pads of the first semiconductor chip can be arranged on the contact areas or a subset of the contact areas and can be electrically connected to them.
  • the first semiconductor chip can, in particular, be stacked on a further semiconductor chip comprising an integrated circuit, wherein the further semiconductor chip has driver functions and is connected to the first semiconductor chip.
  • the second semiconductor chip can, for example, serve as a base plate for the first semiconductor chip and the optoelectronic component(s).
  • the component package further comprises a hermetic encapsulation, in particular a hermetically sealing cap, which is arranged on the second semiconductor chip.
  • a hermetically sealed cavity can be formed by an inorganic cap on the second semiconductor chip, in which the first semiconductor chip and the optoelectronic component(s) can be arranged.
  • the hermetically sealing cap can in particular be used for the
  • the wavelength emitted by the optoelectronic component(s) must be transparent or translucent on at least one side, which is used to extract the light from the component package. Both a lateral emitting configuration, i.e. in the direction of the main propagation direction of the second semiconductor chip, and an upward emitting configuration, i.e. in a direction perpendicular to a main side of the second semiconductor chip, are possible.
  • the component package further comprises a carrier, in particular a PCB, on which the first and/or second semiconductor chip are arranged.
  • the component package further comprises a plurality of first passive electrical components, such as resistors, thermistors (NTC), ESD protection diodes, capacitors and/or inductors, which are arranged on the second semiconductor chip and/or on the carrier and are each electrically connected to the second semiconductor chip and/or the carrier.
  • first passive electrical components such as resistors, thermistors (NTC), ESD protection diodes, capacitors and/or inductors
  • the component package further comprises a plurality of bond wires that electrically connect the carrier to contact pads of the second semiconductor chip and/or to contact pads on the first main side of the first semiconductor chip.
  • Such bond wires can be provided in addition to or as an alternative to the first and second vias.
  • passive electrical components and/or the optoelectronic component(s) can be electrically connected to the first semiconductor chip and/or the carrier by means of additional bond wires or merely by means of bond wires.
  • the component package further comprises a third semiconductor chip and/or at least one second passive electrical component, such as a resistor, a capacitor and/or an inductor, which is integrated into the carrier, in particular on a side opposite the first semiconductor chip.
  • a third semiconductor chip and/or at least one second passive electrical component, such as a resistor, a capacitor and/or an inductor, which is integrated into the carrier, in particular on a side opposite the first semiconductor chip.
  • the component package further comprises a plurality of third vias, in particular metallic vias, through the carrier, which electrically contact the third semiconductor chip and/or the at least one second passive electrical component.
  • third vias By means of the third vias, the second semiconductor chip and/or the at least one second passive electrical component can be electrically connected to the first semiconductor chip in a space-saving manner, for example.
  • the second semiconductor chip can be designed according to the aspects of the first semiconductor chip and in particular can comprise at least one layer with an integrated circuit which is electrically connected to at least parts of the third vias.
  • the second semiconductor chip comprises at least two layers arranged one above the other, each containing an integrated circuit.
  • the second semiconductor chip can comprise correspondingly stacked layers, each containing an integrated circuit. Between the layers there can be, for example, an intermediate or compensating layer through which fourth vias run, which electrically couple the layers arranged one above the other, each containing an integrated circuit.
  • the fourth vias can therefore also be called IC-IC vias.
  • such an arrangement can also result from two separate integrated circuits being stacked on top of one another with their active area facing one another, and an intermediate or compensating layer being arranged between the two circuits.
  • the component package further comprises an optical element, in particular a lens, which is arranged on the second semiconductor chip downstream of the first semiconductor chip in the light emission direction of the first optoelectronic component.
  • an optical element in particular a lens
  • thermal stresses within the component package can have no or only a minimal negative effect on the position of the optical element relative to the first semiconductor chip or the first optoelectronic component.
  • optical element is arranged on the same continuous material as the first semiconductor chip or the first optoelectronic component and also to the fact that the second semiconductor chip can have a relatively high rigidity and thus provides an optical bench with high rigidity and low GTE for the arrangement of the first semiconductor chip or first optoelectronic component and optical element.
  • the optical element and the first semiconductor chip or first optoelectronic component can be placed on the second semiconductor chip, the space requirement in the lateral direction of such a component package can be greatly reduced compared to individual components arranged next to one another.
  • the first semiconductor chip can in particular serve as a submount for light emitted from the at least one light output surface and from emission surfaces of further optoelectronic components.
  • This can be advantageous, for example, in combination with an optical element arranged downstream of the at least one light output surface and emission surfaces in the light emission direction, since an increase can prevent or at least reduce so-called beam clipping of the emitted light.
  • it also allows greater flexibility in selecting the optical element with regard to, for example, size, optical properties and material, as well as greater flexibility with regard to the arrangement of the optical element with regard to the distance between the optical element and the first semiconductor chip.
  • the first semiconductor chip comprises a substrate layer made of a semiconductor material, in particular Si, which is free of an integrated circuit.
  • the first semiconductor chip may comprise a leveling layer that, for example, levels out unevenness within or on the first and/or second main side.
  • the component package further comprises a heat sink which is arranged on the first and/or second semiconductor chip and/or the carrier. It is also conceivable that the component package additionally or alternatively comprises a heat extraction layer which is arranged between the first semiconductor chip and the optoelectronic component(s) and/or between the first semiconductor chip and the second semiconductor chip and/or between the second semiconductor chip and the carrier and/or between the layers of the first semiconductor chip.
  • Such a heat sink and/or such a heat extraction layer can in particular be designed to store and/or dissipate heat generated during operation of the component package in order to prevent overheating and the associated change in the operating conditions of the component package or, in extreme cases, even failure of the component package.
  • Figures 1A to 1C show a side, a top and a front view of a component package according to some aspects of the proposed principle
  • FIGS 2A to 6C show side, top and front views of another component package according to some aspects of the proposed principle.
  • Figures 7A to 8B show side views and top views of another component package according to some aspects of the proposed principle.
  • FIGS 1A to 1C show a first embodiment of a component package 1 according to some aspects of the proposed principle.
  • the component package comprises a first semiconductor chip 2a with a first main side 3a and a second main side 3b opposite the first.
  • the first semiconductor chip 2a has a first layer 10a adjacent to the first main side 3a, which comprises a photonically integrated element, wherein the first layer 10a has light coupling surfaces 13a, light output surfaces 13c, and light guides 13b connecting the light coupling surfaces 13a and the light output surfaces 13c.
  • the first semiconductor chip 2a also has a second layer 10b adjacent to the second main side 3b, which comprises an integrated circuit.
  • the integrated circuit is decoupled from the photonically integrated element and serves to control the Component packages, in particular optoelectronic component(s) of the component package.
  • a plurality of contact pads 4 are formed in the form of a ball grid arrangement, which are provided for connection to, for example, a carrier, in particular a PCB, or a second semiconductor chip.
  • the component package 1 also comprises a first optoelectronic component 5a, in particular a laser chip, which is designed to emit light of a first wavelength from a plurality of first emission surfaces 12a.
  • the optoelectronic component 5a is arranged adjacent to the first semiconductor chip 2a on a submount 15 such that the first emission surfaces 12a are opposite the light coupling surfaces 13a of the photonically integrated element.
  • the core of the invention is the hybrid-designed first semiconductor chip 2a, which, on the one hand, provides a photonically integrated element by means of which light coupled into the light coupling surfaces 13a can be guided and/or processed, while the first semiconductor chip additionally provides an integrated circuit that serves to control the component package. Accordingly, this results in a compact system by means of which light emitted by the first optoelectronic component 5a can be emitted at a different location and optionally with a different emission pattern.
  • the first optoelectronic component 5a is designed as an edge-emitting laser chip with three laser ridges (represented by the dash-dot line), which is designed to couple laser light of essentially the same wavelength into light coupling surfaces of the photonically integrated element via three emission surfaces 12a.
  • the photonically integrated element is then designed to guide the coupled-in light along the light guides 13b and to couple it out again at the light coupling surfaces 13c.
  • the photonically integrated element can be designed to It may be possible to combine light coupled in at a greater distance from one another so that it is coupled out via three very closely spaced light coupling surfaces 13c, thus resulting in a virtual point light source (shown in Figure 4B).
  • the emission points located close to one another are to be deflected by means of a small optical system, for example in order to provide an LBS system.
  • the individual laser resonators can be controlled individually.
  • the number of laser bridges or emission surfaces, light coupling surfaces, light guides and light output surfaces is to be understood as exemplary and can vary in any direction.
  • Figures 2A to 2C show a further embodiment of a component package 1 according to some aspects of the proposed principle.
  • the first optoelectronic component 5a is not arranged on a separate submount 15 but on the bottom 3d of a cavity 8 in the first semiconductor chip 2a.
  • the light coupling surfaces 13a are arranged in a side surface 3c which is formed by the cavity.
  • the cavity 8 has a depth such that the emission surfaces 12a and the light coupling surfaces 13a lie opposite one another.
  • the embodiment shown has the advantage that the first optoelectronic component 5a is arranged directly on the first semiconductor chip 2a and can be electrically connected to the integrated circuit by means of first vias 9a. This eliminates the need for conductor tracks for contacting the first optoelectronic component 5a, thereby reducing the impedance of the component package and enabling faster switching frequencies (e.g., 0.2 GHz) of the first optoelectronic component 5a to be realized.
  • first vias 9a This eliminates the need for conductor tracks for contacting the first optoelectronic component 5a, thereby reducing the impedance of the component package and enabling faster switching frequencies (e.g., 0.2 GHz) of the first optoelectronic component 5a to be realized.
  • Figures 3A to 3C show a further embodiment of a component package 1 according to some aspects of the proposed principle.
  • the first optoelectronic component 5a is not in a cavity, but on the bottom 3d of a rearwardly open recess 8 in the first semiconductor chip 2a.
  • the first semiconductor chip 2a is at least partially electrically connected to the integrated circuit by means of a conductor track 11.
  • the first optoelectronic component 5a can accordingly also be designed so that it can be contacted vertically, so that electrical contact must be provided separately from a side opposite the base 3d.
  • the embodiment shown in Figures 3A to 3C is intended in particular to suggest by way of example the design options for the individual elements covered by the application, which elements can be combined with one another in any embodiment. It should also be understood that the application is not intended to be limited to the design options shown, but that these merely indicate exemplary design options.
  • FIGS 4A to 4C show a further embodiment of a component package 1 according to some aspects of the proposed principle.
  • the component package 1 comprises, in addition to the first optoelectronic component 5a, a second and a third optoelectronic component 5b, 5c, which are arranged adjacent to one another on the first main side 3a of the first semiconductor chip 2a.
  • the second and third optoelectronic components 5b, 5c are designed to emit light of a second and third wavelength through second and third emission surfaces 12b, 12c, respectively.
  • the second and third optoelectronic components 5b, 5c are arranged on an edge region of the first semiconductor chip 2a and, in particular, are essentially flush with a side surface of the first semiconductor chip 2a.
  • the second and third optoelectronic components 5b, 5c are also designed and arranged on the first main side 3a of the first semiconductor chip 2a in such a way that the emission surfaces 12b, 12c and the light output surfaces 13c of the photonically integrated element lie very close to one another and This results in a virtual point light source. This can be particularly advantageous if the emission points located close to one another are to be redirected using a small optic, for example to provide an LBS system.
  • the photonically integrated element and the optoelectronic components can in particular be designed and arranged such that the emission surfaces 12b, 12c and the light output surfaces 13c of the photonically integrated element are spaced from one another in a direction perpendicular to the first main side 3a of the first semiconductor chip 2a, i.e. in the vertical direction, by a distance of less than 50 pm or less than 25 pm.
  • the photonically integrated element and the optoelectronic components can in particular be designed and arranged such that the emission surfaces 12b, 12c and the light output surfaces 13c of the photonically integrated element are also spaced from one another in the horizontal direction by a distance of less than 50 pm or less than 25 pm.
  • the associated emission surfaces 12b, 12c and light output surfaces 13c of an optoelectronic component or of the photonically integrated element can in particular be spaced apart by a distance of less than 10 pm or less than 5 pm.
  • the second and third optoelectronic components 5b, 5c can also be electrically connected to the integrated circuit by means of first vias 9a. This eliminates the need for conductor tracks for contacting the second and third optoelectronic components 5b, 5c, thereby reducing the impedance of the component package and enabling faster switching frequencies (e.g., 0.2 GHz) of the optoelectronic components to be realized.
  • Figure 4B also shows a possible functionality of the photonically integrated element, according to which the photonically integrated element can be designed to combine light coupled in at a greater distance from one another, so that it is coupled out via three very closely spaced light coupling surfaces 13c, thus resulting in a virtual point light source.
  • This can be particularly advantageous for laser bars of the The first optoelectronic component 5a can be designed further apart from one another in order to better dissipate heat during their intended use.
  • the final emission points can still be very close to one another.
  • Figures 5A to 5C show a further embodiment of a component package 1 according to some aspects of the proposed principle.
  • the second optoelectronic component 5b is arranged on the first main side 3a of the first semiconductor chip 2a, and the third optoelectronic component 5c is arranged on the bottom 3d of the cavity 8 next to the first optoelectronic component 5a.
  • the photonically integrated element accordingly has further light coupling surfaces 13a, light coupling surfaces 13c, and light guides 13b connecting the light coupling surfaces 13a and the light coupling surfaces 13c in order to guide the light emitted by the second optoelectronic component 5b.
  • the number and arrangement of the optoelectronic components is to be understood merely as an example, and more or fewer optoelectronic components than those shown can also be provided and arranged in any number on the first main side 3a of the first semiconductor chip 2a and/or on the bottom 3d of the cavity 8 or recess next to the first optoelectronic component 5a.
  • the optoelectronic components and the photonically integrated element are designed and arranged such that the emission points of the light emitted by the component package are as close to one another as possible.
  • Figures 6A to 6C show a further embodiment of a component package 1 according to some aspects of the proposed principle.
  • the first optoelectronic component 5a is not arranged on the bottom 3d of a cavity or recess in the first semiconductor chip, but is arranged by means of a submount 15 on the first main side 3a of the first semiconductor chip 2a in such a way that the first optoelectronic component 5a projects into the cavity 8, but does not necessarily touch the bottom 3d of the cavity.
  • the submount 15 can serve, on the one hand, for electrically contacting the first optoelectronic component 5a and for cooling the first optoelectronic component 5a during its operation.
  • the submount 15 can be electrically coupled to the integrated circuit of the first semiconductor chip 2a by means of first vias 9a. Contacting of the first optoelectronic component 5a can, for example, be effected solely via the submount 15, or a contacting option can also be provided between the base 3d of the cavity 8 and the first optoelectronic component 5a.
  • the submount 15 or contact paths integrated therein can be in direct contact with the laser bars of the first optoelectronic component 5a in order to ensure optimal heat dissipation of the first optoelectronic component 5a during its operation.
  • FIGS 7A and 7B show a further embodiment of a component package 1 according to some aspects of the proposed principle.
  • the component package 1 comprises a carrier 6 on which a second semiconductor chip 2b is arranged.
  • a first semiconductor chip 2a which has a first layer 10a comprising a photonically integrated element and a second layer 10b comprising an integrated circuit.
  • the component package 1 has a first optoelectronic component 5a which is arranged on the first semiconductor chip 2a or integrated therein in such a way that light coupled out from first emission surfaces 12a is coupled into light coupling surfaces 13a of the photonically integrated element.
  • the component package 1 has a second and a third optoelectronic component 5b, 5c, which are arranged on a first main side 3a on the first semiconductor chip 2a and which are designed to emit light via second and third emission surfaces 12b, 12c.
  • the component package 1 is designed, in particular, to emit light L of the colors red, green, and blue, or any color that can be mixed therewith, by means of the optoelectronic components 5a, 5b, 5c.
  • the module arranged on the second semiconductor chip 2b, comprising the first semiconductor chip 2a and the optoelectronic component(s), can be designed according to one of the aforementioned embodiments.
  • the said module is covered on the second semiconductor chip 2b by means of a hermetically sealing cap 17 which, together with the second semiconductor chip, forms a hermetically sealed cavity in which the module is arranged.
  • the cap is designed to be transparent to the light emitted by the optoelectronic component(s), so that the light L can pass through the cap without being substantially influenced by it.
  • the cap can be particularly advantageous for increasing the service life of the optoelectronic component(s) during operation of the component package 1 by preventing foreign bodies from settling on the emission surfaces of the optoelectronic component(s).
  • a connecting region can be provided between the cap 17 and the second semiconductor chip 2b, which connecting region is free of organic material and exerts a sealing effect between the cap 17 and the second semiconductor chip 2b.
  • the second semiconductor chip 2b or a surface of the second semiconductor chip located within the hermetically sealed cavity can also be free of organic material in order to prevent particles of the organic material from settling on the emission surfaces of the optoelectronic component(s) and leading to degradation thereof.
  • the second semiconductor chip 2b has a layer with an integrated circuit 8, which is electrically connected to the carrier 6 for its power supply.
  • the layer with the integrated circuit is indicated by the dashed line.
  • An electrical connection to the carrier 6 can be made via second vias 9b directly or via bonding wires 11.
  • the second semiconductor chip has on a main side facing the first semiconductor chip Contact surfaces 16 which are at least partially in electrical contact with the contact pads 4 of the first semiconductor chip 2a.
  • first passive electrical components 18a are arranged on the second semiconductor chip 2b and on the carrier 6, which are each electrically connected to the second semiconductor chip 2b and to the carrier 6 and contribute partial functionality to the operation of the component package 1.
  • the term "operation of the integrated component package” is to be understood as meaning both an electrical supply and a signaling control of the component package.
  • the positioning and number of the first passive electrical components 18a and the bond wires 11, as well as the contact surfaces, are to be understood as examples and can vary depending on the design and application of the component package 1.
  • bonding wires 11 alternatively or in addition to vias 9b through the second semiconductor chip 2b, the design and implementation of the second semiconductor chip 2b itself can be simplified, since no or at least fewer vias through the second semiconductor chip 2b are necessary.
  • the carrier 6, the second semiconductor chip 2b, the first semiconductor chip 2a, the optoelectronic components, and the passive electrical components 18a By stacking the carrier 6, the second semiconductor chip 2b, the first semiconductor chip 2a, the optoelectronic components, and the passive electrical components 18a, it is possible to design the component package 1 in the most space-saving way possible compared to a design in which the individual components are arranged side by side and must be electrically connected to one another by laterally extending contact lines. Furthermore, such an integrated module can be installed and connected in a designated application easily and without any further complex subsequent processes.
  • the component package 1 also has a third semiconductor chip 2c and second passive electrical components 18b, which are integrated into the carrier 6 on a side opposite the first semiconductor chip 2a.
  • the carrier 6 has recesses in which the components or the semiconductor chip are arranged.
  • third vias 9c are provided through the carrier, by means of which an electrical contact is passed through the carrier 6 in order to connect the third semiconductor chip 2c and the second passive electrical components 18b from the side facing the first semiconductor chip 2a.
  • Figures 8a and 8B show an embodiment of a component package 1 which additionally comprises an optical element 14.
  • the optical element 14 is arranged downstream of the first semiconductor chip 2a or the optoelectronic components in the light emission direction L on the second semiconductor chip 2b.
  • the optical element 14 can in particular be a passive optical element such as one or more lenses which shape, scatter or deflect/redirect the light emitted by the optoelectronic components.
  • the optical element 14 it is also conceivable for the optical element 14 to be formed by an active optical element which actively shapes, scatters or in particular deflects/redirects the light emitted by the optoelectronic components.
  • the optical element 14 can also be formed by a prism which deflects the emitted light in a direction perpendicular to the second semiconductor chip 2b.
  • thermal stresses within the component package 1 can have no or only a minimal negative effect on the position of the optical element 14 relative to the optoelectronic components. This can be due, among other things, to the fact that the optical element 14 is arranged on the same continuous material as the first semiconductor chip 2a or the optoelectronic components and also to the fact that the second semiconductor chip 2b can have a relatively high rigidity and thus provides an optical bench with high rigidity and low GTE for the arrangement of optoelectronic components and optical element 14.
  • the space requirement in the lateral direction of such a component package 1 can be greatly reduced compared to individual components arranged next to one another.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Semiconductor Lasers (AREA)

Abstract

L'invention concerne un boîtier de composant, en particulier un boîtier laser, comprenant une première puce semi-conductrice ayant une première face principale et une seconde face principale en regard de la première. La première puce semi-conductrice comprend une première couche, qui est adjacente à la première face principale et comprend un élément intégré de manière photonique, la première couche ayant au moins une surface de couplage d'entrée de lumière, au moins une surface de couplage de sortie de lumière, et au moins un guide d'ondes reliant la ou les surfaces de couplage d'entrée de lumière et la ou les surfaces de couplage de sortie de lumière. La première puce semi-conductrice comprend également une seconde couche, qui est adjacente à la seconde face principale et comprend un circuit intégré qui est découplé de l'élément intégré de manière photonique, et un grand nombre de plots de contact sur la seconde face principale, qui sont prévus pour une connexion à un substrat, en particulier une PCB ou une seconde puce semi-conductrice. Le boîtier de composant comprend également un premier composant optoélectronique, en particulier une puce laser, qui est conçu pour émettre de la lumière d'une première longueur d'onde à partir d'au moins une première surface d'émission, la ou les premières surfaces d'émission étant disposées en regard de la ou des surfaces de couplage d'entrée de lumière.
PCT/EP2024/084926 2023-12-08 2024-12-05 Boîtier de composant ayant une puce semi-conductrice hybride Pending WO2025120086A1 (fr)

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DE102023134453.6 2023-12-08
DE102023134453.6A DE102023134453A1 (de) 2023-12-08 2023-12-08 Bauelementpackage mit einem hybriden halbleiterchip

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WO2025120086A1 true WO2025120086A1 (fr) 2025-06-12

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DE102023134453A1 (de) 2023-12-08 2025-06-12 Ams-Osram International Gmbh Bauelementpackage mit einem hybriden halbleiterchip

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477286B1 (en) * 1999-07-16 2002-11-05 Canon Kabushiki Kaisha Integrated optoelectronic device, and integrated circuit device
US20050072979A1 (en) * 2002-07-22 2005-04-07 Applied Materials, Inc. Optical-ready wafers
US20100272388A1 (en) * 2009-04-23 2010-10-28 Im Young-Min Photoelectric conversion module
WO2023014647A1 (fr) * 2021-08-03 2023-02-09 Meta Platforms Technologies, Llc Conditionnement de puce laser pour une source de lumière rvb
DE102023134453A1 (de) 2023-12-08 2025-06-12 Ams-Osram International Gmbh Bauelementpackage mit einem hybriden halbleiterchip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4091005B1 (fr) * 2020-01-16 2026-01-28 SRI International Ensembles de cellules sous vide intégrées

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477286B1 (en) * 1999-07-16 2002-11-05 Canon Kabushiki Kaisha Integrated optoelectronic device, and integrated circuit device
US20050072979A1 (en) * 2002-07-22 2005-04-07 Applied Materials, Inc. Optical-ready wafers
US20100272388A1 (en) * 2009-04-23 2010-10-28 Im Young-Min Photoelectric conversion module
WO2023014647A1 (fr) * 2021-08-03 2023-02-09 Meta Platforms Technologies, Llc Conditionnement de puce laser pour une source de lumière rvb
DE102023134453A1 (de) 2023-12-08 2025-06-12 Ams-Osram International Gmbh Bauelementpackage mit einem hybriden halbleiterchip

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