CN114400994B - NMOS high-side switch control circuit and method based on capacitor bootstrap boost - Google Patents

NMOS high-side switch control circuit and method based on capacitor bootstrap boost Download PDF

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Publication number
CN114400994B
CN114400994B CN202210020951.XA CN202210020951A CN114400994B CN 114400994 B CN114400994 B CN 114400994B CN 202210020951 A CN202210020951 A CN 202210020951A CN 114400994 B CN114400994 B CN 114400994B
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nmos tube
switch
small
switch nmos
capacitor
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CN114400994A (en
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谢建军
童诚
周获
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NINGBO YINZHOU MASAHIRO ELECTRON & ARTS Inc
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NINGBO YINZHOU MASAHIRO ELECTRON & ARTS Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0063—High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention discloses an NMOS high-side switch control circuit and method based on capacitor bootstrap boost, comprising a micro controller, a timer and a switch control circuit, wherein the switch control circuit comprises a square wave level, a third fast diode, a third small-signal switch NMOS tube, a small-signal PNP triode, a bootstrap capacitor, a first switch NMOS tube, a second switch NMOS tube, a small-signal NPN triode, a first bypass capacitor, a first fast diode, a second fast diode and a direct current stabilized voltage source. The invention utilizes the micro controller to output square wave control level to control the bootstrap boost of the capacitor, so that the grid potential of the first switch NMOS tube is larger than the sum of the source potential and the threshold voltage V GS(th) and is continuous. The invention solves the technical problems that similar boost NMOS saturated conduction based on capacitive bootstrap cannot be sustained, and the circuit design is complex and the production and manufacturing cost is high due to the use of an application specific integrated circuit or a boost transformer.

Description

NMOS high-side switch control circuit and method based on capacitor bootstrap boost
Technical Field
The invention relates to the technical field of NMOS high-side driving circuits, in particular to an NMOS high-side switching control circuit and method based on capacitor bootstrap boost in a direct current electronic system.
Background
In electronic systems, it is often necessary to control the power supply to a load to start or stop the load. MOSFETs (metal oxide semiconductor field effect transistors) are conducting with voltage controlled majority carriers and have low resistivity, which is an ideal choice for on and off control. The channel types can be classified into NMOS and PMOS. The NMOS majority carrier is electron, the PMOS majority carrier is hole, the electron mobility is 2 to 3 times of the hole mobility, and then the NMOS has lower on-resistance, and the power consumption is lower and the current carrying capacity is larger under the same on-current. It is a great advantage to choose NMOS as the switch control element.
The NMOS is used for high-side circuit on-off control, namely, the drain electrode (D electrode) is connected with the positive electrode of a power supply, the source electrode S (S electrode) is connected with the positive electrode of a load, and the grid electrode (G electrode) is connected with a control signal. When saturated conduction is performed, the source electrode S voltage is approximately equal to the drain electrode voltage, that is, the source electrode S voltage is equal to the power supply voltage, and according to the saturated conduction condition of the NMOS, the gate electrode potential needs to be greater than the sum of the source electrode S potential and the gate threshold voltage V GS(th), so that saturated conduction can be performed. In the prior art, a dedicated NMOS high-side driver integrated circuit is mostly adopted or a boost transformer is used to generate the gate control voltage, and the design greatly increases the complexity, the manufacturing cost and the maintenance cost of the circuit design, so that improvement is needed.
Disclosure of Invention
The invention aims to provide an NMOS high-side switch control circuit and method based on capacitor bootstrap boost, which are used for solving the problems of complexity, production and manufacturing cost and maintenance cost of the circuit design proposed in the background art.
In order to achieve the above purpose, the present invention provides the following technical solutions: the NMOS high-side switch control circuit based on capacitor bootstrap boost comprises a micro controller and a timer, wherein the micro controller is connected with a switch control circuit, the switch control circuit comprises a square wave level V2, a third fast diode D3, a third small signal switch NMOS tube M3, a small signal PNP triode Q1, a bootstrap capacitor C1, a first switch NMOS tube M1, a second switch NMOS tube M2, a small signal NPN triode Q2, a first bypass capacitor C2, a first fast diode D1, a second fast diode D2 and a direct current voltage stabilizing source V1 for providing voltage stabilizing electric energy for the micro controller, the switch NMOS tube, a load and various discrete components, wherein the positive electrode of the output end of the square wave level V2 is connected with the grid G of the third switch NMOS tube M3 through the third fast diode D3, the positive electrode of the output end of the square wave level V2 is also connected with the base electrode of a small signal NPN type triode Q2 through a fourth resistor R4, the collector electrode of the small signal NPN type triode Q2 is connected with the positive electrode of the direct current stabilized voltage source V1 through a first resistor R1, the collector electrode of the small signal NPN type triode Q2 is connected with the base electrode of a small signal PNP type triode Q1, the emitter electrode of the small signal PNP type triode Q1 is connected with the positive electrode end of the direct current stabilized voltage source V1, the first fast diode D1, a bootstrap capacitor C1 and a fifth resistor R5 are connected in series between the positive electrode end of the direct current stabilized voltage source V1 and a grounding end GND, the public ends of the first fast diode D1 and the bootstrap capacitor C1 are connected with the grid electrode G of a first switch NMOS tube M1 through a second fast diode D2 and a current limiting resistor R3 which are connected in series, the public ends of the bootstrap capacitor C1 and the fifth resistor R5 are connected with the collector electrode of the small signal PNP type triode Q1, the fast diode D2, be connected with between the public end of current-limiting resistor R3 and the ground terminal GND first bypass electric capacity C2, the drain electrode D of first switch NMOS pipe M1 is connected the positive terminal of direct current steady voltage source V1, the drain electrode D of second switch NMOS pipe M2 is connected grid G of first switch NMOS pipe M1, grid G of second switch NMOS pipe M2 passes through second resistance R2 and connects the positive terminal of direct current steady voltage source V1, grid G of second switch NMOS pipe M2 still is connected with the drain electrode D of third small signal switch NMOS pipe M3, be connected with sixth resistance R6 between source S and the ground terminal GND of first switch NMOS pipe M1, source S of third small signal switch NMOS pipe M3 and second switch NMOS pipe M2 all connect ground terminal GND, source S of first switch NMOS pipe M1 is as load output.
Preferably, the bootstrap capacitor C1 is capable of performing buck charging and boost discharging according to the state of the small-signal PNP type triode Q1, when the small-signal PNP type triode Q1 is in saturated conduction, the bootstrap capacitor C1 is in boost discharging, and when the small-signal PNP type triode Q1 is in off, the bootstrap capacitor C1 is in buck charging.
Preferably, the first bypass capacitor C2 provides a continuous stable forward bias voltage for the saturated conduction of the first switch NMOS M1, and when the small-signal PNP transistor Q1 is saturated and conducted, the first bypass capacitor C2 charges when the positive potential of the bootstrap capacitor C1 increases; when the small-signal PNP triode Q1 is cut off, the first bypass capacitor C2 discharges when the potential of the positive electrode of the bootstrap capacitor C1 falls back.
Preferably, a second bypass capacitor C3 is connected between the gate G of the third switch NMOS transistor M3 and the ground GND, and the second bypass capacitor C3 provides a continuous stable forward bias voltage for the saturated conduction of the third switch NMOS transistor M3, when the square wave level V2 is at a high level, the second bypass capacitor C3 charges, and when the square wave level V2 is at a low level, the second bypass capacitor C3 discharges.
Preferably, the first fast diode D1 can prevent the bootstrap capacitor C1 from flowing backward to the dc voltage stabilizing source V1 during the boost discharge process of the bootstrap capacitor C1 when the small-signal PNP type triode Q1 is saturated and turned on, and establish a charging loop signal for the bootstrap capacitor C1 when the small-signal PNP type triode Q1 is turned off, and the second fast diode D2 charges the first bypass capacitor C2 when the small-signal PNP type triode Q1 is saturated and turned on, and prevents the first bypass capacitor C2 from reversely discharging the front-stage circuit when the small-signal PNP type triode Q1 is turned off.
The invention also discloses an NMOS high-side switch control method based on capacitor bootstrap boost, which specifically comprises the following steps:
S1, outputting a square wave control level V2 by a micro controller 1, controlling a small signal PNP triode Q1 to be alternately saturated and switched on and off, and when the small signal PNP triode Q1 is saturated and switched on, raising the potential of the negative electrode of a bootstrap capacitor C1, and raising the potential of the positive electrode of the bootstrap capacitor C1 along with the potential of the negative electrode of the bootstrap capacitor C1, wherein the potential is larger than the sum of the potential of a source electrode S of a first switch NMOS tube M1, a gate threshold voltage V GS(th) of the first switch NMOS tube M1 and the voltage between the positive electrode of the bootstrap capacitor C1 and a grid electrode G of the first switch NMOS tube M1, so that the first switch NMOS tube M1 is saturated and switched on, and the positive electrode of a direct current voltage stabilizing source V1 is supplied to the source electrode S of the first switch NMOS tube M1 through a drain electrode D of the first switch NMOS tube M1 to supply power for a load; when the DC voltage-stabilizing source is cut off, the positive electrode of the DC voltage-stabilizing source V1 charges the bootstrap capacitor C1 through the fast diode D1, the first bypass capacitor C2 at the later stage discharges the grid electrode G of the first switch NMOS tube M1 through the current-limiting resistor R3, and the first switch NMOS tube M1 is kept in saturated conduction, and at the moment, the DC voltage-stabilizing source V1 supplies power to a load continuously;
S2, when the micro controller stops outputting the square wave control level V2, the grid G and the source S of the third small signal switch NMOS tube M3 gradually lose forward bias voltage and are converted from a saturated on state to an off state, at the moment, the grid G of the second switch NMOS tube M2 is pulled up to the power supply voltage through the second resistor R2, the grid G and the source S of the second switch NMOS tube M2 obtain forward bias voltage and are converted from the off state to the saturated on state, the grid G voltage of the first switch NMOS tube M1 is pulled to the ground end GND through the drain D of the second switch NMOS tube M2, the first switch NMOS tube M1 is converted from the saturated on state to the off state, and at the moment, the direct current voltage stabilizing source V1 is cut off by the first switch NMOS tube M1 due to a power supply loop and stops supplying power to a load.
Further, the square wave level V2 is generated by the microcontroller 1, the amplitude of the square wave level V2 is 0-5V, the square wave level V is connected with the fourth resistor R4, the other small signal PNP type triode Q1 is controlled by the small signal NPN type triode Q2, the small signal PNP type triode Q1 is saturated and conducted when the square wave control level is high, the potential of the negative electrode of the bootstrap capacitor C1 is raised, and the voltage of the negative electrode of the bootstrap capacitor C1 is equal to the power supply voltage minus the conduction voltage drop of the emitter and the collector of the small signal PNP type triode Q1.
Preferably, the frequency range of the square wave generated by the microcontroller through the timer is: when the bootstrap capacitor C1 is in the unit charge-discharge period, the electric energy of the second-stage first bypass capacitor C2 maintains the first switch NMOS M1 to be turned on, and the positive potential of the first bypass capacitor C2 should be greater than the sum of the voltage drop of the current limiting resistor R3, the threshold voltage V GS(th) of the first switch NMOS M1, and the voltage of the source S after being turned on, i.e., V c2≥VR3+VGS(th)+V1 at any time.
The NMOS high-side switch control circuit and method based on capacitor bootstrap boost have the following technical effects:
the invention utilizes the micro controller to output square wave control level, controls the capacitor to bootstrap and boost, so that the NMOS grid potential is larger than the sum of the source S potential and the gate threshold voltage V GS(th) and continues, further NMOS saturation conduction is continued, namely the switch is closed, when the micro controller stops outputting the square wave control level, the NMOS grid potential is zero, further NMOS is cut off, namely the switch is opened, the technical problems that similar boost NMOS saturation conduction cannot be continued based on capacitor bootstrap, and the circuit design is complex and the production and manufacturing cost is high due to the use of an application-specific integrated circuit or a boost transformer are solved.
Drawings
FIG. 1 is a schematic diagram of an NMOS high side switch control circuit based on capacitive bootstrap boost;
FIG. 2 is a schematic circuit diagram of a switch control circuit;
FIG. 3 is a graph showing the relationship between the voltage at two poles of the bootstrap capacitor C1 and the square wave control level;
FIG. 4 is a graph showing the relationship between the positive potential of the bootstrap capacitor C1 and the positive potential of the bypass capacitor C2;
Fig. 5 is a graph showing the relationship between the square wave control level V2 and the positive potential of the bypass capacitor C3.
FIG. 6 is a first voltage level diagram of the source S of the first switch NMOS transistor M1 when the square wave control level V2 is outputted;
Fig. 7 is a second voltage diagram of the source S of the first switch NMOS M1 when the square wave control level V2 stops outputting.
In the figure: a micro controller 1, a timer 2 and a switch control circuit 3.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1:
Referring to fig. 1-2, the embodiment provides an NMOS high-side switch control circuit based on capacitor bootstrap boost, which includes a micro controller 1 and a timer 2, wherein the micro controller 1 is connected with a switch control circuit 3, the switch control circuit 3 includes a square wave level V2, a third fast diode D3, a third small signal switch NMOS M3, a small signal PNP type triode Q1, a bootstrap capacitor C1, a first switch NMOS M1, a second switch NMOS M2, a small signal NPN type triode Q2, a first bypass capacitor C2, a first fast diode D1, a second fast diode D2, and a dc voltage stabilizing source V1 for providing voltage stabilizing power for the micro controller 1, the switch NMOS, a load and various discrete components, wherein an output positive electrode of the square wave level V2 is connected with a gate G of the third switch NMOS M3 through the third fast diode D3, the positive electrode of the output end of the square wave level V2 is also connected with the base electrode of a small signal NPN type triode Q2 through a fourth resistor R4, the collector electrode of the small signal NPN type triode Q2 is connected with the positive electrode of the direct current stabilized voltage source V1 through a first resistor R1, the collector electrode of the small signal NPN type triode Q2 is connected with the base electrode of a small signal PNP type triode Q1, the emitter electrode of the small signal PNP type triode Q1 is connected with the positive electrode end of the direct current stabilized voltage source V1, the first fast diode D1, the bootstrap capacitor C1 and the fifth resistor R5 are connected in series between the positive electrode end of the direct current stabilized voltage source V1 and the grounding end GND, the common end of the first fast diode D1 and the bootstrap capacitor C1 is connected with the grid electrode G of a first switch NMOS tube M1 through a second fast diode D2 and a current limiting resistor R3 which are connected in series, the common end of the bootstrap capacitor C1 and the fifth resistor R5 is connected with the collector of the small-signal PNP triode Q1, the first bypass capacitor C2 is connected between the common end of the second fast diode D2 and the current limiting resistor R3 and the ground end GND, the drain electrode D of the first switch NMOS tube M1 is connected with the positive end of the direct-current voltage stabilizing source V1, the drain electrode D of the second switch NMOS tube M2 is connected with the grid electrode G of the first switch NMOS tube M1, the grid electrode G of the second switch NMOS tube M2 is connected with the positive end of the direct-current voltage stabilizing source V1 through the second resistor R2, the grid electrode G of the second switch NMOS tube M2 is also connected with the drain electrode D of the third small-signal switch NMOS tube M3, the sixth resistor R6 is connected between the source electrode S of the first switch NMOS tube M1 and the ground end GND, the source electrode S of the third small-signal switch NMOS tube M3 and the second switch NMOS tube M2 are both connected with the ground end GND, and the source electrode S of the first switch NMOS tube M1 serves as the output load.
Preferably, the bootstrap capacitor C1 is capable of performing buck charging and boost discharging according to the state of the small-signal PNP type triode Q1, when the small-signal PNP type triode Q1 is in saturated conduction, the bootstrap capacitor C1 is in boost discharging, and when the small-signal PNP type triode Q1 is in off, the bootstrap capacitor C1 is in buck charging.
Preferably, the first bypass capacitor C2 provides a continuous stable forward bias voltage for the saturated conduction of the first switch NMOS M1, and when the small-signal PNP transistor Q1 is saturated and conducted, the first bypass capacitor C2 charges when the positive potential of the bootstrap capacitor C1 increases; when the small-signal PNP triode Q1 is cut off, the first bypass capacitor C2 discharges when the potential of the positive electrode of the bootstrap capacitor C1 falls back.
Preferably, a second bypass capacitor C3 is connected between the gate G of the third switch NMOS transistor M3 and the ground GND, and the second bypass capacitor C3 provides a continuous stable forward bias voltage for the saturated conduction of the third switch NMOS transistor M3, when the square wave level V2 is at a high level, the second bypass capacitor C3 charges, and when the square wave level V2 is at a low level, the second bypass capacitor C3 discharges.
Preferably, the first fast diode D1 can prevent the bootstrap capacitor C1 from flowing backward to the dc voltage stabilizing source V1 during the boost discharge process of the bootstrap capacitor C1 when the small-signal PNP type triode Q1 is saturated and turned on, and establish a charging loop signal for the bootstrap capacitor C1 when the small-signal PNP type triode Q1 is turned off, and the second fast diode D2 charges the first bypass capacitor C2 when the small-signal PNP type triode Q1 is saturated and turned on, and prevents the first bypass capacitor C2 from reversely discharging the front-stage circuit when the small-signal PNP type triode Q1 is turned off.
As shown in fig. 3 to 7, in fig. 3, a solid line marked with a symbol '×' is a square wave control level V2; the sub-thick line marked by symbol '≡' is the potential of the negative electrode of the bootstrap capacitor C1; the thick line marked by the symbol' ″ is the positive electrode potential of the bootstrap capacitor C1; in fig. 4, a solid line denoted by a symbol' ″ is the positive electrode potential of the bootstrap capacitor C1; the sub-thick line marked by the symbol 'Delta' is the positive potential of the bypass capacitor C2; in fig. 5, a solid line marked with a symbol '×' is a square wave control level V2; the sub-thick line marked with the symbol 'V' is the positive electrode potential of the bypass capacitor C3; in fig. 6, a solid line marked with a symbol '×' is a square wave control level V2; the sub-thick line marked with 'o' is the source electrode S pole potential of the first switch NMOS transistor M1, and in fig. 7, the solid line marked with 'x' is the square wave control level V2; the sign 'O' marked sub-thick line is the S pole potential of the source electrode of the first switch NMOS tube M1, and the embodiment also discloses an NMOS high-side switch control method based on capacitor bootstrap boost, which specifically comprises the following steps:
S1, outputting a square wave control level V2 by a micro controller 1, controlling a small signal PNP triode Q1 to be alternately saturated and switched on and off, and when the small signal PNP triode Q1 is saturated and switched on, raising the potential of the negative electrode of a bootstrap capacitor C1, and raising the potential of the positive electrode of the bootstrap capacitor C1 along with the potential of the negative electrode of the bootstrap capacitor C1, wherein the potential is larger than the sum of the potential of a source electrode S of a first switch NMOS tube M1, a gate threshold voltage V GS(th) of the first switch NMOS tube M1 and the voltage between the positive electrode of the bootstrap capacitor C1 and a grid electrode G of the first switch NMOS tube M1, so that the first switch NMOS tube M1 is saturated and switched on, and the positive electrode of a direct current voltage stabilizing source V1 is supplied to the source electrode S of the first switch NMOS tube M1 through a drain electrode D of the first switch NMOS tube M1 to supply power for a load; when the DC voltage-stabilizing source is cut off, the positive electrode of the DC voltage-stabilizing source V1 charges the bootstrap capacitor C1 through the fast diode D1, the first bypass capacitor C2 at the later stage discharges the grid electrode G of the first switch NMOS tube M1 through the current-limiting resistor R3, and the first switch NMOS tube M1 is kept in saturated conduction, and at the moment, the DC voltage-stabilizing source V1 supplies power to a load continuously;
S2, when the micro controller stops outputting the square wave control level V2, the grid G and the source S of the third small signal switch NMOS tube M3 gradually lose forward bias voltage and are converted from a saturated on state to an off state, at the moment, the grid G of the second switch NMOS tube M2 is pulled up to the power supply voltage through the second resistor R2, the grid G and the source S of the second switch NMOS tube M2 obtain forward bias voltage and are converted from the off state to the saturated on state, the grid G voltage of the first switch NMOS tube M1 is pulled to the ground end GND through the drain D of the second switch NMOS tube M2, the first switch NMOS tube M1 is converted from the saturated on state to the off state, and at the moment, the direct current voltage stabilizing source V1 is cut off by the first switch NMOS tube M1 due to a power supply loop and stops supplying power to a load.
It should be noted that: in this embodiment, the threshold voltage V GS(th) is the on-state voltage of M1, and if and only if the G, S voltage difference of the MOS is greater than the threshold voltage V GS(th), the D, S electrode of the MOS transistor is in the on-state, and the threshold voltage V GS(th) is determined by the physical properties of the MOS and the manufacturing process, and the NMOS is generally 2-4V.
Further, the square wave level V2 is generated by the microcontroller 1, the amplitude of the square wave level V2 is 0-5V, the square wave level V is connected with the fourth resistor R4, the other small signal PNP type triode Q1 is controlled by the small signal NPN type triode Q2, the small signal PNP type triode Q1 is saturated and conducted when the square wave control level is high, the potential of the negative electrode of the bootstrap capacitor C1 is raised, and the voltage of the negative electrode of the bootstrap capacitor C1 is equal to the power supply voltage minus the conduction voltage drop of the emitter and the collector of the small signal PNP type triode Q1.
Preferably, the frequency range of the square wave generated by the microcontroller 1 through the timer 2 is: when the bootstrap capacitor C1 is in a unit charge-discharge period, the electric energy of the second-stage first bypass capacitor C2 keeps the first switch NMOS M1 conductive, the positive potential of the first bypass capacitor C2 at any time should be greater than the voltage drop of the current-limiting resistor R3, the sum of the threshold voltage V GS(th) of the first switch NMOS M1 and the voltage of the source S after being conductive, i.e., V c2≥VR3+VGS(th)+V1, in this embodiment, if the positive potential of the bootstrap capacitor C1 is seen, the voltage to ground Vc1 is greater than or equal to vd2+vc2, so that the D, S pole of the first switch M1 can be conducted, where Vd2 is a fast diode D2 forward conduction voltage drop, and if the positive potential of the first bypass capacitor C2 is seen, the voltage to ground should satisfy V c2≥VR3+VGS(th)+V1 in the boost-buck period of the bootstrap capacitor C1, so that the D, S pole of the first switch M1 can be conducted.
Working principle:
The micro controller 1 is utilized to output square wave control level to control the PNP triode Q1 to be alternately saturated and switched on and off, so that the bootstrap capacitor C1 is alternately increased and decreased. When the voltage is further boosted, the first bypass capacitor C2 of the rear stage is charged, and forward bias voltage is provided for the gate and the source S of the first switch NMOS tube M1, so that the first switch NMOS tube M is saturated and conducted; during voltage reduction, the direct-current regulated power supply V1 charges the bootstrap capacitor C1, the first bypass capacitor C2 continuously provides forward bias voltage for saturated conduction of the first switch NMOS tube M1, and the saturated conduction state is maintained to be not influenced by voltage reduction of the bootstrap capacitor.
The micro controller 1 is utilized to stop square wave control level output, so that the bootstrap capacitor C1 is only charged and cannot be boosted. Meanwhile, the second switch NMOS tube M2 is controlled to be saturated and turned on through the second pull-up resistor R2, and the gate potential of the first switch NMOS tube M1 is pulled down, so that the gate and the source S lose forward bias voltage and are turned off.
The working process comprises the following steps:
First, the microcontroller 1 outputs a square wave control level V2.
During high level, the small signal PNP triode Q1 and the small signal NPN triode Q2 are saturated and conducted, the potential of the negative electrode of the bootstrap capacitor C1 is raised, the voltage at two ends of the capacitor cannot be suddenly changed, the potential of the positive electrode of the bootstrap capacitor C1 is raised along with the voltage, the first bypass capacitor C2 at the later stage is charged through the fast diode (D2), forward bias is provided for the grid and the source electrode S of the first switch NMOS tube M1 through the current limiting resistor R3, saturated and conducted, and further, a power supply loop is established for the drain and the source electrode S of the first switch NMOS tube M1, and the direct current voltage stabilizing source V1 supplies power for a load.
When in low level, the small signal PNP triode Q1 and the small signal NPN triode Q2 are cut off, the positive and negative potentials of the bootstrap capacitor C1 are reduced, the direct current voltage stabilizing source V1 charges the bootstrap capacitor C1 through the fast diode, the first bypass capacitor C2 at the rear stage continuously provides forward bias for the grid and the source S of the first switch NMOS tube M1 through the current limiting resistor R3, the saturated conduction state of the first switch NMOS tube M1 is maintained, and further, the direct current voltage stabilizing source V1 continuously supplies power to a load;
The micro controller 1 stops outputting the square wave control level V2, the bootstrap capacitor C1 does not bootstrap and boost, the grid and the source electrode S of the first switch NMOS tube M1 lose forward bias voltage, the other path of the bootstrap capacitor C1 is cut off due to the fact that the third small signal switch NMOS tube M3 loses forward bias voltage, the grid electrode of the second switch NMOS tube M2 is saturated and conducted by obtaining normal bias voltage under the action of the pull-up second resistor R2, the grid potential of the first switch NMOS tube M1 is pulled to the public ground, namely 0V, further, the first switch NMOS tube M1 is cut off, the direct current voltage stabilizing source V1 loses a power supply loop, and power cannot be supplied to loads.
Therefore, the micro controller 1 is utilized to output square wave control level to control the bootstrap boost of the capacitor, so that the potential of the grid electrode (G electrode) of the NMOS is larger than the sum of the potential of the source electrode S and the threshold voltage V GS(th) and is continuous, and further the saturated conduction of the NMOS is continuous, namely the switch is closed. When the microcontroller 1 stops outputting the square wave control level, the potential of the NMOS gate (G pole) is zero, and the NMOS is further turned off, namely the switch is turned off. The invention solves the technical problems that similar saturated conduction of a boost NMOS based on capacitor bootstrap cannot be sustained, and the circuit design is complex and the production and manufacturing cost is high due to the use of an application specific integrated circuit or a boost transformer.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims (8)

1. The utility model provides a NMOS high side switch control circuit based on electric capacity bootstrapping boost, includes micro-controller (1) and timer (2), its characterized in that: the micro controller (1) is connected with a switch control circuit (3), the switch control circuit (3) comprises a square wave level (V2), a third fast diode (D3), a third small signal switch NMOS tube (M3), a small signal PNP triode (Q1), a bootstrap capacitor (C1), a first switch NMOS tube (M1), a second switch NMOS tube (M2), a small signal NPN triode (Q2), a first switch NMOS tube (M1), a second switch NMOS tube (M2) and a second switch NMOS tube (M1), a third fast diode (D3) which are output by the micro controller (1) through timing setting of a timer (2), The first bypass capacitor (C2), the first fast diode (D1), the second fast diode (D2) and a direct current voltage stabilizing source (V1) for providing voltage stabilizing electric energy for the micro controller (1), the switch NMOS tube, the load and various discrete components, wherein the positive electrode of the output end of the square wave level (V2) is connected with the grid electrode G of the third switch NMOS tube (M3) through the third fast diode (D3), the positive electrode of the output end of the square wave level (V2) is also connected with the base electrode of the small signal NPN triode (Q2) through the fourth resistor (R4), the collector electrode of the small signal NPN triode (Q2) is connected with the positive electrode end of the direct current voltage stabilizing source (V1) through the first resistor (R1), the collector of the small signal NPN triode (Q2) is connected with the base of the small signal PNP triode (Q1), the emitter of the small signal PNP triode (Q1) is connected with the positive electrode end of the direct current voltage stabilizing source (V1), the first fast diode (D1), the bootstrap capacitor (C1) and the fifth resistor (R5) are connected in series between the positive electrode end of the direct current voltage stabilizing source (V1) and the grounding end (GND), the public ends of the first fast diode (D1) and the bootstrap capacitor (C1) are connected with the grid electrode G of the first switch NMOS tube (M1) through the second fast diode (D2) and the current limiting resistor (R3) which are connected in series, the common end of the bootstrap capacitor (C1) and the fifth resistor (R5) is connected with the collector electrode of the small-signal PNP triode (Q1), the first bypass capacitor (C2) is connected between the common end of the second fast diode (D2) and the current limiting resistor (R3) and the grounding end (GND), the drain electrode D of the first switch NMOS tube (M1) is connected with the positive electrode end of the direct current voltage stabilizing source (V1), the drain electrode D of the second switch NMOS tube (M2) is connected with the grid electrode G of the first switch NMOS tube (M1), the grid electrode G of the second switch NMOS tube (M2) is connected with the positive electrode end of the direct current voltage stabilizing source (V1) through the second resistor (R2), the grid G of second switch NMOS pipe (M2) still is connected with the drain electrode D of third little signal switch NMOS pipe (M3), is connected with sixth resistance (R6) between the source S of first switch NMOS pipe (M1) and ground connection (GND), the source S of third little signal switch NMOS pipe (M3) and second switch NMOS pipe (M2) all connect ground connection (GND), the source S of first switch NMOS pipe (M1) is as load output.
2. The NMOS high side switch control circuit based on capacitive bootstrap boost of claim 1, wherein: the bootstrap capacitor (C1) can perform buck charging and boost discharging according to the state of the small-signal PNP type triode (Q1), when the small-signal PNP type triode (Q1) is in saturated conduction, the bootstrap capacitor (C1) is in boost discharging, and when the small-signal PNP type triode (Q1) is in cut-off, the bootstrap capacitor (C1) is in buck charging.
3. The NMOS high-side switch control circuit based on capacitive bootstrap boost of claim 2, wherein: the first bypass capacitor (C2) provides continuous and stable forward bias voltage for saturated conduction of the first switch NMOS tube (M1), and when the small-signal PNP triode (Q1) is saturated and conducted, the first bypass capacitor (C2) is charged when the positive potential of the bootstrap capacitor (C1) is increased; when the small-signal PNP triode (Q1) is cut off, the first bypass capacitor (C2) discharges when the potential of the positive electrode of the bootstrap capacitor (C1) falls back.
4. The NMOS high side switch control circuit based on capacitive bootstrap boost of claim 3, wherein: a second bypass capacitor (C3) is connected between the gate G of the third switch NMOS tube (M3) and the ground end GND, the second bypass capacitor (C3) provides continuous and stable forward bias voltage for saturated conduction of the third switch NMOS tube (M3), when the square wave level (V2) is at a high level, the second bypass capacitor (C3) charges, and when the square wave level (V2) is at a low level, the second bypass capacitor (C3) discharges.
5. The NMOS high side switch control circuit based on capacitive bootstrap boost of claim 3, wherein: the first fast diode (D1) can prevent the bootstrap capacitor (C1) from boosting and discharging in the process of conducting when the small-signal PNP type triode (Q1) is saturated, current flows backward to the direct current voltage stabilizing source (V1), a charging loop signal is established for the bootstrap capacitor (C1) when the small-signal PNP type triode (Q1) is cut off, the second fast diode (D2) charges the first bypass capacitor (C2) when the small-signal PNP type triode (Q1) is saturated and conducted, and the first bypass capacitor (C2) is prevented from reversely discharging a front-stage circuit when the small-signal PNP type triode (Q1) is cut off.
6. An NMOS high-side switch control method based on capacitive bootstrap boost, comprising the steps of adopting the NMOS high-side switch control circuit based on capacitive bootstrap boost as defined in any one of claims 1-5, specifically comprising the following steps:
S1, outputting a square wave control level (V2) by a micro controller (1), controlling a small-signal PNP triode (Q1) to be alternately saturated and switched on and off, lifting the potential of the negative electrode of a bootstrap capacitor (C1) when the small-signal PNP triode is saturated and switched on, and lifting the potential of the positive electrode of the bootstrap capacitor (C1) along with the potential of the positive electrode of the bootstrap capacitor, wherein the potential is larger than the potential of a source electrode S of a first switch NMOS tube (M1), the threshold voltage V GS(th) of the first switch NMOS tube (M1) and the sum of voltages between the positive electrode of the bootstrap capacitor (C1) and a grid electrode G of the first switch NMOS tube (M1), so that the first switch NMOS tube (M1) is saturated and switched on, and the positive electrode of a direct current voltage stabilizing source (V1) supplies power to a load through a drain electrode D of the first switch NMOS tube (M1); when the DC voltage stabilizing source is cut off, the positive electrode of the DC voltage stabilizing source (V1) charges the bootstrap capacitor (C1) through the fast diode (D1), the first bypass capacitor (C2) of the later stage discharges the grid electrode G of the first switch NMOS tube (M1) through the current limiting resistor (R3) and maintains the first switch NMOS tube (M1) to be in saturated conduction, and at the moment, the DC voltage stabilizing source (V1) continuously supplies power to a load;
S2, when the micro controller (1) stops outputting the square wave control level (V2), the grid electrode G and the source electrode S of the third small signal switch NMOS tube (M3) gradually lose forward bias voltage, the state is changed from a saturated on state to an off state, at the moment, the grid electrode G of the second switch NMOS tube (M2) is pulled up to the power supply voltage through the second resistor (R2), the grid electrode G and the source electrode S of the second switch NMOS tube (M2) obtain forward bias voltage, the state is changed from the off state to the saturated on state, the grid electrode G voltage of the first switch NMOS tube (M1) is pulled to the ground end (GND) through the drain electrode D of the second switch NMOS tube (M2), the first switch NMOS tube (M1) is changed from the saturated on state to the off state, and at the moment, the direct current voltage stabilizing source (V1) is cut off by the first switch NMOS tube (M1) due to a power supply loop, and power supply to a load is stopped.
7. The method for controlling the NMOS high-side switch based on capacitive bootstrap boost as defined in claim 6, wherein the method comprises the steps of: the square wave level (V2) is generated by the micro controller (1), the amplitude of the square wave level is 0-5V, the square wave level is connected with the fourth resistor (R4), the other small-signal PNP triode (Q1) is controlled by the small-signal NPN triode (Q2), the small-signal PNP triode (Q1) is saturated and conducted when the square wave control level is high, the negative electrode potential of the bootstrap capacitor (C1) is lifted, and the negative electrode voltage of the bootstrap capacitor (C1) is equal to the power supply voltage minus the conduction voltage drop of the emitter and the collector of the small-signal PNP triode (Q1).
8. The NMOS high side switch control method based on capacitive bootstrap boost of claim 6, characterized by: the frequency range of the square wave generated by the micro controller (1) through the timer (2) is as follows: when the bootstrap capacitor (C1) is in the unit charge-discharge period, the electric energy of the first bypass capacitor (C2) at the later stage maintains the first switch NMOS (M1) to be turned on, and the positive potential of the first bypass capacitor (C2) at any moment should be greater than the sum of the voltage drop of the current-limiting resistor R3, the threshold voltage V GS(th) of the first switch NMOS (M1) and the voltage of the source S after being turned on, namely V c2≥VR3+VGS(th)+V1.
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