CN106253896B - Low-Power High-Resolution Sigma-Delta Frequency-to-Digital Converter - Google Patents

Abstract

The invention discloses a sigma-delta frequency digital converter with low power consumption and high resolution. Including frequency detector, loop filter, buffer, voltage controlled oscillator, frequency divider and phase/time quantizer; frequency detector, loop filter, buffer, voltage controlled oscillator, divider The frequency divider is connected in turn, the phase/time quantizer is inserted into the feedback loop of the phase-locked loop composed of other modules, the wiring after the frequency divider of the phase-locked loop is disconnected, and the feedback port of the phase/time quantizer (fb ) is connected with the frequency divider output, and the quantization feedback port (fbq) of the phase/time quantizer is connected with the feedback terminal of the phase detector at the same time. Adopting the scheme of the invention can realize higher resolution, and can further reduce its cost and power consumption.

Description

Low-Power High-Resolution Sigma-Delta Frequency-to-Digital Converter

technical field

The invention belongs to the field of analog-to-digital converters, in particular to a sigma-delta frequency-to-digital converter with low power consumption and high resolution.

Background technique

The frequency-to-digital converter is a kind of analog-to-digital converter, which is used to directly demodulate the analog frequency modulation signal and convert it into a digital output, and is widely used in various frequency modulation (FM) sensors. In such applications, various sensors based on micro-nano machinery (MEMS/NEMS), such as frequency modulation gyroscopes, accelerometers, pressure sensors, and various biochemical sensors for health monitoring, Internet of Things, etc. The power consumption and performance of the device put forward very high requirements on the performance indicators that originally restricted each other. Therefore, a high-performance frequency-to-digital converter that meets application requirements is of great significance, and how to implement the frequency-to-digital converter in an integrated circuit is also of great significance.

As shown in Figure 1, the reset counter consists of a free counter operating at a frequency higher than the measured signal, two D flip-flops and a subtractor. When each rising edge of the input signal arrives, the first D flip-flop (the flip-flop connected to the counter) collects the value of the counter, and the second D flip-flop collects the current value of the first flip-flop. The last two flip-flops are subtracted to obtain the value changed by the counter during each cycle of the input signal. This value is inversely proportional to the frequency of the input signal, and the real frequency value of the input signal can be calculated from this value. However, the quantization noise of this technique is relatively large, and a relatively high operating frequency of the counter is often required to achieve relatively good resolution. But this will consume a large power consumption. At the same time, the higher counting frequency also increases the scale of the subsequent digital processing circuit, consumes more digital hardware, and thus increases the cost.

As shown in Figure 2, the voltage-mode sigma-delta frequency-to-digital converter consists of a phase detector, a loop filter, an analog-to-digital converter converter, and a numerically controlled oscillator. It replaces the voltage-controlled oscillator part of the traditional phase-locked loop with a traditional low-performance low-digit analog-to-digital converter and a numerically controlled oscillator. The analog-to-digital converter quantizes the output voltage of the loop filter. Since the voltage is proportional to the frequency of the input signal, the measured frequency value can be calculated from the output signal of the analog-to-digital converter. At the same time, the numerically controlled oscillator controlled by the analog-to-digital converter provides a feedback signal to keep the entire phase-locked loop oscillating, so that the loop filter in the phase-locked loop can be used to suppress the quantization noise generated by the low-bit analog-to-digital converter, thereby only Use a low-performance ADC while achieving good resolution with a low clock frequency. However, this technique requires a multi-bit analog-to-digital converter, thereby increasing system complexity and circuit cost. This technology uses the analog-to-digital converter output signal to control the numerically controlled oscillator to generate a feedback signal, but because the numerically controlled oscillator samples its control signal at the input clock frequency. Therefore, the bandwidth of the control signal cannot exceed half of the input signal, otherwise aliasing will occur and greatly deteriorate the measurement resolution. This also limits the application of the frequency-to-digital converter, which has very limited space to improve performance by increasing the sampling frequency of the analog-to-digital converter, and it is difficult to achieve high-resolution measurement. Due to the above reasons, the application of the frequency-to-digital converter must reduce the sampling frequency of the analog-to-digital converter when measuring relatively low-frequency signals, and the resolution will be greatly reduced.

As shown in Figure 3, the phase-mode Sigma-Delta frequency-to-digital converter consists of a phase-frequency detector (PFD), a charge pump, a loop filter, a sub-controlled oscillator, and an edge detector. Its principle is to embed the edge detector in the feedback path of the traditional phase-locked loop, quantize the edge of the output signal of the voltage-controlled oscillator to the edge generated by the clock through the clock-controlled edge detector, and feed it back to the PFD . In this way, the output of the VCO is quantized in phase, and then the signal is delayed by another D flip-flop, and the single-bit output signals of the two flip-flops are subtracted to obtain a pulse width proportional to the frequency of the input signal. output signal. From this a frequency measurement of the input signal is derived. At the same time, in this process, the phase quantization noise generated by the edge detector will be suppressed by the loop filter in the phase-locked loop, so as to achieve lower quantization noise. Although the quantization noise is largely suppressed in the output signal of this scheme. However, the energy of the useful signal will also be attenuated with the increase of the clock frequency, so it is difficult to improve the signal-to-noise ratio of the frequency readout circuit, so it is difficult to achieve high resolution. At the same time, because the useful signal and quantization noise decrease at the same speed as the clock frequency increases, the circuit cannot obtain higher measurement resolution by increasing the clock frequency.

Contents of the invention

The object of the present invention is to provide a sigma-delta frequency digital converter with low power consumption and high resolution.

The technical solution that realizes the object of the present invention is: frequency digital converter proposed by the present invention is shown in Figure 4, is made up of following several necessary parts: frequency discrimination phase detector, loop filter, voltage controlled oscillator, Frequency divider, phase/time quantizer. This frequency-to-digital converter is equivalent to inserting the phase/time quantizer (shown in Figure 5) into the feedback loop of the phase-locked loop composed of the remaining blocks. Disconnect the wiring after the frequency divider of the phase-locked loop, connect the feedback port (fb) of the phase/time quantizer to the output of the frequency divider, and connect the quantization feedback port (fbq) of the phase/time quantizer to the phase detector The feedback terminal of the device is connected.

When working, the signal to be tested is connected to one end of the phase detector, and an external clock signal is connected to the phase/time quantizer at the same time. After that, the ratio between the external clock signal and the measured signal can be read from the digital output port of the phase/time quantizer. The real frequency of the signal under test can be estimated by this value.

At the same time, since the phase quantization noise generated by the phase/time quantizer is shaped by the loop filter in the PLL system, the power spectral density seen at the output of the quantization noise will be much lower at low frequencies than conventional frequency-to-digital converters.

The phase/time quantizer consists of registers, counters, and edge synchronizers. There are 2 inputs and 2 outputs in total, which are feedback signal input (fb), clock signal input (clk), quantization feedback signal output (fbq) and digital output (Do). Its connection method is shown in Figure 5. First, the external clock (clk) controls the reset counter to count continuously and freely. At the same time, the edge synchronizer uses the feedback signal (fb) synchronously connected to the external clock to generate a synchronized quantized feedback signal (fbq). Use the synchronized fbq signal as the trigger signal of the two registers, let register 1 collect the output of the counter, register 2 collect the output of register 1, and subtract the value of register 1 from register 2 as a digital signal output (Do), thus completing The function of the entire phase/time quantizer.

Compared with the prior art, the present invention has significant advantages: (1) High-order Sigma-Delta frequency-to-digital converter is realized by means of quantized phase, and a lower clock frequency realizes high-resolution measurement without introducing voltage modulus converter, ensuring that the design is low-cost and low-power. (2) While the frequency-to-digital converter suppresses quantization noise by boosting the frequency, the useful signal cannot be attenuated. At the same time, aliasing cannot occur, and finally a higher resolution can be achieved. (3) The invention can be realized by application-specific integrated circuit technology, thereby further reducing its cost and power consumption.

Description of drawings

Figure 1 is a working principle diagram of the reset counter.

Figure 2 is a voltage-mode sigma-delta frequency-to-digital converter.

Figure 3 is a phase-mode sigma-delta frequency-to-digital converter.

FIG. 4 is a block diagram of the frequency-to-digital converter system proposed by the present invention.

FIG. 5 is a schematic diagram of the quantizer in FIG. 4 .

Fig. 6 is a timing diagram of various parts in the quantizer.

Figure 7 is an XOR phase detector.

Figure 8 is a tri-state phase detector.

Figure 9 shows several interchangeable forms of passive filters.

Figure 10 shows several interchangeable forms of active filters.

Detailed ways

The frequency-to-digital converter of the present invention is shown in Figure 4, and is composed of the following parts connected in the order shown in the figure: a three-state frequency and phase detector, a passive second-order second-type loop filter, a buffer, and a ring voltage control Oscillator, 2N frequency divider, quantizer.

The input signal of the system as a whole is a square wave signal of the frequency to be measured, and the output signal is the clock frequency divided by the output value of the quantizer, which is used as the measured value of the frequency of the input signal.

The quantizer is shown in Figure 5, which consists of an edge synchronizer (edge detector), a counter, two serial registers, and a subtractor.

Wherein, the edge synchronizer synchronizes the rising edge of the feedback signal fb to the rising edge of the clock, and generates the fbq signal for feeding back to the phase detector.

The counter counts continuously under the control of the clock, and the count value increases by 1 at each rising edge of the clock.

The two registers are controlled by the fbq signal. When each fbq rising edge arrives, register 1 samples the output value of the current counter. Register 2 samples the current output value of Register 1. As shown in Figure 6.

The subtractor can be a clock-controlled subtractor or a combinational logic subtractor, which is used to obtain the result (Do) of register 2-register 1, which represents the number of rising edges of the clock signal in each cycle of the fbq signal . This result is absolutely accurate because the rising edge of fbq and the rising edge of clock are synchronized. As shown in Figure 6.

In order to obtain the frequency of the measured signal through the output signal (Do) of the quantizer, it is necessary to divide the clock frequency by Do, which can be realized by digital combinational logic.

The quantization error generated by the edge synchronizer sampling fb will be adjusted by the phase-locked loop, especially by the loop filter, which is equivalent to the input or output noise and is suppressed in the specified frequency band.

Under this design, no matter how high the clock frequency is, the sampling rate of the quantization noise e(n) generated by the edge synchronizer is equal to the input signal, so noise aliasing does not occur. The increase of the clock frequency is equivalent to the increase of quantization bits of the quantizer.

As shown in Figure 7-10, the phase detector can be realized by one of the following forms: XOR phase detector, multiplier (mixer), and three-state phase detector. Among them, the three-state phase detector can be used directly, and the XOR phase detector and the multiplier need an additional auxiliary system locking circuit, such as a three-state frequency detector with a large dead zone in parallel with the above-mentioned phase detectors.

The phase detector and filter of the system can be implemented by a fully differential architecture or a single-ended architecture. The difference lies in whether the charge pump in the phase detector is implemented in a fully differential form.

The loop filter can be replaced by an active filter, as well as higher order filters. As shown in the figure (only single-ended structure is shown in the figure), the passive filter can be a second-order type I (Type I, order 2), a second-order type II (Type II, order2), a third-order type I ( Type I, order 3), three-order type II (Type II, order 3). The same model and order can also be selected for active filters.

At the same time, if the measured frequency changes periodically, the filter can also be replaced by a band-pass filter or an oscillator, thereby realizing a band-pass Sigma-Delta frequency-to-digital converter.

VCO can use not only ring sub-controlled oscillator (Ring-VCO) but also inductor-capacitor sub-controlled oscillator (LC-VCO).

The frequency divider can also adopt a fractional frequency divider (fractional-N divider).

The present invention can be realized by discrete device analog circuit chips, and can also be realized by application-specific integrated circuit (ASIC) technology.

When calculating the frequency of the measured signal through the output digital signal (Do) of the quantizer, the consumption of combinational logic circuit hardware can also be reduced by sequential logic. At the same time, the calculation can also be completed in the manner of a lookup table.

Claims (1)

1. a kind of high-resolution sigma-delta frequency digital quantizer of low-power consumption, it is characterised in that: including frequency and phase discrimination Device, loop filter, buffer, voltage controlled oscillator, frequency divider and phase/time quantization device；Phase frequency detector, loop filtering Device, buffer, voltage controlled oscillator, frequency divider are sequentially connected, and phase/time quantization device insertion is by phase frequency detector, loop filtering In the feedback control loop for the phaselocked loop that device, buffer, voltage controlled oscillator, frequency divider form, by connecing after the frequency divider of phaselocked loop Line disconnects, and phase/time quantization device feedback port (fb) and frequency divider are exported and are connected, while by phase/time quantization device Quantization feedback port (fbq) be connected with the feedback end of phase discriminator；The phase/time quantization device is by register, counter, side It is formed along synchronizer；Equipped with 2 inputs and 2 outputs, respectively feedback signal input (fb), clock signal input, quantization is anti- Feedback signal exports (fbq) and digital signal output (Do)；Firstly, external clock control reset count device circulation is continuously freely counted Number, meanwhile, edge synchroniser generates the quantization feedback signal after synchronizing using the feedback signal (fb) of the synchronous access of external clock (fbq)；The fbq signal after synchronizing is used as the trigger signal of two registers, allows the first register (1) acquisition counter device Output, the second register (2) acquires the output of register 1, and the value that the second register (2) subtracts the first register (1) is made (Do) is exported for digital signal, to complete entire phase/time quantization device function.