CN103487648A - Sigma-delta PLL frequency measuring circuit and method - Google Patents

Abstract

The invention provides a sigma-delta PLL frequency measurement circuit and method. The circuit includes a shaping circuit, a phase detector, a loop filter, an ADC and a delay link arranged sequentially from the input end, and the output end of the delay link is fed back to the phase detector through a counter; the frequency measurement method is: shaping circuit After the signal to be tested is filtered and amplified, it is converted into a square wave signal of the same frequency; the phase detector measures the zero-crossing time difference between the square wave signal and the counter output signal, and outputs a pulse current signal whose area is proportional to the time difference; the loop filter Integrate and filter the output current of the phase detector and convert it into a voltage signal; the ADC converts the analog voltage output by the loop filter into a digital signal; the delay link delays the digital signal output by the ADC, and determines the signal to be tested accordingly. Frequency; the counter generates a counter output signal whose clock period is proportional to the delayed digital signal and inputs it to the phase detector. The invention has strong anti-noise capability, high resolution and easy realization for frequency measurement.

Description

Sigma-delta PLL frequency measurement circuit and method

technical field

The invention relates to the field of electronics and time-frequency measurement, in particular to a sigma-delta (Σ-Δ) PLL (Phase Locked Loop, phase-locked loop) frequency measurement circuit and method.

Background technique

In electronic technology, frequency has always been one of the most basic parameters, and has a very close relationship with the measurement scheme and measurement results of many electrical parameters, so the measurement of frequency is also particularly important. In recent years, with the development of electronic information technology, the precision of crystal oscillators and resonant sensors with frequency as output signal is constantly improving, and their applications are becoming more and more extensive. The development of matching low-noise frequency measurement circuits is also It seems more and more urgent.

At present, there are three basic principles of frequency measurement circuits commonly used in the domestic and foreign markets: (1) measure the frequency of the periodic signal by performing Fourier transform on the measured signal, (2) measure the frequency of the measured frequency signal within the standard gate time The measured frequency value is obtained by counting the number of cycles. (3) Based on the frequency measurement circuit of the phase-locked loop, the frequency identification is realized by using the characteristic that the control signal of the voltage-controlled oscillator (VCO) is proportional to the frequency; among them, the first (1 ) technology has a certain anti-noise performance, but it is inevitable to truncate the time domain in the process of Fourier transform. Domain signal characteristics, so the accuracy of its measurement results is poor. Type (2) technology can complete frequency measurement and digital output at the same time, and the sampling frequency of this system is only twice the frequency of the signal to be measured, there is no high requirement for oversampling rate, the measurement is convenient, and the reading is direct. There are quantization errors caused by counting, which limits the improvement of frequency measurement accuracy; although there are improved multi-cycle synchronization methods and delay chain methods to limit the quantization errors, the multi-cycle synchronization method is at the expense of system bandwidth, while the delay chain method The precision requirements of the delay unit are extremely high, and it is difficult to realize, and there are problems such as uneven distribution of delay chain length and delay jitter, so that the actual precision is far lower than the theoretical value. Type (3) technology first locks the frequency of the signal under test through a phase-locked loop, outputs a voltage signal proportional to the signal under test, and then converts the voltage signal into a digital frequency through an analog-to-digital converter (ADC). The measured frequency is converted into a digital signal. The advantage of the phase-locked loop frequency measurement method is that the circuit is simple and easy to implement, but the VCO in the phase-locked loop itself will introduce phase noise, and the VCO has nonlinearity and temperature sensitivity, which will affect the final frequency measurement. accuracy.

To sum up, the currently commonly used frequency measurement methods have the problems of high noise and low resolution, and it is difficult to adapt to the high-precision frequency reading requirements of new crystal oscillators and resonant sensors.

Contents of the invention

The object of the present invention is to provide a sigma-delta PLL frequency measurement circuit and method with strong anti-noise capability, high resolution and easy implementation.

The technical solution that realizes the object of the present invention is:

A sigma-delta PLL frequency measurement circuit, including a shaping circuit, a phase detector, a loop filter, an ADC and a delay link arranged sequentially from the input end, and the output end of the delay link is input to the phase detector through counter feedback , wherein: the shaping circuit filters and amplifies the signal to be tested, and converts it into a square wave signal V _out of the same frequency; the phase detector measures the zero-crossing time difference between the shaped signal V _out and the counter output signal C _out , and output the pulse current signal I _out whose area is proportional to the time difference e _n ; the loop filter integrates and filters the output current I _out of the phase detector, and converts it into a voltage signal; ADC filters the loop The analog voltage output by the converter is converted into a digital signal N; the delay link is to delay the digital signal N output by the ADC by one clock cycle; the counter generates a counter output signal C _out whose clock cycle is proportional to the delayed digital signal N, and The counter output signal C _out is input to the phase detector.

A sigma-delta PLL frequency measurement method, the steps are as follows:

Step 1, after the signal to be tested is filtered and amplified by the shaping circuit, it is converted into a square wave signal V _out of the same frequency;

Step 2, the phase detector measures the time difference e _n between the zero-crossing point of the shaped signal V _out and the output signal C _out of the counter, and outputs a pulse current signal I _out whose area is proportional to the time difference e _n ;

Step 3, the loop filter integrates and filters the output current I _out of the phase detector, and converts it into a voltage signal;

Step 4, the ADC converts the analog voltage output by the loop filter into a digital signal N;

Step 5, the delay link delays the digital signal N output by the ADC for one clock cycle, and determines the frequency of the signal to be tested according to the delayed digital signal N;

Step 6: The counter generates a counter output signal C _out whose clock period is proportional to the delayed digital signal N, and inputs the counter output signal C _out to the phase detector for phase difference comparison with the shaped signal V _out to be tested.

Compared with the prior art, the significant advantages of the present invention are: (1) the VCO is replaced by a counter, which avoids the extra phase noise, nonlinearity and temperature sensitivity brought by the VCO; (2) the transfer function is Σ-Δ The structure of the modem can modulate the quantization noise brought by the counter to the high-frequency region, move it out of the bandwidth range of the signal to be tested, and greatly improve the frequency measurement resolution within the bandwidth range; under the premise that the quantization noise remains unchanged, it can By increasing the loop order to further improve the resolution performance, it has a strong anti-noise ability; (3) The structure is simple, the flexibility is large, and the requirements for the device are low: first, the crystal oscillator frequency value used as the counter clock reference is not required. High; in addition, because the ADC performs digital-to-analog conversion on the DC voltage after the integration link and the filter link, there are no excessive requirements on the number of bits and the sampling rate of the ADC.

Description of drawings

Fig. 1 is the structural representation of sigma-delta PLL frequency measuring circuit of the present invention.

Fig. 2 is the waveform schematic diagram of the signal in the sigma-delta PLL frequency measurement method of the present invention.

Fig. 3 is a structural diagram of a loop filter adopting an integrator cascaded multi-channel feedforward structure in the sigma-delta PLL frequency measurement circuit of the present invention.

Fig. 4 is a schematic diagram of the structure of the sigma-delta PLL frequency measurement circuit of the present invention after removing the first-stage feedforward path in the integrator cascaded multi-channel feedforward structure and adding lead compensation.

Fig. 5 is the structural representation of the filter link in the sigma-delta PLL frequency measurement loop of different orders among the present invention, wherein (a) is the structural representation of the filter link in the second-order sigma-delta PLL frequency measurement loop, (b) (c) is a structural schematic diagram of the filtering link in the fourth-order sigma-delta PLL frequency measurement loop.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

In conjunction with Fig. 1, the sigma-delta PLL frequency measurement circuit of the present invention is a closed-loop negative feedback system as a whole, including a shaping circuit 100, a phase detector 200, a loop filter 300, an ADC400 and a delay set sequentially from the input end link 500, and the output end of the delay link 500 is fed back to the phase detector 200 through the counter 600, wherein: the shaping circuit 100 filters and amplifies the signal to be tested, and converts it into a square wave signal V _out of the same frequency; the phase detector 200, measure the zero-crossing time difference between the signal V _out to be tested after shaping and the counter output signal C _out , and output the pulse current signal I _out whose area is proportional to the time difference e _n ; the loop filter 300, to the phase detector 200 The output current I _out is integrated and filtered, and converted into a voltage signal; ADC400 converts the analog voltage output by the loop filter 300 into a digital signal N; the delay link 500 performs a clock on the digital signal N output by the ADC400 Periodic delay; the counter 600 generates a counter output signal C _out whose clock period is proportional to the delayed digital signal N, and inputs the counter output signal C _out to the phase detector 200 .

The sigma-delta PLL frequency measurement method of the present invention mainly controls the output signal of the counter 600, so that the output signal C _out of the counter 600 is kept in phase with the signal V _out to be measured after shaping, thereby simultaneously realizing the frequency of the signal to be measured in one step. demodulation and digitization. In order to maintain the phase consistency, first use the phase detector 200 to measure the zero-crossing time difference between the shaped signal V _out and the counter output signal C _out e _n =t _n -τ _n , and generate the corresponding area A _n =K The pulse current signal I _out of _d × (t _n -τ _n ) is shown in Figure 2, where K _d is the phase detector 200 gain, t _n is the zero-crossing time of the signal V _out after shaping, τ _n is the zero-crossing time of the counter output signal C _out , and the subscript n represents the number of the time period. Then, A _n is used to estimate the next time period Δt _n+1 of the reshaped signal V _{out to} be tested. After passing through the loop filter 300 and ADC 400, A _n becomes a digital signal N _n+1 , so that the counter 600 generates a time period of The counter output signal C _out of 2N _n+1 ×T _ref is compared with the phase difference of V _out in the next period, where T _ref is the period of the reference signal generated by the crystal oscillator. It can be seen from the schematic diagram of the signal waveform in Fig. 2 that there is a delay of one clock cycle between measuring the time difference e _n and using A _n to estimate the next time period Δt _n+1 , so a delay link 500 is set in the feedforward network, The specific steps of frequency measurement are as follows:

Step 1, after the signal to be tested is filtered and amplified by the shaping circuit 100, it is converted into a square wave signal V _out of the same frequency, which is the shaped signal V _out to be tested;

Step 2, the phase detector 200 measures the time difference en between the zero-crossing point of the shaped signal V _out and the output signal C _out of the counter, and outputs a pulse current signal I _out whose area is proportional to the time difference _{en ;}

Step 3, the loop filter 300 integrates and filters the output current _Iout of the phase detector 200, and converts it into a voltage signal;

Step 4, the ADC400 converts the analog voltage output by the loop filter 300 into a digital signal N;

Step 5, the delay link 500 delays the digital signal N output by the ADC400 by one clock period, the delayed digital signal N is proportional to the clock period of the signal to be tested, and the frequency of the signal to be tested is determined according to the delayed digital signal N ;

Step 6, the counter 600 generates a counter output signal C _out whose clock period is proportional to the delayed digital signal N, and inputs the counter output signal C _out to the phase detector 200 for phase difference comparison with the shaped signal V _out .

Combined with the schematic diagram of the signal waveform in the sigma-delta (Σ-Δ) PLL frequency measurement method shown in Figure 2, combined with the working principle of the counter 600 in the figure, it can be obtained that τ _n+1 -τ _n =N _n+1 ×T _ref , after z transformation, it is easy to know that the transfer function C(z) of the counter 600 is:

$\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}}{{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}}$

Combined with the structural schematic diagram of the sigma-delta PLL frequency measurement circuit shown in Figure 1, the output term N(z) of the sigma-delta PLL frequency measurement circuit can be expressed as:

$\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; ]</span>\frac{\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}$

Wherein, F(z) is the transfer function of the loop filter 300 , A _Q is the linear gain of the ADC 400 , and q(z) is the quantization noise introduced by the counter 600 .

In Figure 2, the period of the signal V _out after shaping is T=2Δt _n =2(t _n -t _n-1 ), which can be obtained by z transformation:

T(z)=2t(z)(1-z ^-1 )

Substituting the above formula T(z) into the expression of the output item N(z), we can get:

$\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; [</span>\frac{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; ]</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}$

Considering the integrator cascade multi-channel feedforward structure of the loop filter transfer function F(z) and C(z)=T _ref /(1-z ^-1 ), it can be seen that the above formula is a typical sigma- The transfer function of the delta modem. The counter 600 converts the digital signal N into an analog time period and functions as a DAC.

Therefore, the frequency measurement method of the present invention has the characteristics of a sigma-delta modem, and can modulate the quantization noise q introduced by the counter 600 into the high-frequency region, move the noise out of the bandwidth of the signal to be measured, and improve the frequency resolution within the bandwidth of the signal to be measured Rate. At the same time, according to the characteristics of the sigma-delta modem, the frequency resolution can be improved by increasing the order of the sigma-delta frequency measurement loop under the condition that the magnitude of the quantization noise q remains unchanged.

If the frequency measurement loop gain of sigma-delta PLL is K _d A _Q z ^-1 F(z)C(z)>>1, then the output term N(z) can be written as:

$\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; T</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ref</span>}}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; q</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; K</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; Q</span>}}{\mathrm{<span\; class="notranslate">\; z</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; C</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; z</span>}<span\; class="notranslate">\; )</span>}$

It can be seen that in the sigma-delta PLL frequency measurement circuit, the signal frequency 1/T of the accelerometer oscillator can be determined by the digital signal N, and the loop gain K _d A _Q z ^-1 F(z)C(z) can be increased It can also effectively suppress the influence of quantization noise q.

As shown in Figure 3, the loop filter 300 in the sigma-delta PLL frequency measurement circuit of the present invention adopts an integrator cascaded multi-channel feedforward structure, and the structural form of the integrator cascaded multi-channel feedforward is more suitable for sigma-delta PLL The loop filter 300 in the frequency measuring circuit, because this structure can avoid the existence of multiple feedback paths, the only feedback path of the sigma-delta PLL adopting this structure is the counter 600. The counter 600 converts the digital signal N into an analog time period and functions as a DAC. If an integrator cascaded multi-channel feedback structure is used in the sigma-delta PLL frequency measurement circuit, multiple additional DACs are required to convert the digital signal N into an analog voltage, which will increase the implementation difficulty and cost.

In conjunction with Fig. 3, the pulse current signal _Iout output by the phase detector 200 is multiplied by the gain A in the first-stage feedforward path FF1 and then added to other feedforward paths, and in other feedforward paths, the pulse current The signal I _out must pass through the integration link 310 to become a voltage quantity, and finally the current and the voltage must be directly added, which is difficult to realize in the circuit. Therefore, the first-stage feedforward path FF1 is removed from the loop filter 300, and a lead compensation link 700 is added to ensure the stability of the loop.

As shown in FIG. 4 , the structure diagram of the sigma-delta PLL frequency measurement circuit after removing the first-stage feedforward path in the cascaded multi-channel feedforward structure of integrators and adding the lead compensation link 700 is shown. The loop filter 300 after removing the first-stage feed-forward path FF1 can be divided into two parts: an integrating link 310 and a filtering link 311, wherein the gain of the integrating link 310 is K _I . At this time, the structure of the sigma-delta PLL frequency measurement circuit is very similar to that of a typical phase-locked loop PLL. In a typical phase-locked loop, the output signal of the phase detector is processed by an integrator and a filter, and then fed back to a voltage-controlled oscillator. Just as the order of the phase-locked loop is determined by the filter, the transfer function G(z) of the filter link 311 also determines the loop order of the sigma-delta PLL frequency measurement circuit. The lead compensation link 700 for maintaining the stability of the loop can be placed between the loop filter 300 and the ADC400 in the feedforward network of the frequency measurement loop, and implemented by an analog circuit based on an integrated operational amplifier; the lead compensation link 700 can also be placed between the delay link 500 and the counter 600 in the feedback network of the frequency measurement loop, and it can be realized by using a digital circuit. It is simpler to implement in digital circuits and can save additional analog circuits.

Fig. 5 is the structural representation of the filter link in the sigma-delta PLL frequency measurement loop of different orders among the present invention, wherein 5 (a) is the structural representation of the filter link in the second-order sigma-delta PLL frequency measurement loop, 5 ( b) is a structural schematic diagram of the filtering link in the third-order sigma-delta PLL frequency measurement loop, and 5(c) is a structural schematic diagram of the filtering link in the fourth-order sigma-delta PLL frequency measurement loop. The higher the order, the stronger the ability to suppress the quantization noise q, and the higher the frequency resolution, but the circuit will be more complicated. It can be seen from Fig. 4 that the loop filter 300 is located in the front stage of the ADC400 and should be implemented by an analog integrated circuit, wherein the integration link 310 is realized by an integrator based on an integrated operational amplifier; and the filter link 311 must first use the state space method The discrete transfer function of the digital filter is converted into an equivalent continuous function, and then realized by an analog filter circuit based on an integrated operational amplifier.

In summary, the sigma-delta PLL frequency measurement circuit and method of the present invention replace the VCO with a counter, avoiding the extra phase noise, nonlinearity and temperature sensitivity brought by the VCO; the transfer function is the structure of a Σ-Δ modem form, it can modulate the quantization noise brought by the counter to the high-frequency region, move it out of the bandwidth range of the signal to be measured, and greatly improve the frequency measurement resolution within the bandwidth range; under the premise that the quantization noise remains unchanged, the It has a strong anti-noise ability; the structure is simple, the flexibility is large, and the requirements for the device are low: first, the crystal oscillator frequency value as the counter clock reference is not high; in addition, because the ADC is The digital-to-analog conversion is performed on the DC voltage after the integration link and the filter link, so there are no excessive requirements on the number of digits and sampling rate of the ADC.

Claims (7)

1. A sigma-delta PLL frequency measurement circuit, characterized in that, comprises a shaping circuit (100), a phase detector (200), a loop filter (300), and an ADC (400) arranged sequentially from the input end and the delay link (500), and the output terminal of the delay link (500) is fed back to the phase detector (200) through the counter (600), wherein: A shaping circuit (100), after filtering and amplifying the signal to be tested, converts it into a square wave signal V _out of the same frequency; A phase detector (200), measuring the zero-crossing time difference between the shaped signal V _out and the counter output signal C _out , and outputting a pulse current signal I _out whose area is proportional to the time difference e _n ; A loop filter (300), integrating and filtering the output current I _out of the phase detector (200), and converting it into a voltage signal; ADC (400), converting the analog voltage output by the loop filter (300) into a digital signal N; A delay link (500), delaying the digital signal N output by the ADC (400) by one clock cycle; The counter (600) generates a counter output signal C _out whose clock period is proportional to the delayed digital signal N, and inputs the counter output signal C _out to the phase detector (200). 2. The sigma-delta PLL frequency measurement circuit according to claim 1, wherein the loop filter (300) adopts an integrator cascaded multi-channel feedforward structure. 3. The sigma-delta PLL frequency measurement circuit according to claim 2, characterized in that the integrator cascaded multi-channel feedforward structure adopted by the loop filter (300) removes the first integration link (301 ) before the first-stage feed-forward path, and correspondingly add a lead compensation link (700) in the measurement circuit. 4. The sigma-delta PLL frequency measurement circuit according to claim 3, characterized in that, the lead compensation link (700) is set between the loop filter (300) and the ADC (400), or is set at between the delay link (500) and the counter (600). 5. The sigma-delta PLL frequency measurement circuit according to claim 3, characterized in that, the loop filter (300) after removing the first-stage feedforward path is divided into an integral link (310) and a filter link (311) , wherein the integration link (310) uses an integrator based on an integrated operational amplifier; the filtering link (311) converts the discrete transfer function of the digital filter into an equivalent continuous transfer function, and then uses an analog filter circuit based on an integrated operational amplifier. 6. A sigma-delta PLL frequency measurement method, characterized in that the steps are as follows: Step 1, after the signal to be tested is filtered and amplified by the shaping circuit (100), it is converted into a square wave signal V _out of the same frequency; Step 2, the phase detector (200) measures the time difference en between the zero-crossing point of the reshaped signal V _out and the output signal C _out of the counter, and outputs a pulse current signal I _out whose area is proportional to the time difference _{e n ;} Step 3, the loop filter (300) integrates and filters the output current I _out of the phase detector (200), and converts it into a voltage signal; Step 4, the ADC (400) converts the analog voltage output by the loop filter (300) into a digital signal N; Step 5, the delay link (500) delays the digital signal N output by the ADC (400) for one clock cycle, and determines the frequency of the signal to be tested according to the delayed digital signal N; Step 6, the counter (600) generates a counter output signal C _out whose clock cycle is proportional to the delayed digital signal N, and inputs the counter output signal C _out to the phase detector (200) and the shaped signal V _out Make a comparison. 7. sigma-delta PLL frequency measuring method according to claim 6, is characterized in that, the digital signal N after the delay described in step 5 is directly proportional to the clock cycle of signal to be measured.

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