CN102902647B - Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) - Google Patents
Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) Download PDFInfo
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- CN102902647B CN102902647B CN201210361085.7A CN201210361085A CN102902647B CN 102902647 B CN102902647 B CN 102902647B CN 201210361085 A CN201210361085 A CN 201210361085A CN 102902647 B CN102902647 B CN 102902647B
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Abstract
本发明提供一种设置在I2C从机印刷电路板的ASIC芯片和印刷电路板。该ASIC芯片包括至少两个功能模块、与功能模块的个数相同的Slave I2C控制模块和一个存储模块；其中，功能模块与对应的Slave I2C控制模块连接；Slave I2C控制模块通过I2C总线与Master I2C控制模块连接，Slave I2C控制模块还与存储模块连接。本发明实施例提供的ASIC芯片具有多个I2C芯片的功能，不需要对Master I2C控制模块进行改进即能够对所述AISC芯片进行访问。
The invention provides an ASIC chip and a printed circuit board arranged on an I2C slave printed circuit board. The ASIC chip includes at least two functional modules, the same Slave I2C control module and a storage module as the number of functional modules; wherein, the functional module is connected to the corresponding Slave I2C control module; the Slave I2C control module is connected to the Master I2C through the I2C bus The control module is connected, and the Slave I2C control module is also connected with the storage module. The ASIC chip provided by the embodiment of the present invention has the function of multiple I2C chips, and can access the AISC chip without improving the Master I2C control module.
Description
Technical Field
The embodiment of the invention relates to the electronic technology, in particular to an ASIC chip arranged on an I2C slave printed circuit board and the printed circuit board.
Background
An internal Integrated Circuit (also called Inter-Integrated Circuit, abbreviated as I2C) is a two-wire serial bus used to connect a microcontroller and its peripheral devices, and is a bus standard widely used in the field of microelectronic communication control. According to the standard I2C protocol, each I2C device has a unique I2C address for accessing the device. The host identifies the other I2C devices by this address. The master refers to a device for initializing the I2C bus, and the other I2C devices addressed by the master are called slaves.
The Master's I2C control module is commonly referred to as the Master I2C control module, and the Slave's I2C control module is commonly referred to as the Slave I2C control module. When a plurality of Slave I2C control modules are arranged on a printed circuit board of the Slave, the Master I2C module accesses the Slave I2C control module through an I2C address. The Master I2C control module may be a central processing unit (collectively referred to as a central processing unit, CPU), or other logic processing device.
In order to replace the I2C chips with an Application Specific Integrated Circuit (ASIC) chip, the modules including the I2C chip functions may be integrated into an ASIC chip. However, since an I2C chip has only one I2C address and an ASIC chip also has only one I2C address, software modification of the Master I2C control module is required so that the Master I2C control module can access a plurality of different modules integrated on the ASIC chip. This increases the software upgrade maintenance cost, thereby increasing the cost and complexity of using ASIC chips.
Disclosure of Invention
The embodiment of the invention provides an ASIC chip arranged on an I2C slave printed circuit board and the printed circuit board, which can identify different I2C control modules in the ASIC chip integrated on the I2C slave printed circuit board under the condition of not improving Master I2C module software, thereby reducing the cost and complexity of using the ASIC chip.
A first aspect of the present invention provides an ASIC chip provided at an I2C slave printed circuit board, the ASIC chip including: the device comprises at least two functional modules, SlaveI2C control modules and a storage module, wherein the number of the SlaveI2C control modules is the same as that of the functional modules; the function module is connected with a corresponding Slave I2C control module; the Slave I2C control module is connected with the Master I2C control module through an I2C bus, and the Slave I2C control module is also connected with the storage module.
In the first aspect of the present invention, a first possible implementation is: the Slave I2C control module is configured to receive an I2C address broadcasted by a Master I2C control module, match an I2C address broadcasted by the Master I2C control module with an I2C address of the Slave I2C control module, and if it is determined that the Slave I2C control module is an access object of the Master I2C control module, the Slave I2C control module is further configured to perform information interaction with the Master I2C control module.
In the first aspect of the present invention, or in a first possible implementation of the first aspect of the present invention, a second possible implementation is: the ASIC chip also comprises one or more mode control lines for transmitting gating signals to the ASIC chip, so that the Slave I2C control module in the ASIC chip receiving the gating signals receives the I2C address sent by the Master I2C control module.
A second aspect of the present invention provides a printed circuit board of an I2C slave, including at least one ASIC chip, where at least one of the ASIC chips is described in the first aspect of the present invention, or the first possible implementation of the first aspect of the present invention, or the second possible implementation of the first aspect of the present invention.
The ASIC chip provided by this embodiment integrates at least two function modules, and each function module is connected with a different Slave I2C control module, so that the Master I2C control module can access different Slave I2C control modules inside the ASIC chip through different I2C addresses, and then access different function modules through different Slave I2C control modules. Therefore, the Master I2C control module does not need to be improved, and the use cost and the complexity of an ASIC chip are reduced.
Drawings
Fig. 1 is a schematic structural diagram of an ASIC chip according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a printed circuit board according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another printed circuit board according to an embodiment of the present invention.
Detailed Description
Fig. 1 is a schematic structural diagram of an ASIC chip disposed on an I2C slave pcb according to an embodiment of the present invention. The ASIC chip with the I2C bus provided in this embodiment includes at least two functional modules, a Slave I2C control module and a memory module, which are the same in number as the above functional modules.
As shown in fig. 1, the ASIC chip includes N Slave I2C control modules and N functional modules, where N is a natural number greater than 1. The functional module 21, the functional modules 22, … …, and the functional module 2N are functional modules in N I2C chips having different functions. The Slave I2C control module 11, the Slave I2C control modules 12, … …, and the Slave I2C control module 1N are Slave I2C control modules in the N I2C chips, respectively.
Each function module is respectively connected with one Slave I2C control module, and different function modules are controlled by different Slave I2C control modules. As shown in fig. 1, the function module 21 is controlled by the Slave I2C control module 11, the function module 22 is controlled by the Slave I2C control module 12, and so on, the function module 2N is controlled by the Slave I2C control module 1N.
The Slave I2C control module is connected to the Master I2C control module via an I2C bus. The Slave I2C control module is also coupled to the memory module. The memory modules include a dedicated memory module that each Slave I2C controls module access. As shown in fig. 1, the memory modules 31 include a Slave I2C dedicated memory module for access by the control module 11, a Slave I2C dedicated memory module for access by the control module 12, and … …, and a Slave I2C dedicated memory module for access by the control module 1N. For example, in the embodiment of the present invention, the storage module may be a register group formed by a plurality of registers, or may refer to a register.
The Slave I2C control module controls the function module, stores data in a special storage module connected with the Slave I2C control module in the storage module, and controls the function module through the data.
The Master I2C control module broadcasts the I2C address of the Slave I2C control module to be accessed to each Slave I2C control module of the ASIC chip. Each Slave I2C control module in the ASIC chip matches the broadcasted I2C address with its I2C address, and if it is determined that it is the access object of the Master I2C control module, it interacts with the Master I2C control module, so that the Master I2C control module can access to different Slave I2C control modules in the ASIC chip.
For example, the Master I2C control module broadcasts the I2C address to the Slave I2C control module in the ASIC chip, and the Slave I2C control module 11 or the Slave I2C control module 12 matches the I2C address of itself after receiving the I2C address, and determines whether itself is an access object of the Master I2C control module. If the destination address in the broadcast message is the I2C address of the Slave I2C control module 11, the Slave I2C control module 11 can interact with the Master I2C control module. For example, according to the indication of the Master I2C control module, the access function module 11 and a dedicated memory module in the memory module can send the obtained data to the Master I2C control module, thereby implementing information interaction between the Master I2C control module and the Slave I2C control module in the ASIC chip.
Optionally, one or more mode control lines may be further disposed on the ASIC chip in the above-described scheme. When the I2C Slave comprises more than one ASIC chip on the printed circuit board, the strobe signal is transmitted to one ASIC chip on the printed circuit board through the mode control line, so that the Slave I2C control module in the ASIC chip receiving the strobe signal receives the address information sent by the Master I2C control module.
For example, the input end of the power supply on the printed circuit board is connected with a pull-up resistor, and after the printed circuit board is powered on, the power supply inputs a high-level signal to the mode control line through the pull-up resistor, wherein the high-level signal is a gating signal.
The number of the mode control lines can be set according to actual needs. If the number of the mode control lines is n, the n mode control lines can gate 2n ASIC chips at most. For example, if there are two mode control lines, the high-low level signals can be adjusted so that the two mode control lines can output 4 signals (00, 01, 10, 11) at most, and thus the two mode control lines can gate 4 chips at most.
The ASIC chip provided by this embodiment integrates at least two function modules, and each function module is connected with a different Slave I2C control module, so that the Master I2C control module can access different Slave I2C control modules inside the ASIC chip through different I2C addresses, and then access different function modules through different Slave I2C control modules. Therefore, the Master I2C control module does not need to be improved, and the use cost and the complexity of an ASIC chip are reduced.
The embodiment of the invention also provides a printed circuit board of the I2C slave computer, which comprises at least one ASIC chip. At least one of the ASIC chips is the ASIC chip shown in fig. 1.
For ease of illustration, the printed circuit board shown in fig. 2 includes an ASIC chip 41 and an ASIC chip 42. The ASIC chip 41 is the ASIC chip shown in fig. 1, and the ASIC chip 42 includes a functional module, a Slave I2C control module, and a storage module.
As shown in fig. 2, the I2C Slave further includes a mode control line on the pcb for transmitting a gating signal to the ASIC chip 41 or the ASIC chip 42, so that the Slave I2C control module in the ASIC chip 41 or the ASIC chip 42 receives the address information broadcasted by the Master I2C control module.
To describe the embodiment of the present invention in more detail, the printed circuit board shown in fig. 3 is taken as an example for further description.
The printed circuit board shown in fig. 3 includes four ASIC chips: ASIC chip 51, ASIC chip 52, ASIC chip 53, and ASIC chip 54. The ASIC chip 51, the ASIC chip 52, and the ASIC chip 53 respectively include a function module, a Slave I2C control module, and a storage module therein, and the ASIC chip 54 is the ASIC chip shown in fig. 1.
The I2C address of the Slave I2C control module on the ASIC chip 51 is 1001000, the I2C address of the Slave I2C control module on the ASIC chip 52 is 1001001, the I2C address of the Slave I2C control module on the ASIC chip 53 is 1001011, the I2C address of the Slave I2C control module 543 on the ASIC chip 54 is 1001010, and the I2C address of the Slave I2C control module 544 on the ASIC chip 54 is 0100000. The function block 542 is controlled by the Slave I2C control block 544, and the function block 541 is controlled by the Slave I2C control block 543.
In fig. 3, two mode control lines are provided, and the mapping relationship between the high and low level values of the mode control lines and the gated ASIC chip is shown in table 1.
TABLE 1
In the printed circuit board provided by this embodiment, at least one ASIC chip integrates at least two function modules with different functions, and each function module is connected to a different Slave I2C control module, so that the Master I2C control module can access different Slave I2C control modules inside the ASIC chip through different I2C addresses, and further access different function modules through different Slave I2C control modules. Therefore, the Master I2C control module does not need to be improved, and the use cost and the complexity of an ASIC chip are reduced.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210361085.7A CN102902647B (en) | 2012-09-25 | 2012-09-25 | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210361085.7A CN102902647B (en) | 2012-09-25 | 2012-09-25 | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102902647A CN102902647A (en) | 2013-01-30 |
| CN102902647B true CN102902647B (en) | 2015-09-30 |
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| CN201210361085.7A Expired - Fee Related CN102902647B (en) | 2012-09-25 | 2012-09-25 | Be arranged on I2C from the asic chip of machine printed circuit board (PCB) and printed circuit board (PCB) |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102015214133B4 (en) * | 2015-07-27 | 2025-01-02 | Vitesco Technologies GmbH | Integrated circuit for operating on a bus and method for operating the integrated circuit |
| CN110046120B (en) * | 2019-04-12 | 2022-02-18 | 苏州浪潮智能科技有限公司 | Data processing method, device and system based on IIC protocol and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1494125A1 (en) * | 2003-07-03 | 2005-01-05 | Thomson Licensing S.A. | Method and data structure for random access via a bus connection |
| CN102023953A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Control method of system having many inter-integrated circuit (I2C) buses |
| CN102231839A (en) * | 2011-05-24 | 2011-11-02 | 深圳市掌网立体时代视讯技术有限公司 | Inter-integrated circuit (I2C) control device and method for double sensors |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1494125A1 (en) * | 2003-07-03 | 2005-01-05 | Thomson Licensing S.A. | Method and data structure for random access via a bus connection |
| CN102023953A (en) * | 2009-09-17 | 2011-04-20 | 研祥智能科技股份有限公司 | Control method of system having many inter-integrated circuit (I2C) buses |
| CN102231839A (en) * | 2011-05-24 | 2011-11-02 | 深圳市掌网立体时代视讯技术有限公司 | Inter-integrated circuit (I2C) control device and method for double sensors |
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| CN102902647A (en) | 2013-01-30 |
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Effective date of registration: 20191220 Address after: No.1, floor 3, No.319, zhanggongshan Road, Yuhui District, Bengbu City, Anhui Province Patentee after: Bengbu guijiu Intellectual Property Service Co.,Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |
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Effective date of registration: 20201021 Address after: 226000 south of Zhongxiu East Road West of Jinshan Road, high tech Zone, Nantong City, Jiangsu Province Patentee after: Nantong Tenglong Communication Technology Co.,Ltd. Address before: No.1, floor 3, No.319, zhanggongshan Road, Yuhui District, Bengbu City, Anhui Province Patentee before: Bengbu guijiu Intellectual Property Service Co.,Ltd. |
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