CN101303677B - Method, system and controller for direct memory access control - Google Patents

Abstract

The invention discloses a direct memory access control method, system and controller. The method includes: a direct memory access controller receives an interrupt signal sent by a logic module; the direct memory access controller configures the The direct memory access controller clears the interrupt source of the corresponding logic module; the direct memory access controller performs direct memory access data transmission processing. The present invention simplifies the DMA control flow and adopts DMAC and logic modules to carry out DMA control, thereby saving CPU resources, shortening the time of DMA control flow, and improving the processing speed.

Description

Method, system and controller for direct memory access control

technical field

The present invention relates to the technical field of communication, in particular to a direct memory access control method, system and controller.

Background technique

In the existing large-scale SOC (System On Chip, system on chip) chip architecture, the general DMA (Direct Memory Access, direct memory access) control method is as follows: the logic module sends an interrupt request to the interrupt controller, and the interrupt controller passes through After the interrupt arbitration process, send an interrupt signal to the CPU. After the CPU receives the interrupt signal, clear the interrupt, and then configure the DMAC (DirectMemory Access Controller, direct memory access controller). After the configuration is completed, start the DMAC, and the DMAC performs data transmission. .

It can be seen that in the existing DMA control method, the CPU, the DMAC, the interrupt controller and the logic module jointly complete the DMA control. The inventor found in the process of implementing the present invention that: in the existing method, CPU resources need to be consumed for interrupt processing, resulting in too long processing time.

Contents of the invention

The technical problem to be solved by the embodiments of the present invention is to provide a direct memory access control method, system and controller to solve the defect that the processing time of the existing DMA control method is too long.

Embodiments of the present invention are realized through the following schemes:

A direct memory access control method, comprising: a direct memory access controller receiving an interrupt signal sent by a logic module; the direct memory access controller acquiring a direct memory access corresponding to the interrupt type according to an interrupt type in the interrupt signal Accessing parameters required for data transmission, configuring the direct memory access controller according to the parameters, and clearing interrupt sources of corresponding logic modules; the direct memory access controller performs direct memory access data transmission processing.

A direct memory access control method, characterized in that it comprises: a direct memory access controller receiving an interrupt signal sent by a logic module; The corresponding direct memory access controller performs regular information on the parameters required for data transmission processing to configure the direct memory access controller, and clear the interrupt source of the corresponding logic module; the direct memory access controller performs direct memory access data transmission deal with.

A direct memory access controller, comprising: a logic interrupt processing unit, configured to receive an interrupt signal, configure the direct memory access controller according to the interrupt signal, and clear the interrupt source of the corresponding logic module; a data transmission processing unit, configured for Based on the direct memory access peripheral device request and response interface, the AHB master interface performs data transmission between the peripheral device and the memory; wherein, the logic interrupt processing unit includes:

The first receiving module is configured to receive the interrupt signal, and obtain parameters required for direct memory access data transmission corresponding to the interrupt type according to the interrupt type in the interrupt signal;

A first configuration module, configured to configure the DMA controller according to the parameters.

A direct memory access controller, characterized in that it comprises:

A logic interrupt processing unit, configured to receive an interrupt signal, configure the direct memory access controller according to the interrupt signal, and clear the interrupt source of the corresponding logic module; a data transmission processing unit, used to request and respond through the direct memory access peripheral Interface, AHB main interface, DMA control module and DMA channel module, carry out the data transmission between peripheral hardware and memory; Wherein, described logic interrupt processing unit comprises:

The second receiving module is configured to receive the interrupt signal, and obtain regularity information of parameters required by the direct memory access controller for data transmission processing according to the interrupt signal;

A second configuration module, configured to configure the DMA controller according to the rule information.

A direct memory access control system, comprising: the logic module, configured to send an interrupt signal; the direct memory access controller, configured to receive the interrupt signal, and obtain the interrupt type according to the interrupt type in the interrupt signal Parameters required for direct memory access data transmission corresponding to the interrupt type, configuring the direct memory access controller according to the parameters, clearing the interrupt source of the corresponding logic module, and performing direct memory access data transmission processing.

The embodiment of the present invention simplifies the DMA control process and adopts DMAC and logic modules to perform DMA control, thereby saving CPU resources, shortening the time of DMA control process, and increasing the processing speed.

Description of drawings

Fig. 1 is the schematic flow sheet of the method embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a DMAC in an embodiment of the present invention.

Detailed ways

The technical solutions of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 1, the direct memory access control method provided by the embodiment of the present invention includes:

Step 100, the logic module sends an interrupt signal to the DMAC.

Step 102, the DMAC receives the interrupt signal, configures the DMAC according to the interrupt signal, and clears the interrupt source of the corresponding logic module.

Step 104, the DMAC performs DMA data transmission processing.

Wherein, before the step 100, a step is also included: setting the configuration information of the DMAC. The configuration information may include: at least one interrupt type, and parameters corresponding to the interrupt type required to start a DMA data transfer. The parameters required to start a DMA data transfer may include: start address, destination address, channel configuration register, channel control register, and interrupt source clearing information. Each interrupt type corresponds to a start address, destination address, channel configuration parameters, channel control parameters and interrupt source clearing information. For example, if there are 5 types of interrupts, there are 5 start addresses, destination addresses, channel configuration registers, channel control registers, and interrupt source clearing information. Each interrupt type corresponds to a start address, destination address, and channel configuration. Parameters, channel control parameters and interrupt source clearing information. Alternatively, the configuration information includes regularity information of parameters required by the DMAC for data transmission processing, so that the DMAC can configure the DMAC according to the regularity information.

The interrupt signal includes the interrupt type. After the DMAC receives the interrupt signal, according to the interrupt type in the interrupt signal, the parameters required for the DMA data transmission corresponding to the interrupt type are obtained, and the DMAC is configured according to the parameters; or the DMAC can be configured according to the DMAC. Regular information of the parameters required for data transfer processing to configure the DMAC. Of course, the interrupt signal may also include other information, such as the number of interrupts. The DMAC can obtain the parameters through its AHB slave interface (AHB slave) (Advanced High-performance Bus slave, advanced high-performance bus slave interface).

Wherein, according to the parameter configuration DMAC required for the DMA data transmission corresponding to the interrupt type, it can be realized in the following manner: the parameters required for the DMA data transmission corresponding to the interrupt type are written into the DMA control module and the DMA channel module, so that capable of the DMA control module and the DMA channel module.

Clearing the corresponding interrupt source of the logic module can be implemented in the following way: send a read/write request to the AHB master interface (AHB master) according to the interrupt source clearing information, and clear the interrupt source of the corresponding logic module.

DMAC data transmission processing can be: DMAC through DMA peripheral request and response interface (DMA req and rsp interface), AHB master, DMA control module and DMA channel module, data transmission between peripherals and memory (memory) . The DMA peripheral request and response interface 221 receives the data transmission request of the peripheral, the AHB master 222 obtains the control right of the AHB bus, and the DMA control module 223 controls the DMA channel module 224 to perform data transmission between the peripheral and the memory. Wherein, the DMA channel module 224 may include multiple DMA data transmission channels, and when the channel receiving the data transmission request has the highest priority among all the channels that are about to start DMA transmission, the channel starts data transmission.

As shown in Figure 2, the direct memory access control system provided by the embodiment of the present invention includes: a logic module 1 and a DMAC 2;

Logic module 1, used to send interrupt signal to DMAC 2.

DMAC 2 is used to receive an interrupt signal, configure the DMAC according to the interrupt signal, and clear the interrupt source of the corresponding logic module 1 to perform DMA data transmission processing.

Wherein, DMAC 2 can comprise: logical interrupt processing unit 21 and data transmission processing unit 22; Logical interrupt processing unit 21 is used for receiving interrupt signal, configures this DMAC according to this interrupt signal, and clears the interrupt source of corresponding logic module 1; Data The transmission processing unit 22 is used for performing data transmission between the peripheral hardware and the memory through the DMA peripheral hardware request and response interface 221, the AHB master 222, the DMA control module 223 and the DMA channel module 224. The DMA peripheral request and response interface 221 receives the data transmission request of the peripheral, the AHB master 222 obtains the control right of the AHB bus, and the DMA control module 223 controls the DMA channel module 224 to perform data transmission between the peripheral and the memory. Wherein, the DMA channel module 224 may include multiple DMA data transmission channels, and when the channel receiving the data transmission request has the highest priority among all the channels that are about to start DMA transmission, the channel starts data transmission.

The logical interrupt processing unit 21 may include: a first receiving module 211, configured to receive an interrupt signal, and obtain parameters required for DMA data transmission corresponding to the interrupt type according to the interrupt type in the interrupt signal; a first configuration module 212, configured to configure the DMAC 2 according to the parameters. The parameters required for DMA data transmission may include: start address, destination address, channel configuration register, channel control register, and interrupt source clearing information. Each interrupt type corresponds to a start address, destination address, channel configuration parameters, channel control parameters and interrupt source clearing information.

Or, the logical interrupt processing unit may include: a second receiving module, configured to receive an interrupt signal, and obtain the regular information of the parameters required by the DMAC for data transmission processing according to the interrupt signal; a second configuration module, configured to Configure DMACs.

Configuration information such as parameters required by the DMAC for data transmission processing and interrupt types corresponding to the parameters, or regular information of parameters required by the DMAC for data transmission processing may be preset. Wherein, the configuration information may also include other information such as the number of interrupts. The DMAC can obtain the parameter or regularity information of the parameter through its AHB slave 23.

The first configuration module 212 can be a first configuration submodule, which is used to write the parameters required for the DMA data transmission corresponding to the interrupt type into the DMA control module 223 and the DMA channel module 224, enabling the DMA control module 223 and DMA channel module 224.

The logical interrupt processing unit 21 also includes an interrupt clearing module 213, which is used to send a read/write request to the AHB master 222 according to the interrupt source clearing information, and clear the interrupt source of the corresponding logic module.

The embodiment of the present invention simplifies the DMA control process and adopts DMAC and logic modules to perform DMA control, thereby saving CPU resources, shortening the time of DMA control process, and increasing the processing speed.

The above is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present invention can easily think of changes or Replacement should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (15)

1. a direct memory access control method is characterized in that, comprising:

The look-at-me that direct memory access controller receive logic module sends;

Described direct memory access controller is according to the interrupt type in the described look-at-me, obtain the pairing direct memory visit data transmission of described interrupt type parameters needed, and according to the described direct memory access controller of described parameter configuration, and the interrupt source of removing respective logic module;

Described direct memory access controller carries out the transmission process of direct memory visit data.

2. method according to claim 1 is characterized in that, also comprises:

The configuration information of direct memory access controller is set, and described configuration information comprises: at least a interrupt type, and a direct memory visit data transmission of the startup of described interrupt type correspondence parameters needed.

3. method according to claim 2 is characterized in that, described parameter comprises: start address, destination address, channel arrangement register, channel control register and interrupt source zero clearing information.

4. method according to claim 1 is characterized in that, described step according to parameter configuration direct memory access controller comprises:

The pairing direct memory visit data transmission of described interrupt type parameters needed is write direct memory access control module and direct memory access path module, enable described DMA control module and described DMA channel module.

5. method according to claim 3 is characterized in that, the step of the interrupt source of described removing respective logic module comprises:

Send read according to described interrupt source zero clearing information to advanced person's high performance bus AHB main interface, remove the interrupt source of respective logic module.

6. method according to claim 1 is characterized in that, the step that described direct memory access controller carries out the transmission process of direct memory visit data comprises:

The direct memory access controller is by direct memory visit peripheral hardware request and reply interface, AHB main interface, DMA control module and DMA channel module, carries out the data transmission between peripheral hardware and the storer.

7. a direct memory access control method is characterized in that, comprising:

The look-at-me that direct memory access controller receive logic module sends;

Described direct memory access controller is according to the interrupt type in the described look-at-me, obtain the rule information that the pairing direct memory access controller of described interrupt type carries out the data transmission and processing parameters needed and dispose described direct memory access controller, and remove the interrupt source of respective logic module;

Described direct memory access controller carries out the transmission process of direct memory visit data.

8. method according to claim 7 is characterized in that, also comprises:

The configuration information of direct memory access controller is set, and described configuration information comprises: DMAC carries out the rule information of data transmission and processing parameters needed.

9. a direct memory access controller is characterized in that, comprising:

Logic Interrupt Process unit is used to receive look-at-me, disposes described direct memory access controller according to described look-at-me, and removes the interrupt source of respective logic module;

The data transmission and processing unit is used for visiting the peripheral hardware request and replying interface, AHB main interface, DMA control module and DMA channel module by direct memory, carries out the data transmission between peripheral hardware and the storer; Wherein, described logic Interrupt Process unit comprises:

First receiver module is used to receive described look-at-me, and according to the interrupt type in the described look-at-me, obtains the pairing direct memory visit data transmission of described interrupt type parameters needed;

First configuration module is used for according to the described direct memory access controller of described parameter configuration.

10. controller according to claim 9 is characterized in that, described parameter comprises: start address, destination address, channel arrangement register, channel control register and interrupt source zero clearing information.

11. controller according to claim 9, it is characterized in that, described first configuration module is the first configuration submodule, be used for the pairing direct memory visit data transmission of described interrupt type parameters needed is write direct memory access control module and direct memory access path module, enable described DMA control module and described DMA channel module.

12. controller according to claim 9 is characterized in that, described logic Interrupt Process unit also comprises the interrupt clear module, is used for sending read according to described interrupt source zero clearing information to the AHB main interface, removes the interrupt source of respective logic module.

13. a direct memory access controller is characterized in that, comprising:

Logic Interrupt Process unit is used to receive look-at-me, disposes described direct memory access controller according to described look-at-me, and removes the interrupt source of respective logic module;

The data transmission and processing unit is used for visiting the peripheral hardware request and replying interface, AHB main interface, DMA control module and DMA channel module by direct memory, carries out the data transmission between peripheral hardware and the storer; Wherein, described logic Interrupt Process unit comprises:

Second receiver module is used to receive described look-at-me, and obtains the rule information that the direct memory access controller carries out the data transmission and processing parameters needed according to described look-at-me;

Second configuration module is used for according to the described direct memory access controller of described rule information configuration.

14. controller according to claim 13 is characterized in that, described logic Interrupt Process unit also comprises the interrupt clear module, is used for sending read according to described interrupt source zero clearing information to the AHB main interface, removes the interrupt source of respective logic module.

15. a direct memory access control system is characterized in that, comprises direct memory access controller and logic module;

Described logic module is used to send look-at-me;

Described direct memory access controller, be used to receive described look-at-me, according to the interrupt type in the described look-at-me, obtain the pairing direct memory visit data transmission of described interrupt type parameters needed, and according to the described direct memory access controller of described parameter configuration, and the interrupt source of removing respective logic module, carry out the transmission process of direct memory visit data.

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