KR980005536A - METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR - Google Patents

METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR Download PDF

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KR980005536A
KR980005536A KR1019960024495A KR19960024495A KR980005536A KR 980005536 A KR980005536 A KR 980005536A KR 1019960024495 A KR1019960024495 A KR 1019960024495A KR 19960024495 A KR19960024495 A KR 19960024495A KR 980005536 A KR980005536 A KR 980005536A
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South Korea
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forming
tungsten
film
oxide
contact hole
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KR1019960024495A
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KR100197535B1 (en
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고창진
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김주용
현대전자산업 주식회사
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Assigned to 매그나칩 반도체 유한회사 reassignment 매그나칩 반도체 유한회사 권리의 전부이전등록 Assignors: 주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/277—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers

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  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 제조 방법에 있어서, CMP공정을 이용한 폴리싱 시 텅스텐 플러그 상부에 형성되는 텅스텐 산화막을 제거함으로써 소자의 신뢰성을 향상시킬 수 잇는 반도체 소자의 금속 배선 형성방법에 관한 것으로, 기본적인 회로를 구비한 반도체 기판 상부에 절연막을 형성하는 단계; 반도체 기판 표면이 일부분이 노출되도록 절연막의 예정된 영역에 콘택홀을 형성하는 단계; 결과물 상부에 보호 금속막을 형성하는 단계; 보호 금속막이 형성된 콘택홀에 매립하도록 콘택홀의 하부 및 측부와 절연막 상부에 텅스텐을 증착하는 단계; 텅스텐을 슬러리를 이용하여 폴리싱(polishing) 공정을 진행함으로써, 텅스텐 플러그를 형성하는 단계; 폴리싱 공정 후 텅세텐 플러그 상부에 형성되는 소정의 산화물을 제거하는 단계; 및, 결과물 상부에 전도막을 형성하는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method of forming a metal wiring of a semiconductor device capable of improving the reliability of a device by removing a tungsten oxide film formed on a tungsten plug at the time of polishing using a CMP process, Forming an insulating film on the semiconductor substrate; Forming a contact hole in a predetermined region of the insulating film so that a part of the surface of the semiconductor substrate is exposed; Forming a protective metal film on the resultant product; Depositing tungsten on the lower and side portions of the contact hole and the upper portion of the insulating film so as to be buried in the contact hole in which the protective metal film is formed; Forming a tungsten plug by subjecting tungsten to a polishing process using a slurry; Removing a predetermined oxide formed on the tungsten plug after the polishing process; And forming a conductive film on the resultant product.

Description

반도체 소자의 금속 배선 형성방법METHOD FOR FORMING METAL WIRING OF SEMICONDUCTOR

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2a도 내지 제2d도는 본 발명의 일 실시예에 따른 반도체 소자의 금속 배선 형성방법을 나타낸 공정 단면도.FIGS. 2a to 2d are process sectional views showing a method of forming a metal wiring of a semiconductor device according to an embodiment of the present invention.

Claims (6)

기본적인 회로를 구비한 반도체 기판 상부에 절연막을 형성하는 단계; 반도체 기판 표면이 일부분이 노출되도록 절연막의 예정된 영역에 콘택홀을 형성하는 단계; 상기 결과물 상부에 보호 금속막을 형성하는 단계; 상기 보호 금속막이 형성된 콘택홀에 매립하도록 콘택홀의 하부 및 측부와 절연막 상부에 텅스텐을 증착하는 단계; 텅스텐을 슬러리를 이용하여 폴리싱(polishing) 공정을 진행함으로써, 상기 텅스텐 플러그를 형성하는 단계; 폴리싱 공정 후 텅세텐 플러그 상부에 형성되는 소정의 산화물을 제거하는 단계; 및, 상기 결과물 상부에 전도막을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.Forming an insulating film on a semiconductor substrate having a basic circuit; Forming a contact hole in a predetermined region of the insulating film so that a part of the surface of the semiconductor substrate is exposed; Forming a protective metal film on the resultant product; Depositing tungsten on the lower and side portions of the contact hole and the upper portion of the insulating film so as to be buried in the contact hole in which the protective metal film is formed; Forming a tungsten plug by subjecting tungsten to a polishing process using a slurry; Removing a predetermined oxide formed on the tungsten plug after the polishing process; And forming a conductive film on an upper surface of the resultant structure. 제1항에 있어서, 상기 폴리싱 공정은 CMP(Chemical - Mechanical - Polishing) 기술로 진행하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method of claim 1, wherein the polishing process is performed by a CMP (Chemical-Mechanical-Polishing) technique. 제1항에 있어서, 상기 텅스텐 플러그 상부에 형성되는 상기 산화물은 텅스텐 산화막인 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method according to claim 1, wherein the oxide formed on the tungsten plug is a tungsten oxide film. 제1항 또는 제3항에 있어서, 상기 산화물의 제거 공정은 스퍼터링 장비에서 수소 개스를 유입하여 상기 산화물을 환원 반응 시키는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.4. The method according to claim 1 or 3, wherein the oxide removing step is performed by introducing hydrogen gas into the sputtering equipment to reduce the oxide. 제1항에 있어서, 상기 전도막은 상기 산화물을 제거한 챔버와 다른 챔버에서 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method according to claim 1, wherein the conductive film is formed in a chamber different from the chamber from which the oxide is removed. 제1항에 있어서, 상기 전도막은 알루미늄 합금으로 이루어진 것을 특징으로 하는 반도체 소자의 금속 배선 형성방법.The method according to claim 1, wherein the conductive film is made of an aluminum alloy. ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960024495A 1996-06-27 1996-06-27 Metal wiring formation method of semiconductor device Expired - Lifetime KR100197535B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960024495A KR100197535B1 (en) 1996-06-27 1996-06-27 Metal wiring formation method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960024495A KR100197535B1 (en) 1996-06-27 1996-06-27 Metal wiring formation method of semiconductor device

Publications (2)

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KR980005536A true KR980005536A (en) 1998-03-30
KR100197535B1 KR100197535B1 (en) 1999-06-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100514536B1 (en) * 1999-04-13 2005-09-13 가부시키가이샤 히타치세이사쿠쇼 A method of polishing

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030052828A (en) * 2001-12-21 2003-06-27 동부전자 주식회사 Fabricating method of metal wire in semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100514536B1 (en) * 1999-04-13 2005-09-13 가부시키가이샤 히타치세이사쿠쇼 A method of polishing

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