KR970072311A - Method of planarizing a semiconductor device - Google Patents

Method of planarizing a semiconductor device Download PDF

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Publication number
KR970072311A
KR970072311A KR1019960009705A KR19960009705A KR970072311A KR 970072311 A KR970072311 A KR 970072311A KR 1019960009705 A KR1019960009705 A KR 1019960009705A KR 19960009705 A KR19960009705 A KR 19960009705A KR 970072311 A KR970072311 A KR 970072311A
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KR
South Korea
Prior art keywords
insulating film
interlayer insulating
semiconductor device
photoresist
planarizing
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Application number
KR1019960009705A
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Korean (ko)
Inventor
신유철
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019960009705A priority Critical patent/KR970072311A/en
Publication of KR970072311A publication Critical patent/KR970072311A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/092—Manufacture or treatment of dielectric parts thereof by smoothing the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching
    • H10P95/066—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask

Landscapes

  • Mechanical Treatment Of Semiconductor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 평탄화 방법에 관한 것으로, 본 발명에 따른 반도체 장치의 평탄화 방법에서는 반도체 장치에 필요한 패턴들에 의해 단차가 형성된 웨이퍼 상에 충간 절연막을 형성하는 단계와, 상기 층간절연막 상에 상기 층간 절연막을 완전히 덮는 포토레지스트층을 형성하는 단계와, 상기 층간 절연막의 오목한 단차 부분 내에서 상기 층간 절연막의 볼록한 단차 부분보다 낮은 높이를 갖는 포토레지스트 잔류층이 잔존하도록 소정의 에칭 종The present invention relates to a method for planarizing a semiconductor device, and a method for planarizing a semiconductor device according to the present invention includes the steps of: forming an interlayer insulating film on a wafer having steps formed by patterns necessary for a semiconductor device; Forming a photoresist layer that completely covers the interlayer insulating film; forming a photoresist layer having a height lower than a convex stepped portion of the interlayer insulating film in a concave stepped portion of the interlayer insulating film,

말점에 따라 상기 포토레지스트층을 에치백하는 단계와, 상기 포토레지스트 잔류층을 에칭마스크로 하여 상기 층간 절연막의 볼록한 단차 부분을 소정의 두께 만큼 에치백하는 단계와, 상기 포토레지스트 잔류층을 제거하는 단계와, 상기 결과물을 CMP(Chemecal Mechanical Polishing) 공정에 의해 평탄화하는 단계를 포함한다. 본 발명에 의하면, CMP 공정의 전처리로서 비교적 단순한 공정으로 단차를 보상하여 반도체 장치의 평탄화를 이룰 수 있다.Comprising the steps of: etching back the photoresist layer according to an end point; etching back the convex stepped portion of the interlayer insulating film to a predetermined thickness using the photoresist residue layer as an etching mask; and removing the photoresist residue layer And planarizing the resultant by a chemical mechanical polishing (CMP) process. According to the present invention, as a pretreatment of the CMP process, the semiconductor device can be planarized by compensating the step difference by a relatively simple process.

Description

반도체 장치의 평탄화 방법Method of planarizing a semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제2도 내지 제5도는 본 발명에 따른 반도체 장치의 평탄화 방법을 설명하기 위하여 각 단계별로 순차적으로 도시한 반도체 장치의 단면도이다.FIGS. 2 to 5 are cross-sectional views sequentially illustrating semiconductor devices in order to explain a planarization method of the semiconductor device according to the present invention.

Claims (3)

반도체 장치에 필요한 패턴들에 의해 단차가 형성된 웨이퍼 상에 층간 절연막을 형성하는 단계와, 상기 층간절연막 상에 상기 층간 절연막을 완전히 덮는 포토레지스트층을 형성하는 단계와, 상기 층간 절연막의 오목한 단차 부분 내에서 상기 층간 절연막의 볼록한 단차 부분보다 낮은 높이를 갖는 포토레지스트 잔류층이 잔존하도록 소정의 에칭 종말점에 따라 상기 포토레지스트층을 에치백하는 단계와, 상기 포토레지스트 잔류층을 에칭마스크로 하여 상기 층간 절연막의 볼록한 단차 부분을 소정의 두께 만큼 에치백하는 단계와, 상기 포토레지스트 잔류층을 제거하는 단계와, 상기 결과물을 CMP(Chemecal Mechanical Polishing) 공정에 의해 평탄화하는단계를 포함하는 것을 특징으로 하는 반도체 장치의 평탄화 방법.A method for manufacturing a semiconductor device, comprising: forming an interlayer insulating film on a wafer having steps formed by patterns necessary for a semiconductor device; forming a photoresist layer completely covering the interlayer insulating film on the interlayer insulating film; Etching the photoresist layer according to a predetermined etching end point so that a photoresist residual layer having a height lower than a convex step portion of the interlayer insulating film remains in the interlayer insulating film, And removing the photoresist residue layer; and planarizing the resultant by a chemical mechanical polishing (CMP) process. The semiconductor device according to claim 1, / RTI > 제1항에 있어서, 상기 포토레지스트층을 에치백하는 단계의 후속 공정으로서 상기 포토레지스트 잔류층을 베이킹하는 단계를 더 포함하는 것을 특징으로 하는 반도체 장치의 평탄화 방법.The method according to claim 1, further comprising baking the photoresist residue layer as a subsequent step of etching back the photoresist layer. 제1항에 있어서, 상기 층간 절연막으로서 SiO2계의 물질을 사용하는 것을 특징으로 하는 반도체 장치의 평탄화 방법.The flattening method of a semiconductor device according to claim 1, wherein an SiO 2 -based material is used as said interlayer insulating film. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960009705A 1996-04-01 1996-04-01 Method of planarizing a semiconductor device Withdrawn KR970072311A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960009705A KR970072311A (en) 1996-04-01 1996-04-01 Method of planarizing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960009705A KR970072311A (en) 1996-04-01 1996-04-01 Method of planarizing a semiconductor device

Publications (1)

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KR970072311A true KR970072311A (en) 1997-11-07

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311495B1 (en) * 1999-07-05 2001-10-18 김영환 Method for flating insulating layer of semiconductor device
KR100363093B1 (en) * 2000-07-28 2002-12-05 삼성전자 주식회사 Method of planarizing interlevel insulating layer in semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100311495B1 (en) * 1999-07-05 2001-10-18 김영환 Method for flating insulating layer of semiconductor device
KR100363093B1 (en) * 2000-07-28 2002-12-05 삼성전자 주식회사 Method of planarizing interlevel insulating layer in semiconductor device
US6518157B2 (en) 2000-07-28 2003-02-11 Samsung Electronics Co., Ltd. Methods of planarizing insulating layers on regions having different etching rates

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