KR920007503B1 - Binary Image Information Processing Equipment - Google Patents

Abstract

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Description

Binary Image Information Processing Equipment

1 is a schematic configuration diagram of a system to which a binary image information processing apparatus is applied.

2 is a block diagram of a conventional binary image information processing apparatus.

3 is a block diagram of the present invention.

4 illustrates one embodiment of a system bus interface circuit.

5 is an exemplary allocation diagram of a memory and an input / output device viewed from the CPU side.

6 is a diagram illustrating the configuration of a second bus control logic circuit according to one embodiment.

7 is an operation timing diagram of FIG.

8 is an image bus access timing diagram.

* Explanation of symbols for main parts of the drawings

1: CPU 2: code and decoder

3: code storage memory section 4 image storage memory section

5: internal bus 6: ROM

7: RAM 8: Image input / output controller

9: System bus 10: System bus interface circuit

11: common memory 12: bus

13: Imagebus 14: Imagebus Interface Circuit

15: first bus control logic circuit 16: second bus control logic circuit

The present invention relates to a binary image information processing apparatus.

In order to realize a device such as a Class 2 or Class 3 device of G4 facsimile that has become the international communication standard, or a teletex with mixed mode operation capability, a binary image is inputted and the G4 facsimile coding method (Modified MR method: According to CCITT T.6 “Facsimile Code, Method and Coding Control Function in G4 Facsimile Device”, the function of compressing or extending binary image information and printing should be designed efficiently.

In addition, a function of displaying an input binary image on a screen while maintaining an appropriate resolution according to a user function is required.

However, in order to satisfy this requirement, the amount of information about one megabyte of ISO A4 document (210 × 297mm) with a resolution of 300 dpi (dot per inch) used as the current standard is large. Therefore, a binary image information processing apparatus for realizing system performance in real time is required.

The conventional binary image information processing apparatus developed in response to this demand is shown in FIG. 2, and will be described below with reference to FIG.

The conventional binary image information processing apparatus is composed of a CPU (1), a code and decoder (2), a code storage memory section (3), and an image storage memory section (4), each of which is connected to the system bus 9 in its main configuration. When the binary information is transmitted and received, each of the above is connected to another processor of FIG. 1 through the system bus 9, that is, a system controller or a graphic display device, so that the system bus 9 is overloaded. Many restrictions are imposed on real-time processing such as deterioration of the performance of the communication control apparatus illustrated in FIG.

That is, in the above structure, the use of the image of the graphics processing apparatus (FIG. 1) generally occupies most of the system buses, and there is a disadvantage in that immediate processing such as transmission and reception is delayed.

An object of the present invention is to solve the above problems, and to solve the above problems, that is, an apparatus for realizing binary image information processing in real time. An image storage memory section for storing the input binary image and a code storage memory for storing the coded code are separately configured with a local CPU (corresponding to the system cpu) to be managed. It is possible to share additional binary images, so that additional processing functions of various binary images are possible, and the input / output of images that take a relatively long time, which is relatively input / output time, is managed by the local CPU, and the system controller simultaneously adds systems such as communication. Function, and a large amount of image information of about 1 megabyte does not pass through the system bus. In addition, by displaying and processing a graphic through an image bus, a device capable of dramatically improving system efficiency in terms of user response time, maximum network transmission speed, and binary image input / output simultaneous processing is constructed.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 3.

3 is a block diagram showing the configuration of the present invention, in which 1 is a CPU, 2 is a code and decoding device, 3 is a code storage memory unit, 4 is an image storage memory unit, 5 is an internal bus, 6 is ROM, 7 is RAM, 8 is image input and output control, 9 is system bus, 10 is system bus interface circuit, 11 is common memory part, 12 is bus, 13 is image bus, 14 Denotes an image bus interface circuit, 15 denotes a first bus control logic circuit, and 16 denotes a second bus control logic circuit.

4 is a diagram illustrating an embodiment of a system bus interface circuit, FIG. 5 is a diagram illustrating allocation of a memory and an input / output device as viewed from the CPU side, FIG. 6 is a diagram showing an embodiment of the configuration of a second bus control logic circuit, and FIG. 6 is an operation timing diagram and FIG. 8 is an image bus access timing diagram.

The image input / output control unit 8, the ROM 6, and the RAM 7 are connected to the CPU 1 via an internal bus 5, and the CPU 1 is connected to the common memory unit 11 by the bus 12. ), The first bus control logic circuit 15 and the second bus control logic circuit 16 are connected.

In the embodiment of the present invention, the CPU 1 was implemented using 6418ORL of Hida-ji, Japan. The ROM 6 used two 27C128s, and the RAM 7 used two 62256SRAMs.

The common memory unit 11 is implemented using two 6264SRAMs in the embodiment, and the address and data signal lines are connected to the system bus interface circuit 10.

The first bus control logic circuit 15 is connected to the system bus interface circuit 10, the code storage memory section 3, the code and decoder 2, and the CPU 1 accesses the code storage memory 3; ), The system bus interface circuit 10, and the address and data signals of the code and decoder 2 are composed of a buffer and an access signal and wait (WATT) signal combination circuit using 74LS244,245.

The second bus control logic circuit 16 is connected to the code and decoder 2, the image storage memory section 4, and the image bus interface circuit 14, and the system bus interface circuit 10 is a system bus 9 ), And the image bus interface circuit 14 is connected to the image bus 13.

The system bus 9 is implemented by using the multibus I (IEEE 796 bus), and is a dedicated image bus designed for image transmission between the high resolution graphic processing device and the device to improve user response time. It is characterized by receiving expansion address signals A14 to A17 other than some system buses, and allowing the graphics processing apparatus and image information to be accessed at high speed by the timing of FIG. 8 in an asynchronous manner.

As described above, the image storage memory unit 4 and the code storage memory unit 3 separate separate buses, and the code and decoder 2 is provided with the first and second bus control logic circuits 15 and 16. Through both the memory unit (3, 4) can be used. In addition, the code stored in the code storage memory section 3 is simultaneously written and read by the CPU 1, the code and decoder 2, and the system controller (see FIG. 1) through the first bus control logic circuit 15. The image information stored in the image storage memory unit 4 may be simultaneously controlled by the CPU 1, the code and decoding device 2, and the graphics processing device (see FIG. 1) through the second bus control logic circuit 16. FIG. It is configured to write and read.

Here, in the embodiment, the code storage memory unit 2 is composed of 128K bytes using four 62256 SRAMs, and the allocation diagrams of the memory and the input / output device viewed from the CPU 1 side are shown in FIG.

On the other hand, binary image information, which is input from an image scanner which is an image input device of the input / output control unit 8, is stored or used as a memory for storing binary image information decoded through a code and a decoding device 2 or printing the same. The image storage memory unit 4 modularized 24 SCRs 62256 and composed of 768K bytes.

The host in FIG. 1 using the system bus interface can pass a parameter indicating image information processing or access the coded code via the system bus.

The memory of the binary image information processing system is allocated to the address 900000-92FFFF (Hex) of the host 80286 of the embodiment, and the first 64K Bytes is the common memory 11 for the buffer for printing parameter and character or graphic information, and the following 128KBytes Is assigned to the code storage memory 3.

The host sets the resolution, input range, and other options as parameters in the input of the image, the resolution, printing range, code type and options as parameters in the output, and the code and decoding range and memory location in the encoding and decoding. In the present invention, after the recognition signal ACK is transmitted, the end of the process is notified by using an interrupt.

The CPU 1 is a multifunction processor that can access more than 1M Bytes of memory, and has a built-in peripheral device, and uses Hitachi HD6418O-R1 in that it is easy to interface with the system bus 9. In this case, in order to satisfy the required function, three processors (host, CPU, code, and decoder 2) are used for the code storage memory unit 3, and three processors (CPU) are used for the image storage memory unit 4. Since it must be accessible by the Graphic Processor, Code, and Decoder), the bus control circuit is constructed by using the buffer to separate each bus and using the state information of the processor to be accessed.

At this time, the code storage memory side of the code and decoder 2 can easily operate the bus because the code and decoder 2 can operate as a master or slave, but the image storage memory side can be controlled. Since there is no state information, the DREADY signal is input by using the address latch enable (ALE), write (DWR), read (DRD) signals of the sign and decoder 2 and the access state information of the remaining processors. The two bus control logic circuit 16 was constructed. An embodiment of this configuration is shown in FIG. 6 and an operation timing diagram in FIG.

The memory, on the other hand, uses mode 1MBytes and can be accessed using the built-in memory management unit (MMU) inside the CPU.

In order to realize the coding and decoding functions according to CCITT T.6, the code and decoder 2 used the CEP (Am7971) chip of AMD of the United States incorporating MH, MR, and MMR functions as firmware. .

The CEP can simultaneously encode and decode binary image information at a speed of 12 Mbps, has an error detection function of an encoded code, and has two processors having two independent buses therein to access 16 MBytes of memory. .

Operation is achieved by controlling 46 registers that can interface with the CPU 1, and optionally several non-standard coding schemes can be selected. Each of the 46 registers is capable of controlling the format of the code, the range of encoding or decoding, the memory address, and the state of the CEP. The state information registers indicate the state of the CEP, the encoding and decoding of information, error recovery, and reactivation. It can be classified into a control register indicating a code, a parameter register controlling a code format, a margin register controlling a size of a document to be encoded and decoded, a mode register specifying a specific mode, and a size register specifying a memory operating range and size. have.

The second bus control logic circuit 16 illustrated in FIG. 6 is designed to access the image storage memory section 4 of the code and decoder 2, and MN8617 of Mazda, Japan, which is an embodiment of the graphic processor. And the access information of the CPU 1 and the ALE, DWR and DRD signals, which are the status information of the CEP, control the DREADY input of the CEP so that the three processors can access the image buffer without error of data.

When a graphics processor attempts to display binary image information on a high resolution display (CRT), or perform arbitrary manipulations for editing by the user, a large amount of information, usually from hundreds of bytes to 1M bytes, is degraded. The exchange of binary image information with the graphics processor is via an independent image bus.

The physical connection uses a uniquely defined 60-pin terminal, and the access timing is designed as shown in Figure 8 considering the characteristics of the graphics processor MN8617.

Since the MN8617, which is an embodiment of the graphics processor, operates asynchronously, its bus adjustment is controlled using an ACK signal for the access request, and the valid data timing is informed using a DACK signal after 300 nscc after giving an ACK.

The image scanner, which is an image input device for inputting binary images, uses IS-300M2 of Japan's System Quality, which has a scanning range of 5 × 5mm and 216 × 297mm at maximum. have. In addition, ISO A4 documents can be entered within 14 seconds of binary image information of 300 dpi, and gray information can be entered within half seconds of halftone. In addition, resolutions of 180, 200, 240 and 300 dpi can be selected and the software can be adjusted for reading density. Optional features include mirror image input, status information output and 16 gray level inputs.

The interface with the scanner is a general 8-bit bidirectional Centronics. In order to instruct the scanner to operate, the control bit is first set to operate the scanner as a slave, and then the command is sent and the image input instruction is followed. The scanner acts as a master and passes the information obtained. At this time, in order to reduce the load of the CPU 1, an interrupt is generated and processed from the strobe signal input only when the information input by the scanner is valid.

The printer, which is an image output device in the image input / output control unit 8, printed character and graphic information and binary image information using a QLBP2000 having a Centronix interface. The image output control device has one latch and two DF / It was simply constructed using only F. That is, first, the data is latched to the printer input / output port allocated in FIG. 5, and then a strobe signal is applied in software to terminate the execution cycle by receiving an ACK signal from the printer connected to the interrupt input of the CPU.

Hereinafter, the operation and effects of the present invention configured as described above will be described.

In a system in which a binary image is input and displayed on a screen as shown in FIG. 1, or a function of encoding (compressing) or decoding (extending) a binary image by a G4 facsimile encoding method and printing through an output device is required. By configuring the device as follows, it has the following effects.

First, by placing an image bus, a large amount of binary image information can be moved quickly according to the demand of the graphics processing device without any load on the system bus, and the performance improvement of the entire system is superior, and binary image processing (editing, enlargement, reduction) User processing speed, etc.) is enhanced. In particular, when the system bus load increases during the transmission and reception of information, the improvement in performance is remarkable compared to the conventional method (figure 2).

Second, by providing a local CPU, the configuration as in the prior art is limited by graphic screen indicators during noise reduction or pre-processing (edge sharpening, filtering, etc.) of binary images or during transmission, reception, or encoding operations. Regardless of this, it can be processed.

Third, by separating the bus using the image storage memory and the code storage memory and adding the bus control logic circuit, when the system controller uses the code, the image processing device can use the image regardless of the image bus. As described above, a plurality of processors can be used by sharing the timing of the code and the image storage memory.

Therefore, the use of the image of the graphics processing device occupies most of the system bus, eliminating the disadvantages of the same configuration as the conventional device, which is difficult to process immediately, such as transmission and reception. Therefore, in the case of the G4 facsimile class 3 device, And decoding and display on a graphic screen.

Fourth, the local CPU can store images that require a lot of input / output time by instructing the commands agreed to the common memory through the system bus. Receive and decrypt can be done at the same time.

Fifth, the local CPU and the code, the decoder, and the memory (for the code storage and the image storage) are controlled by the bus through two bus control logic circuits as shown in FIG. Since it is shared, the hardware configuration is more concise than the configuration of the conventional device and the device is easy to integrate.

Claims (1)

The image input / output control unit 8, ROM 6 and RAM 7 are connected to the CPU 1 via an internal bus 5, and the CPU 1 is connected to the common memory means 1 by the bus 12. Is connected to the first bus control logic means 15, the second bus control logic means 16, and the common memory means 1 is connected to the system bus interface means 10, and the first bus control logic means. (15) is connected to the system bus interface means (10), code storage memory means (3), code and decoding means (2), and the second bus control logic means (16) is used for the code and decoding means (2). ), The image storage memory means 4, the image bus interface means 14, the system bus interface means 10 is connected to the system bus (9), the image bus interface means 14 is an image bus Is configured to be connected to 13; The image storage memory means 4 and the code storage memory means 3 are separated into separate buses, and the code and decoding means 2 are connected via the first and second bus control logic means 15, 16. The code storage and image storage means (3, 4) can be used, and the code stored in the code storage memory means (3) is the CPU (1), the code and decoding device (2) and the system controller One bus control logic means 15 allows simultaneous writing and reading, and image information stored in the image storage memory 4 is controlled by the CPU 1, the code and decoding device 2, and the graphics processing device. Binary image information processing device characterized in that the writing and reading through the logic means at the same time.

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