KR102902640B1 - Semiconductor devices and methods of manufacturing semiconductor devices - Google Patents

Abstract

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of forming a first sacrificial layer and a first semiconductor layer on a substrate having first and second regions, removing the first semiconductor layer in the second region so that the first sacrificial layer remains, forming a second sacrificial layer and a second semiconductor layer on the first semiconductor layer in the first region and the first sacrificial layer in the second region, forming sacrificial gate structures extending in one direction on the second semiconductor layer, and removing the sacrificial gate structures and the first and second sacrificial layers and forming gate structures.

Description

Semiconductor devices and methods of manufacturing semiconductor devices {SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES}

The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

As demands for high performance, high speed, and/or multifunctionality in semiconductor devices increase, the integration of semiconductor devices is also increasing. To meet this trend of high integration, the fabrication of micro-patterned semiconductor devices requires the implementation of patterns with minute widths or minute spacings. Furthermore, efforts are being made to develop semiconductor devices with three-dimensional channels to overcome the limitations in operating characteristics associated with the shrinking size of planar MOSFETs (metal oxide semiconductor FETs).

One of the technical tasks to be achieved by the present invention is to provide a semiconductor device with improved electrical characteristics and mass productivity and a method for manufacturing the same.

A method for manufacturing a semiconductor device according to exemplary embodiments comprises the steps of: forming a first sacrificial layer and a first semiconductor layer on a substrate having first to third regions; removing the first semiconductor layer in the second and third regions; forming a second sacrificial layer and a second semiconductor layer on the substrate; removing the second semiconductor layer in the second and third regions; forming a third sacrificial layer and a third semiconductor layer on the substrate; removing the third semiconductor layer in the third region; forming a fourth sacrificial layer and a fourth semiconductor layer on the substrate; forming active structures extending in a first direction by removing a portion of the first to fourth sacrificial layers, the first to fourth semiconductor layers, and the substrate; forming sacrificial gate structures extending in a second direction intersecting the active structures on the active structures and gate spacer layers on both sidewalls of the sacrificial gate structures; forming recessed regions by removing a portion of the active structures from both sides of the sacrificial gate structures; forming source/drain regions in the recessed regions; and forming the sacrificial gate. A method for forming a gate structure, comprising: removing the structures and the first to fourth sacrificial layers and forming gate structures; and forming contact plugs connected to the source/drain regions, wherein a first channel structure including first to fourth channel layers formed by the first to fourth semiconductor layers is formed in the first region, a second channel structure including fifth and sixth channel layers formed by the third and fourth semiconductor layers is formed in the second region, and a third channel structure including a seventh channel layer formed by the fourth semiconductor layer is formed in the third region.

A method for manufacturing a semiconductor device according to exemplary embodiments may include forming a first sacrificial layer and a first semiconductor layer on a substrate having first and second regions, removing the first semiconductor layer in the second region so that the first sacrificial layer remains, forming a second sacrificial layer and a second semiconductor layer on the first semiconductor layer in the first region and the first sacrificial layer in the second region, forming sacrificial gate structures extending in one direction on the second semiconductor layer, and removing the sacrificial gate structures and the first and second sacrificial layers and forming gate structures.

According to exemplary embodiments, a semiconductor device includes a substrate having first to third regions, first channel structures including first to fourth channel layers that are sequentially arranged and spaced apart from each other along a third direction perpendicular to an upper surface of the substrate on the first region, second channel structures including fifth and sixth channel layers that are sequentially arranged and spaced apart from each other along the third direction on the second region, third channel structures including a seventh channel layer that is arranged on the third region, and gate structures that surround the first to third channel structures on the substrate and extend in one direction, each of the gate structures including a gate dielectric layer that is in contact with each of the first to third channel structures, and a gate electrode layer on the gate dielectric layer, wherein the first to seventh channel layers have the same thickness, and at least one of the fifth to seventh channel layers may be located at a different level from the first to fourth channel layers.

By arranging transistors having different numbers of channel layers, a semiconductor device with improved electrical characteristics can be provided.

By forming transistors having different numbers of channel layers through a simplified process, a method for manufacturing semiconductor devices with improved mass productivity can be provided.

The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments.
FIGS. 2A and 2B are cross-sectional views illustrating semiconductor devices according to exemplary embodiments.
FIGS. 3A and 3B are cross-sectional views illustrating semiconductor devices according to exemplary embodiments.
FIGS. 4A and 4B are cross-sectional views illustrating semiconductor devices according to exemplary embodiments.
FIGS. 5A and 5B are cross-sectional views illustrating semiconductor devices according to exemplary embodiments.
FIGS. 6A and 6B are flowcharts illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.
FIGS. 7A to 20B are drawings illustrating a process sequence to explain a method of manufacturing a semiconductor device according to exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

FIG. 1 is a plan view illustrating a semiconductor device according to exemplary embodiments.

Figures 2a and 2b are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. Figure 2a illustrates a cross-section of the semiconductor device of Figure 1 taken along line I-I', and Figure 2b illustrates cross-sections taken along lines II-II', III-III', and IV-IV'. For convenience of explanation, only some components of the semiconductor device are illustrated in Figure 1.

Referring to FIGS. 1 to 2B, a semiconductor device (100) may include a substrate (101) having first to third regions (R1, R2, R3), active regions (105) on the substrate (101), first to third channel structures (140A, 140B, 140C) including first to seventh channel layers (141-147) arranged vertically spaced apart from each other on the active regions (105), gate structures (160) extending to intersect the active regions (105), source/drain regions (150) in contact with the first to seventh channel layers (141-147), and contact plugs (180) connected to the source/drain regions (150). The semiconductor device (100) may further include a device isolation layer (110), internal spacer layers (130), and an interlayer insulating layer (190). The gate structure (160) may include a gate dielectric layer (162), a gate electrode (165), and gate spacer layers (164).

In the semiconductor device (100), the active region (105) may have a fin structure, and the gate electrode (165) may be disposed between the active region (105) and the first to third channel structures (140A, 140B, 140C), between the first to seventh channel layers (141-147) of the first to third channel structures (140A, 140B, 140C), and on the upper portions of the first to third channel structures (140A, 140B, 140C). Accordingly, the semiconductor device (100) may include a transistor having a MBCFET ^TM (Multi Bridge Channel FET) structure, which is a gate-all-around type field effect transistor, disposed in each of the first to third regions (R1, R2, R3).

The substrate (101) may have an upper surface extending in the x-direction and the y-direction. The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

The first to third regions (R1, R2, R3) of the substrate (101) may be adjacent or spaced apart regions. The first to third regions (R1, R2, R3) may be regions in which transistors including different numbers of some of the first to seventh channel layers (141-147) are respectively arranged.

The device isolation layer (110) may define active regions (105) in the substrate (101). The device isolation layer (110) may be formed, for example, by a shallow trench isolation (STI) process. In some embodiments, the device isolation layer (110) may further include a region that extends deeper and has a step downward from the substrate (101). The device isolation layer (110) may expose the upper surfaces of the active regions (105), and in some embodiments, may partially expose the upper surfaces. In exemplary embodiments, the device isolation layer (110) may have a curved upper surface so that the upper surface has a higher level as it approaches the active regions (105). The device isolation layer (110) may be formed of an insulating material. The device isolation layer (110) may be, for example, an oxide, a nitride, or a combination thereof.

The active regions (105) are defined by the device isolation layer (110) within the substrate (101), and may be arranged to extend in a first direction, for example, the x-direction, respectively. The active regions (105) may have a structure protruding from the substrate (101). According to embodiments, the upper ends of the active regions (105) may be arranged to protrude a predetermined height from the upper surface of the device isolation layer (110). The active regions (105) may be formed as a part of the substrate (101), or may include an epitaxial layer grown from the substrate (101). However, on both sides of the gate structures (160), the active regions (105) may be partially recessed to form recessed regions, and source/drain regions (150) may be arranged in the recessed regions.

In exemplary embodiments, the active regions (105) may include an impurity region. The impurity region may correspond to a well region of the transistor. Accordingly, in the case of a p-type transistor (pFET), the impurity region may include n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb), and in the case of an n-type transistor (nFET), the impurity region may include p-type impurities such as boron (B), gallium (Ga), or aluminum (Al). The impurity region may be positioned at a predetermined depth from the upper surface of the active regions (105) and the substrate (101).

The first to third channel structures (140A, 140B, 140C) may include one or more channel layers (141-147) that are spaced apart from each other in a direction perpendicular to the upper surface of the active regions (105), for example, in the z direction, on the active regions (105). The first to third channel structures (140A, 140B, 140C) may include different numbers of channel layers (141-147). Specifically, in the first region (R1), the first channel structure (140A) may include first to fourth channel layers (141, 142, 143, 144), which are four channel layers sequentially stacked from the bottom. In the second region (R2), the second channel structure (140B) may include fifth and sixth channel layers (145, 146), which are two channel layers sequentially stacked from the bottom. In the third region (R3), the third channel structure (140C) may include a seventh channel layer (147), which is one channel layer.

The first to seventh channel layers (141-147) may have the same thickness. The first to seventh channel layers (141-147) may have substantially the same thickness, with only differences in the range of deviations occurring during the manufacturing process. In the present embodiment, the first thickness (T1) of each of the first to seventh channel layers (141-147) may be the same as or similar to the second thickness (T2) of the gate structures (160) between the first to seventh channel layers (141-147), but is not limited thereto.

At least one of the fifth to seventh channel layers (145, 146, 147) of the second and third channel structures (140B, 140C) may be positioned at a different level, i.e., a different height, than the first to fourth channel layers (141, 142, 143, 144) of the first channel structure (140A). The fifth and sixth channel layers (145, 146) may be positioned at a level between the upper surface of the first channel layer (141) and the lower surface of the fourth channel layer (144). The seventh channel layer (147) may be positioned at a level between the lower surface of the second channel layer (142) and the upper surface of the third channel layer (143). For example, in the present embodiment, the fifth and sixth channel layers (145, 146) may be positioned at the same level as the second and third channel layers (142, 143), respectively, and the seventh channel layer (147) may be positioned at a level corresponding to a level between the second and third channel layers (142, 143), for example, a level between the lower surface of the fifth channel layer (145) and the upper surface of the sixth channel layer (146). However, the relative levels of the fifth to seventh channel layers (145, 146, 147) may be changed depending on the relative thickness relationship of the gate structures (160) between the first to seventh channel layers (141-147) and the first to seventh channel layers (141-147). This will be described in more detail with reference to FIGS. 3A and 3B below.

The first to seventh channel layers (141-147) may be connected to the source/drain regions (150) and spaced apart from the upper surfaces of the active regions (105). The first to seventh channel layers (141-147) may have a width that is the same as or similar to the active regions (105) in the y direction and a width that is the same as or similar to the gate structure (160) in the x direction. In some embodiments, for example, the first to seventh channel layers (141-147) may have a reduced width so as to have a width that is smaller than the entire width of the gate structure (160) in the x direction.

The first to seventh channel layers (141-147) may be made of a semiconductor material, and may include, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). The first to seventh channel layers (141-147) may be made of, for example, the same material as the substrate (101). According to embodiments, the first to seventh channel layers (141-147) may also include an impurity region located in a region adjacent to the source/drain regions (150).

The first channel structure (140A) can form a high speed and high power device that allows a relatively large amount of current to flow by including a relatively large number of channel layers. The second channel structure (140B) can form a low speed and low power device that allows a relatively small amount of current to flow by including a smaller number of channel layers than the first channel structure (140A). The third channel structure (140C) can form an ultra-low speed and ultra-low power device by including a smaller number of channel layers than the second channel structure (140B).

However, in embodiments, the number and shape of the channel layers (141-147) forming each of the first to third channel structures (140A, 140B, 140C) may be varied within a range that satisfies the above-described relationship in the number of channel layers of the first to third channel structures (140A, 140B, 140C). In addition, according to embodiments, the first to third channel structures (140A, 140B, 140C) may further include a channel layer disposed on the upper surface of the active regions (105).

The source/drain regions (150) may be disposed on the active regions (105) on both sides of the gate structures (160) and the first to third channel structures (140A, 140B, 140C), respectively. The source/drain regions (150) may be disposed to cover the side surfaces of each of the first to seventh channel layers (141-147) and the upper surfaces of the active regions (105). The source/drain regions (150) may be disposed in some recess regions on the upper portions of the active regions (105). In the present embodiment, the source/drain regions (150) may be disposed to have the same thickness in the first to third regions (R1, R2, R3).

The upper surfaces of the source/drain regions (150) may be positioned at the same or similar height as the lower surfaces of the gate structures (160) on the first to third channel structures (140A, 140B, 140C), and the heights of the upper surfaces may vary in embodiments. According to embodiments, the source/drain regions (150) may be connected to each other or merged on two or more adjacent active regions (105) along the y direction to form one source/drain region (150).

The gate structures (160) may be arranged to extend in a second direction, for example, in the y direction, intersecting the active regions (105) and the first to third channel structures (140A, 140B, 140C) from above the active regions (105) and the first to third channel structures (140A, 140B, 140C). Physical channel regions of transistors may be formed in the active regions (105) and/or the first to third channel structures (140A, 140B, 140C) intersecting the gate electrode (165) of the gate structure (160). The gate structures (160) may have different levels of upper surfaces in the first to third regions (R1, R2, R3) and the same levels of lower surfaces. The gate structures (160) can sequentially lower the level of the top surfaces from the first region (R1).

For example, in the first region (R1), the gate structure (160) may have the same thickness between the first to fourth channel layers (141, 142, 143, 144) and under the first channel layer (141). In the second region (R2), the gate structure (160) may have a relatively thinner thickness between the fifth channel layer (145) and the sixth channel layer (146) than a thickness under the fifth channel layer (145). In the third region (R3), the gate structure (160) may have a thicker thickness under the seventh channel layer (147) than a thickness under the fifth channel layer (145) in the second region (R2).

The gate structure (160) may include a gate electrode (165), a gate dielectric layer (162) between the gate electrode (165) and the first to seventh channel layers (141-147), and gate spacer layers (164) on side surfaces of the gate electrode (165). In exemplary embodiments, the gate structure (160) may further include a capping layer on a top surface of the gate electrode (165). Alternatively, a portion of the interlayer insulating layer (190) on the gate structure (160) may be referred to as a gate capping layer.

The gate dielectric layer (162) may be disposed between the active region (105) and the gate electrode (165) and between the first to third channel structures (140A, 140B, 140C) and the gate electrode (165), and may be disposed to cover at least a portion of the surfaces of the gate electrode (165). For example, the gate dielectric layer (162) may be disposed to surround all surfaces except the uppermost surface of the gate electrode (165). The gate dielectric layer (162) may extend between the gate electrode (165) and the gate spacer layers (164), but is not limited thereto. The gate dielectric layer (162) may be formed together in the first to third regions (R1, R2, R3) and may have the same thickness.

The gate dielectric layer (162) may include an oxide, a nitride, or a high-k dielectric material. The high-k dielectric material may refer to a dielectric material having a higher dielectric constant than a silicon oxide film (SiO ₂ ). The high-k material may be, for example, any one of aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _{x O y} ), _lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl x O y ), and praseodymium oxide (Pr ₂ O ₃ ). According to embodiments, the gate dielectric layer (162) may be formed of a multilayer film.

The gate electrode (165) may be disposed to fill the space between the first to seventh channel layers (141-147) on the upper portion of the active region (105) and extend onto the first to third channel structures (140A, 140B, 140C). The gate electrode (165) may be spaced from the first to seventh channel layers (141-147) by a gate dielectric layer (162). The gate electrode (165) may include a conductive material, for example, a metal nitride such as a titanium nitride (TiN), a tantalum nitride (TaN), or a tungsten nitride (WN), and/or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to embodiments, the gate electrode (165) may be composed of two or more multilayers.

Gate spacer layers (164) may be arranged on both sides of the gate electrode (165). The gate spacer layers (164) may insulate the source/drain regions (150) and the gate electrodes (165). The gate spacer layers (164) may, according to embodiments, be formed of a multilayer structure. The gate spacer layers (164) may be formed of an oxide, a nitride, and an oxynitride, and in particular, may be formed of a low-k film.

The internal spacer layers (130) may be arranged parallel to the gate electrode (165) between the first to seventh channel layers (141-147) along the z direction. The gate electrode (165) may be stably spaced apart from the source/drain regions (150) by the internal spacer layers (130) and may be electrically isolated therefrom. The internal spacer layers (130) may have a shape in which a side facing the gate electrode (165) is convexly rounded inward toward the gate electrode (165), but is not limited thereto. The internal spacer layers (130) may be formed of an oxide, a nitride, and an oxynitride, and in particular, may be formed of a low-k film. However, according to embodiments, the internal spacer layers (130) may be omitted.

The contact plugs (180) can be connected to the source/drain regions (150) by penetrating the interlayer insulating layer (190) and can apply an electrical signal to the source/drain regions (150). The contact plugs (180) may have slanted sides in which the width of the lower portion is narrower than the width of the upper portion depending on the aspect ratio, but the present invention is not limited thereto. The contact plugs (180) may extend from the upper portion downward, for example, below the lower surface of the uppermost channel layers of each of the first to third channel structures (140A, 140B, 140C), but the present invention is not limited thereto. In exemplary embodiments, the contact plugs (180) may be arranged to contact the upper surfaces of the source/drain regions (150) without recessing the source/drain regions (150).

The contact plugs (180) may include a metal silicide layer positioned at the bottom including the lower surface, and may further include a barrier layer disposed on the upper surface and sidewalls of the metal silicide layer. The barrier layer may include a metal nitride, such as, for example, a titanium nitride (TiN) film, a tantalum nitride (TaN) film, or a tungsten nitride (WN) film. The contact plugs (180) may include a metal material, such as, for example, aluminum (Al), tungsten (W), or molybdenum (Mo). In exemplary embodiments, the number and arrangement of conductive layers constituting the contact plugs (180) may vary.

The contact plugs (180) may sequentially become deeper from the first region (R1), but are not limited thereto. That is, the contact plugs (180) may sequentially become longer in length in the z direction in the first to third regions (R1, R2, R3). This may be because the level of the top surface of the gate structures (160) in the first to third regions (R1, R2, R3) becomes lower, and the level of the source/drain regions (150) also becomes lower. Due to the relative arrangement of the first to third channel structures (140A, 140B, 140C), the gate structures (160), the source/drain regions (150), and the contact plugs (180), the resistance due to the source/drain junction of the transistor may not increase in the second and third regions (R2, R3). That is, in the second and third channel structures (140B, 140C), the fifth to seventh channel layers (145, 146, 147) are positioned close to the gate structures (160) and are positioned relatively higher than the first channel layer (141), so that the resistance due to the source/drain junction can be minimized.

The interlayer insulating layer (190) covers the source/drain regions (150) and the gate structures (160), and may be arranged to cover the device isolation layer (110). The interlayer insulating layer (190) may include at least one of an oxide, a nitride, and an oxynitride, and may include, for example, a low-k material. According to embodiments, the interlayer insulating layer (190) may include a plurality of insulating layers.

Figures 3a and 3b are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. Figures 3a and 3b illustrate cross-sections corresponding to Figure 2a.

Referring to FIG. 3a, in the semiconductor device (100a), the first thickness (T1a) of each of the channel layers (141-147) may be smaller than the second thickness (T2a) of the gate structures (160) between the first to seventh channel layers (141-147).

In this case, the fifth to seventh channel layers (145, 146, 147) may be positioned at different levels from the first to fourth channel layers (141, 142, 143, 144), respectively. For example, the fifth and sixth channel layers (145, 146) may be positioned at a level between the lower surface of the second channel layer (142) and the lower surface of the fourth channel layer (144). For example, the seventh channel layer (147) may be positioned at a level between the upper surface of the second channel layer (142) and the lower surface of the fourth channel layer (144).

Referring to FIG. 3b, in the semiconductor device (100b), the first thickness (T1b) of each of the channel layers (141-147) may be greater than the second thickness (T2b) of the gate structures (160) between the first to seventh channel layers (141-147).

In this case, the fifth to seventh channel layers (145, 146, 147) may be positioned at different levels from the first to fourth channel layers (141, 142, 143, 144), respectively. For example, the fifth and sixth channel layers (145, 146) may be positioned at a level between the lower surface of the second channel layer (142) and the upper surface of the fourth channel layer (144). For example, the seventh channel layer (147) may be positioned at a level between the upper surface of the second channel layer (142) and the lower surface of the fourth channel layer (144).

In this way, in the embodiments, the relative levels of the first to fourth channel layers (141, 142, 143, 144) and the fifth to seventh channel layers (145, 146, 147) can be varied.

Figures 4a and 4b are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. Figures 4a and 4b illustrate cross-sections corresponding to Figure 2a.

Referring to FIG. 4A, in the semiconductor device (100C), the level of the fifth channel layer (145C) of the second channel structure (140B) may be different from the embodiments of FIGS. 2A and 2B. For example, the fifth channel layer (145C) may be positioned at the same level as the first channel layer (141). Accordingly, the thickness of the gate structure (160) between the fifth channel layer (145C) and the sixth channel layer (146) may be relatively thicker than the thickness of the gate structure (160) under the fifth channel layer (145C).

Referring to FIG. 4B, in the semiconductor device (100d), the level of the fifth channel layer (145d) of the second channel structure (140B) may be different from the embodiments of FIGS. 2A and 2B and the embodiment of FIG. 4A. For example, the fifth channel layer (145d) may be positioned at a level corresponding to between the first channel layer (141) and the second channel layer (142). Accordingly, for example, the thickness of the gate structure (160) between the fifth channel layer (145d) and the sixth channel layer (146) may be the same as or similar to the thickness of the gate structure (160) under the fifth channel layer (145d).

In this way, in the embodiments, the relative levels of the fifth channel layers (145c, 145d) may be varied, and accordingly, the thickness of the gate structure (160) above and below may also be varied. Furthermore, in the embodiments, the levels of the sixth and seventh channel layers (146, 147) may also be varied within the levels corresponding to the first to fourth channel layers (141, 142, 143, 144).

Figures 5a and 5b are cross-sectional views illustrating semiconductor devices according to exemplary embodiments. Figures 5a and 5b illustrate cross-sections corresponding to Figure 2a.

Referring to FIG. 5a, in the semiconductor device (100e), the source/drain regions (150e) may be arranged with the levels of the lower surfaces being constant in the first to third regions (R1, R2, R3). Accordingly, the source/drain regions (150e) may have a thinner thickness in the second region (R2) than in the first region (R1), and may have a thinner thickness in the third region (R3) than in the second region (R2). According to embodiments, a separate etch stop layer may be further arranged below the source/drain regions (150e).

Referring to FIG. 5b, the semiconductor element (100f) may not include an internal spacer layer (130), unlike the embodiment of FIG. 2a. In this embodiment, the source/drain regions (150) may have a shape that extends to an area where the internal spacer layers (130) are omitted. Accordingly, the source/drain regions (150) may include areas that extend vertically between the first to sixth channel layers (141-146) and below the seventh channel layer (147) in an area in contact with the gate dielectric layers (162).

In another embodiment, the source/drain regions (150) may not extend into the region where the internal spacer layers (130) are omitted, and the gate electrodes (165) may be arranged to extend along the x-direction.

With this structure, the internal spacer layer (130) can be omitted, so that the source/drain regions (150) can be formed to have improved crystallinity. According to embodiments, the internal spacer layer (130) may be omitted only in some elements of the semiconductor element (100f) or only in some of the first to third regions (R1, R2, R3). For example, when SiGe is used in the source/drain regions (150) in a pFET, the internal spacer layer (130) can be selectively omitted only in the pFET in order to improve the crystallinity of the SiGe.

FIGS. 6A and 6B are flowcharts illustrating a method for manufacturing a semiconductor device according to exemplary embodiments.

FIGS. 7A to 20B are drawings illustrating a process sequence for explaining a method for manufacturing a semiconductor device according to exemplary embodiments. FIGS. 7A to 20B illustrate an embodiment of a manufacturing method for manufacturing the semiconductor device of FIGS. 1 to 2B, and illustrate cross-sections corresponding to FIGS. 2A and 2B, respectively.

First, referring to FIGS. 6b, 7a to 13b below, a step (S110) of alternately stacking first to fourth sacrificial layers (121, 122, 123, 124) and first to fourth semiconductor layers (SL1, SL2, SL3, SL4) on a substrate (101) having first to third regions (R1, R2, R3) will be described.

Referring to FIG. 6b, FIG. 7a, and FIG. 7b, a first sacrificial layer (121) and a first semiconductor layer (SL1) can be formed on a substrate (101) (S111).

The first sacrificial layer (121) and the second to fourth sacrificial layers (122, 123, 124) described below (see FIGS. 8A to 13B) may be layers that are replaced with a gate dielectric layer (162) and a gate electrode (165) through a subsequent process, as shown in FIGS. 2A and 2B. The first to fourth sacrificial layers (121, 122, 123, 124) may be formed of a material having etch selectivity with respect to the first to fourth semiconductor layers (SL1, SL2, SL3, SL4), respectively. The first semiconductor layer (SL1) and the second to fourth semiconductor layers (SL2, SL3, SL4) described below may be layers forming the first to seventh channel layers (141 to 147). The first to fourth semiconductor layers (SL1, SL2, SL3, SL4) may include a different material from the first to fourth sacrificial layers (121, 122, 123, 124).

The first to fourth sacrificial layers (121, 122, 123, 124) and the first to fourth semiconductor layers (SL1, SL2, SL3, SL4) include a semiconductor material including, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the first to fourth sacrificial layers (121, 122, 123, 124) may include silicon germanium (SiGe), and the first to fourth semiconductor layers (SL1, SL2, SL3, SL4) may include silicon (Si).

The first sacrificial layer (121) and the first semiconductor layer (SL1) can be formed by performing an epitaxial growth process from the substrate (101). Each of the first sacrificial layer (121) and the first semiconductor layer (SL1) may have, for example, about 1 It can have a thickness in the range of about 100 nm.

Referring to FIGS. 6b, 8a, and 8b, the first semiconductor layer (SL1) can be removed in the second and third regions (R2, R3) (S112).

First, a first mask layer (ML1) can be formed in the first region (R1) to expose the second and third regions (R2, R3). The first mask layer (ML1) can be, for example, a photomask layer. Next, the first semiconductor layer (SL1) can be selectively removed with respect to the first sacrificial layer (121) in the second and third regions (R2, R3). The first semiconductor layer (SL1) can be removed by a dry etching or wet etching process.

Referring to FIG. 6b, FIG. 9a, and FIG. 9b, a second sacrificial layer (122) and a second semiconductor layer (SL2) can be formed on the substrate (101) (S113).

The second sacrificial layer (122) and the second semiconductor layer (SL2) may be formed over the entire first to third regions (R1, R2, R3). In the second and third regions (R2, R3), the second sacrificial layer (122) may be formed on the first sacrificial layer (121). The second sacrificial layer (122) and the second semiconductor layer (SL2) may be formed by performing an epitaxial growth process from the first semiconductor layer (SL1) or the first sacrificial layer (121) below.

Referring to FIG. 6b, FIG. 10a, and FIG. 10b, the second semiconductor layer (SL2) can be removed in the second and third regions (R2, R3) (S114).

The second semiconductor layer (SL2) can be removed in the same manner as the first semiconductor layer (SL1) described above. First, a second mask layer (ML2) can be formed in the first region (R1) to expose the second and third regions (R2, R3). The second mask layer (ML2) can be, for example, a photomask layer. Next, the second semiconductor layer (SL2) can be selectively removed in the second and third regions (R2, R3) with respect to the second sacrificial layer (122).

Referring to FIG. 6b, FIG. 11a, and FIG. 11b, a third sacrificial layer (123) and a third semiconductor layer (SL3) can be formed on the substrate (101) (S115).

The third sacrificial layer (123) and the third semiconductor layer (SL3) may be formed over the entire first to third regions (R1, R2, R3). In the second and third regions (R2, R3), the third sacrificial layer (123) may be formed on the second sacrificial layer (122). The third sacrificial layer (123) and the third semiconductor layer (SL3) may be formed by performing an epitaxial growth process from the second semiconductor layer (SL2) or the second sacrificial layer (122) below.

Referring to FIG. 6b, FIG. 12a, and FIG. 12b, the third semiconductor layer (SL3) can be removed in the third region (R3) (S116).

First, a third mask layer (ML3) can be formed in the first and second regions (R1, R2) to expose the third region (R3). The third mask layer (ML3) can be, for example, a photomask layer. Next, the third semiconductor layer (SL3) in the third region (R3) can be selectively removed with respect to the third sacrificial layer (123).

Referring to FIG. 6b, FIG. 13a, and FIG. 13b, a fourth sacrificial layer (124) and a fourth semiconductor layer (SL4) can be formed on the substrate (101) (S117).

The fourth sacrificial layer (124) and the fourth semiconductor layer (SL4) may be formed over the entire first to third regions (R1, R2, R3). In the third region (R3), the fourth sacrificial layer (124) may be formed on the third sacrificial layer (123). The fourth sacrificial layer (124) and the fourth semiconductor layer (SL4) may be formed by performing an epitaxial growth process from the third semiconductor layer (SL3) or the third sacrificial layer (123) below.

Accordingly, in the first region (R1), the first to fourth sacrificial layers (121, 122, 123, 124) and the first to fourth semiconductor layers (SL1, SL2, SL3, SL4) can be alternately stacked. In the second region (R2), the first to third sacrificial layers (121, 122, 123), the third semiconductor layer (SL3), the fourth sacrificial layer (124), and the fourth semiconductor layer (SL4) can be sequentially stacked. In the third region (R3), the first to fourth sacrificial layers (121, 122, 123, 124) and the fourth semiconductor layer (SL4) can be sequentially stacked.

In the above steps, the first to fourth sacrificial layers (121, 122, 123, 124) and the first to fourth semiconductor layers (SL1, SL2, SL3, SL4) are formed together in the entire first to third regions (R1, R2, R3), and the removal process of the first to third semiconductor layers (SL1, SL2, SL3) can be formed only in some regions. Accordingly, the process can be simplified while forming different laminated structures in the first to third regions (R1, R2, R3).

Referring to FIG. 6a, FIG. 14a, and FIG. 14b, the first to fourth sacrificial layers (121, 122, 123, 124), the first to fourth semiconductor layers (SL1, SL2, SL3, SL4), and a portion of the substrate (101) are removed to form active structures (AS1, AS2, AS3), and a device isolation layer (110) can be formed (S120).

The active structures (AS1, AS2, AS3) may include some of the first to fourth sacrificial layers (121, 122, 123, 124) and the first to seventh channel layers (141-147), and may further include active regions (105) formed by removing a part of the substrate (101) to protrude from the substrate (101). The active structures (AS1, AS2, AS3) may be formed in a line shape extending in one direction, for example, the x direction, and may be formed spaced apart from each other in the y direction. In this step, in the first region (R1), a first channel structure (140A) including the first to fourth channel layers (141, 142, 143, 144) by the first to fourth semiconductor layers (SL1, SL2, SL3, SL4) may be defined. In the second region (R2), a second channel structure (140B) including fifth and sixth channel layers (145, 146) by third and fourth semiconductor layers (SL3, SL4) can be defined. In the third region (R3), a third channel structure (140C) including a seventh channel layer (147) by fourth semiconductor layer (SL4) can be defined. However, in this step, the first to third channel structures (140A, 140B, 140C) may have a form extending in the x direction. Therefore, depending on the description method, the first to third channel structures (140A, 140B, 140C) may be viewed as being defined in a subsequent step, for example, in the step of forming recess regions (RC) described below with reference to FIGS. 16A and 16B.

In an area where a portion of the substrate (101) has been removed, a device isolation layer (110) can be formed by filling in an insulating material and then removing a portion of the insulating material so that the active regions (105) protrude. The upper surface of the device isolation layer (110) can be formed lower than the upper surfaces of the active regions (105).

Referring to FIG. 6a, FIG. 15a, and FIG. 15b, sacrificial gate structures (170) and gate spacer layers (164) can be formed on active structures (AS1, AS2, AS3) (S130).

The sacrificial gate structures (170) may be sacrificial structures formed in a region where a gate dielectric layer (162) and a gate electrode (165) are disposed, as shown in FIGS. 2A and 2B, through a subsequent process. The sacrificial gate structure (170) may include first and second sacrificial gate layers (172, 175) and a mask pattern layer (176) that are sequentially stacked. The first and second sacrificial gate layers (172, 175) may be patterned using the mask pattern layer (176). The first and second sacrificial gate layers (172, 175) may be an insulating layer and a conductive layer, respectively, but are not limited thereto, and the first and second sacrificial gate layers (172, 175) may be formed as a single layer. For example, the first sacrificial gate layer (172) may include silicon oxide, and the second sacrificial gate layer (175) may include polysilicon. The mask pattern layer (176) may include silicon oxide and/or silicon nitride. The sacrificial gate structures (170) may have a line shape extending in one direction intersecting the active structures (AS1, AS2, AS3). The sacrificial gate structures (170) may extend in the y direction, for example, and may be arranged spaced apart from each other in the x direction.

Gate spacer layers (164) may be formed on both sidewalls of the sacrificial gate structures (170). The gate spacer layers (164) may be made of a low-k material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

Referring to FIGS. 6A, 16A, and 16B, on both sides of the sacrificial gate structures (170), portions of the active structures (AS1, AS2, AS3) may be removed to form recess regions (RC) (S140).

First, by using the sacrificial gate structures (170) and the gate spacer layers (164) as masks, portions of the exposed first to fourth sacrificial layers (121, 122, 123, 124) and the first to seventh channel layers (141-147) may be removed to form recess regions (RC). As a result, the first to third channel structures (140A, 140B, 140C) may have a limited length along the x direction. The recess regions (RC) may be formed with a constant size and depth in the first to third regions (R1, R2, R3).

Next, the first to fourth sacrificial layers (121, 122, 123, 124) can be selectively etched with respect to the first to seventh channel layers (141-147) by, for example, a wet etching process, and removed to a predetermined depth from the side surface along the x direction. The first to fourth sacrificial layers (121, 122, 123, 124) can have inwardly concave side surfaces by the side surface etching as described above. However, the shape of the side surfaces of the first to fourth sacrificial layers (121, 122, 123, 124) is not limited to that illustrated.

Referring to FIG. 6a, FIG. 17a, and FIG. 17b, internal spacer layers (130) can be formed, and source/drain regions (150) filling the recess regions (RC) can be formed (S150).

First, internal spacer layers (130) can be formed in areas where the first to fourth sacrificial layers (121, 122, 123, 124) are partially removed. The internal spacer layers (130) can be formed by filling an insulating material in areas where the first to fourth sacrificial layers (121, 122, 123, 124) are removed, and removing the insulating material deposited on the outside of the first to seventh channel layers (141-147). The internal spacer layers (130) can be formed of the same material as the gate spacer layers (164), but is not limited thereto. For example, the internal spacer layers (130) can include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN.

Next, the source/drain regions (150) may be formed by growing from the side surfaces of the active regions (105) and the first to seventh channel layers (141-147), for example, by a selective epitaxial process. The source/drain regions (150) may include impurities by in-situ doping and may include a plurality of layers having different doping elements and/or doping concentrations.

Referring to FIG. 6a, FIG. 18a, and FIG. 18b, an interlayer insulating layer (190) can be formed, and the sacrificial gate structures (170) and the first to fourth sacrificial layers (121, 122, 123, 124) can be removed (S160).

The interlayer insulating layer (190) can be formed by forming an insulating film covering the sacrificial gate structures (170) and the source/drain regions (150) and performing a planarization process. In this step, the upper surfaces of the interlayer insulating layer (190) in the first to third regions (R1, R2, R3) can be located at different levels, but are not limited thereto.

The sacrificial gate structures (170) and the first to fourth sacrificial layers (121, 122, 123, 124) can be selectively removed with respect to the gate spacer layers (164), the interlayer insulating layer (190), the first to seventh channel layers (141-147), and the internal spacer layers (130). First, the sacrificial gate structures (170) are removed to form upper gap regions (UR), and then the first to fourth sacrificial layers (121, 122, 123, 124) exposed through the upper gap regions (UR) are removed to form lower gap regions (LR). For example, when the first to fourth sacrificial layers (121, 122, 123, 124) include silicon germanium (SiGe) and the first to seventh channel layers (141-147) include silicon (Si), the first to fourth sacrificial layers (121, 122, 123, 124) can be selectively removed by performing a wet etching process using peracetic acid as an etchant. During the removal process, the source/drain regions (150) can be protected by the interlayer insulating layer (190) and the internal spacer layers (130).

Referring to FIG. 6a, FIG. 19a, and FIG. 19b, gate structures (160) can be formed (S160).

Gate structures (160) can be formed to fill the upper gap regions (UR) and the lower gap regions (LR). Gate dielectric layers (162) can be formed to conformally cover the inner surfaces of the upper gap regions (UR) and the lower gap regions (LR). After the gate electrode (165) is formed to completely fill the upper gap regions (UR) and the lower gap regions (LR), it can be removed from the upper portion of the upper gap regions (UR) to a predetermined depth together with the gate dielectric layers (162) and the gate spacer layers (164). As a result, gate structures (160) including the gate dielectric layer (162), the gate electrode (165), and the gate spacer layers (164) can be formed.

Next, an interlayer insulating layer (190) can be further formed on the gate structures (160).

Referring to FIG. 6a, FIG. 20a, and FIG. 20b, a contact plug (180) can be formed (S170).

First, as illustrated in FIGS. 20A and 20B, the interlayer insulating layer (190) may be patterned to form contact holes (CH) exposing the source/drain regions (150). The lower surfaces of the contact holes (CH) may be recessed into the source/drain regions (150) or formed along the upper surfaces of the source/drain regions (150).

Next, referring to FIGS. 2A and 2B together, a conductive material can be embedded within the contact holes (CH). Specifically, after depositing a material forming a barrier layer within the contact holes (CH), a silicide process can be performed to form a metal-semiconductor compound layer, such as a silicide layer, at the bottom. Next, a conductive material can be deposited to fill the contact holes (CH), thereby forming contact plugs (180).

The present invention is not limited to the above-described embodiments and the attached drawings, but is intended to be defined by the appended claims. Therefore, those skilled in the art will appreciate that various substitutions, modifications, and alterations may be made without departing from the technical spirit of the present invention as defined in the claims, and such modifications are also within the scope of the present invention.

101: Substrate 105: Active area
110: Device isolation layer 121, 122, 123, 124: Sacrificial layer
130: Inner spacer layer 140A, 140B, 140C: Channel structure
141-147: Channel layer 150: Source/drain region
160: Gate structure 162: Gate dielectric layer
164: Gate spacer layer 165: Gate electrode
170: Sacrificial gate structure 180: Contact plug
190: Interlayer insulation layer

Claims (10)

A step of forming a first sacrificial layer and a first semiconductor layer on a substrate having first to third regions;
In the second and third regions, a step of removing the first semiconductor layer;
A step of forming a second sacrificial layer and a second semiconductor layer on the substrate;
In the second and third regions, a step of removing the second semiconductor layer;
A step of forming a third sacrificial layer and a third semiconductor layer on the substrate;
In the third region, a step of removing the third semiconductor layer;
A step of forming a fourth sacrificial layer and a fourth semiconductor layer on the substrate;
A step of forming active structures extending in a first direction by removing a portion of the first to fourth sacrificial layers, the first to fourth semiconductor layers, and the substrate;
A step of forming sacrificial gate structures extending in a second direction intersecting the active structures on the active structures and gate spacer layers on both sidewalls of the sacrificial gate structures;
A step of forming recess regions by removing some of the active structures on both sides of the sacrificial gate structures;
A step of forming source/drain regions in the above recess regions;
A step of removing the above sacrificial gate structures and the first to fourth sacrificial layers and forming gate structures; and
comprising a step of forming contact plugs connected to the source/drain regions;
In the first region, a first channel structure is formed including first to fourth channel layers formed by the first to fourth semiconductor layers,
In the second region, a second channel structure is formed including fifth and sixth channel layers formed by the third and fourth semiconductor layers,
A method for manufacturing a semiconductor device, wherein a third channel structure including a seventh channel layer formed by the fourth semiconductor layer is formed in the third region.
In the first paragraph,
A method for manufacturing a semiconductor device, wherein the formation process of each of the first to fourth sacrificial layers and the first to fourth semiconductor layers is performed simultaneously for all of the first to third regions.
In the first paragraph,
A method for manufacturing a semiconductor device, wherein at least one of the fifth to seventh channel layers is located at a different level from the first to fourth channel layers.
In the first paragraph,
A method for manufacturing a semiconductor device, wherein the fifth to seventh channel layers are positioned at a level between the upper surface of the first channel layer and the lower surface of the fourth channel layer.
In the first paragraph,
The second sacrificial layer is formed on the first semiconductor layer in the first region, and is formed on the first sacrificial layer in the second and third regions,
The third sacrificial layer is formed on the second semiconductor layer in the first region, and is formed on the second sacrificial layer in the second and third regions.
A method for manufacturing a semiconductor device, wherein the fourth sacrificial layer is formed on the third semiconductor layer in the first and second regions, and is formed on the third sacrificial layer in the third region.
In the first paragraph,
The step of forming the above gate structures is:
A step of forming gate dielectric layers on the first to third channel structures; and
comprising a step of forming gate electrode layers on the above gate dielectric layers,
A method for manufacturing a semiconductor device, wherein the gate dielectric layers are formed simultaneously in the first to third regions.
A step of forming a first sacrificial layer and a first semiconductor layer on a substrate having first and second regions;
In the second region, a step of removing the first semiconductor layer so that the first sacrificial layer remains;
A step of forming a second sacrificial layer and a second semiconductor layer on the first semiconductor layer of the first region and the first sacrificial layer of the second region;
A step of forming sacrificial gate structures extending in one direction on the second semiconductor layer; and
A method for manufacturing a semiconductor device, comprising the steps of removing the sacrificial gate structures and the first and second sacrificial layers and forming gate structures.
A substrate having first to third regions;
First channel structures including first to fourth channel layers sequentially arranged and spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the first region;
Second channel structures including fifth and sixth channel layers sequentially arranged spaced apart from each other along the third direction on the second region;
Third channel structures including a seventh channel layer disposed on the third region; and
The gate structures each include a gate dielectric layer extending in one direction and surrounding the first to third channel structures on the substrate, and a gate electrode layer on the gate dielectric layer in contact with each of the first to third channel structures,
The first to seventh channel layers have the same thickness,
At least one of the fifth to seventh channel layers is located at a different level from the first to fourth channel layers,
At least one of the first thickness of the gate structure between the fifth channel layer and the sixth channel layer and the second thickness of the gate structure below the fifth channel layer is greater than the third thickness of the gate structure between the first channel layer and the second channel layer,
A semiconductor device wherein the fourth thickness of the gate structure under the seventh channel layer is greater than the first thickness and the second thickness.
A substrate having first to third regions;
First channel structures including first to fourth channel layers sequentially arranged and spaced apart from each other along a third direction perpendicular to the upper surface of the substrate on the first region;
Second channel structures including fifth and sixth channel layers sequentially arranged spaced apart from each other along the third direction on the second region;
Third channel structures including a seventh channel layer disposed on the third region; and
The gate structures each include a gate dielectric layer extending in one direction and surrounding the first to third channel structures on the substrate, and a gate electrode layer on the gate dielectric layer in contact with each of the first to third channel structures,
The first to seventh channel layers have the same thickness,
At least one of the fifth to seventh channel layers is located at a different level from the first to fourth channel layers,
The fifth channel layer is located at the same level as the second channel layer,
The above 6th channel layer is located at the same level as the above 3rd channel layer,
A semiconductor device in which the seventh channel layer is located at a level between the lower surface of the fifth channel layer and the upper surface of the sixth channel layer.
In paragraph 8,
A semiconductor device in which the gate dielectric layers in the first to third regions have the same thickness.