KR101190920B1 - Stacked semiconductor package and method of manufacturing thereof - Google Patents

Abstract

The present invention relates to a laminated semiconductor package and a method of manufacturing the same, wherein a pair of semiconductor dies are embedded in a wiring board in a face up-down form, thereby simplifying the wiring and the process while increasing the number of semiconductor dies embedded in the wiring board, thereby increasing the overall package. Provided is a method of manufacturing the laminated semiconductor package capable of reducing the thickness. The present invention for this purpose is a first wiring board having a cavity formed on the upper surface; A first semiconductor die flip-chip bonded to the cavity; A second semiconductor die mounted face-up on the first semiconductor die; A resin part filled in the cavity; And an upper package including at least one semiconductor die and stacked to be electrically connected to the first wiring board and the second semiconductor die through solder balls. By the above configuration, the present invention has the effect of simplifying the process while reducing the overall thickness of the package.

Description

Stacked semiconductor package and method of manufacturing thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated semiconductor package and a method of manufacturing the same, and more particularly, to embed a pair of semiconductor dies in a face up-down form in a wiring board to simplify the wiring and the process while increasing the number of semiconductor dies embedded in the wiring board. The present invention relates to a method for manufacturing a laminated semiconductor package capable of reducing the overall package thickness.

As products equipped with the latest semiconductor packages are thin and short, and many functions are required, semiconductor package technology is a method such as SIP (System in Package) and POP (Package on Package) for mounting a plurality of semiconductor chips in a semiconductor package. The trend is to use

The number of semiconductor dies stacked in order to increase the capacity of such a semiconductor package is increased, but in the case of simply stacking the semiconductor dies, the total thickness of the package increases as the number of stacked stacks increases, so that the thin and small size of the product tends not to be achieved. In order to solve this problem, it is required to reduce the thickness of the entire package while increasing the capacity of the semiconductor package.

As a solution to this, an embedded PCB, in which a semiconductor die is embedded inside a PCB, has been introduced in the case of a package stacked on the bottom thereof. This reduces the thickness of the entire package.

In addition, since the semiconductor die is embedded in the wiring board, the wiring for the semiconductor may be replaced by the internal wiring of the wiring board, so that the overall wiring is simplified and shortened, thereby improving product performance.

However, such a semiconductor package using a conventional embedded PCB has a limited number of semiconductor dies embedded in the wiring board, the manufacturing process of the wiring board is complicated, and some wire bonding is omitted to simplify wiring. The wiring has a rather complicated problem.

In order to solve the above problems of the prior art, the present invention is to provide a laminated semiconductor package and a method of manufacturing the same that can simplify the wiring and reduce the overall thickness of the package by increasing the number of semiconductor chips embedded in the wiring board. do.

The present invention for solving the above problems is the first wiring board having a cavity formed on the upper surface; A first semiconductor die flip-chip bonded to the cavity; A second semiconductor die mounted face-up on the first semiconductor die; A resin part filled in the cavity; And an upper package including at least one semiconductor die and stacked to be electrically connected to the first wiring board and the second semiconductor die through solder balls, wherein the first wiring board includes a wiring terminal and a first via hole. Build-up including an upper wiring board, an intermediate wiring board having a cavity or a through-hole inserted into a passive element, and a lower wiring board having a second via hole and an external terminal, wherein the wiring terminal, the first via hole, and the passive The device, the second via hole and the external terminal may be electrically connected to each other.

According to another aspect of the present invention, a multilayer semiconductor package includes: a first wiring board having a cavity formed on an upper surface thereof; A first semiconductor die flip-chip bonded to the cavity; A second semiconductor die mounted face-up on the first semiconductor die; A resin part filled in the cavity; A second wiring board stacked on the first wiring board and the second semiconductor die and electrically connected to the second semiconductor die through a first solder ball; And an upper package including at least one semiconductor die and stacked to be electrically connected to the second wiring board through the second solder ball, wherein the first wiring board includes an upper wiring board on which wiring terminals and a first via hole are formed. And an intermediate wiring board formed with a cavity or a through hole, into which a passive element is inserted, and a lower wiring board having a second via hole and an external terminal, wherein the wiring terminal, the first via hole, the passive element, and the The second via hole and the external terminal may be electrically connected to each other.

Preferably, the semiconductor device may further include a redistribution layer formed on the second semiconductor die.

Preferably, the method may further include an adhesive layer formed on the bottom surface of the second semiconductor die.

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Preferably, the upper package may further include a third wiring board on which the at least one semiconductor die is stacked, and a molding part for sealing the at least one semiconductor die.

Preferably, the upper package may be a multichip package in which the at least one semiconductor die is stacked face-up.

Preferably, the upper package may include a third semiconductor die flip-chip bonded onto the third wiring board and a fourth semiconductor die stacked face-up on the third semiconductor die.

According to another aspect of the present invention, there is provided a method of manufacturing a laminated semiconductor package, comprising: preparing a first wiring board; Forming a cavity on an upper surface of the first wiring board; Flip chip bonding a first semiconductor die to the cavity; Stacking a second semiconductor die face-up on the first semiconductor die; Filling a resin into the cavity; And stacking an upper package including at least one semiconductor die on the first wiring board and the second semiconductor die to be electrically connected to each other via solder balls. The preparing of the first wiring board may include: And build up the upper wiring board having the wiring terminal and the first via hole, the intermediate wiring board having the cavity or through-hole formed therein and inserting the passive element, and the lower wiring board having the second via hole and the external terminal formed thereon. The first via hole, the passive element, the second via hole, and the external terminal may be provided to be electrically connected to each other.

According to another aspect of the present invention, there is provided a method of manufacturing a laminated semiconductor package, comprising: preparing a first wiring board; Forming a cavity on an upper surface of the first wiring board; Flip chip bonding a first semiconductor die to the cavity; Stacking a second semiconductor die face-up on the first semiconductor die; Filling a resin into the cavity; Forming a second wiring board on the first wiring board and the second semiconductor die to be electrically connected to the second semiconductor die through a first solder ball; And stacking an upper package including at least one semiconductor die to be electrically connected to the second wiring board through the second solder ball. The preparing of the first wiring board may include: a wiring terminal and a second wiring board; 1, an upper wiring board having a via hole formed therein, an intermediate wiring board having a cavity or a through hole formed therein into which passive elements are inserted, and a lower wiring board having a second via hole and an external terminal formed thereon; The passive element, the second via hole, and the external terminal may be provided to be electrically connected to each other.

Preferably, the preparation step may include a passive element in the first wiring board.

Preferably, the method may further include forming a redistribution layer on the second semiconductor die before the stacking of the second semiconductor die.

Preferably, in the stacking of the second semiconductor die, the second semiconductor die may be adhered with an adhesive.

Preferably, the upper package may be a multichip package in which the at least one semiconductor die is stacked face-up.

The laminated semiconductor package and the method of manufacturing the same according to the present invention simplify the wiring by embedding a pair of semiconductor dies in a face up-down form, thereby increasing the number of semiconductors embedded in the wiring board, thereby reducing the overall thickness of the package. There is an effect that can be simplified.

1 is a cross-sectional view of a multilayer semiconductor package according to a first embodiment of the present invention,
2 is a cross-sectional view showing a modification of FIG.
3 is a cross-sectional view illustrating a process of manufacturing a multilayer semiconductor package according to a first embodiment of the present invention;
4 is a cross-sectional view of a multilayer semiconductor package according to a second embodiment of the present invention.
5 is a cross-sectional view illustrating a process of manufacturing a multilayer semiconductor package according to a second embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

First, a multilayer semiconductor package according to a first embodiment of the present invention will be described with reference to FIG. 1.

1 is a cross-sectional view of a multilayer semiconductor package according to a first embodiment of the present invention.

The multilayer semiconductor package 10 is a variation of a package-on-package (PoP) package, in which a pair of semiconductor dies 120 and 130 are embedded with an embedded substrate 100 in a face up-down form. The upper package 200 is stacked on the substrate 100 and has at least one semiconductor die 220 and 230 mounted thereon.

The embedded substrate 100 includes a first wiring board 110 having a cavity 118 formed on an upper surface thereof, a first semiconductor die 120 and a second semiconductor die 130 mounted on the cavity 118, and a first wiring. It includes a passive element 150 embedded in the substrate 110.

The first wiring board 110 includes an upper wiring board 110a on which a first wiring terminal 112 is formed to be connected to the upper package 200, and a first connection to the outside through the first solder ball 160. The intermediate wiring board 110b disposed between the lower wiring board 110c on which the external terminal 116 is formed, and the upper wiring board 110a and the lower wiring board 110c and electrically connected through the first via hole 114. ) Is a multilayer printed circuit board.

Here, the first via hole 114 is formed of a hole penetrating between the upper wiring board 110a, the intermediate wiring board 110b, and the lower wiring board 110c, and the conductive paste is filled in the hole.

In addition, a cavity 118 for mounting the first semiconductor die 120 and the second semiconductor die 130 is formed at a central portion of the first wiring board 110, and the cavity 118 is a semiconductor die stacked with each other. In order to secure a sufficient space for mounting, the upper wiring board 110a is formed to have a depth from the lower wiring board 110c. Preferably, the upper surface of the second semiconductor die 130 is the upper surface of the first wiring board 110. To a depth similar to the thickness of the first semiconductor die 120 and the second semiconductor die 130.

In the present exemplary embodiment, the first wiring substrate 110 is formed as a multilayer, but may be formed as a single layer according to the wiring of the semiconductor dies 120 and 130. That is, the first wiring board 110 has a first wiring terminal 112 electrically connected to the upper package 200 on an upper surface thereof, and is connected to the outside through the first solder ball 130 on the lower surface thereof. The first external terminal 116 may be formed, and the first wire terminal 112 and the first external terminal 116 may be a single-layer printed circuit board electrically connected to each other through the first via hole 114.

The first semiconductor die 120 is flip-chip bonded to the lower wiring board 110c of the first wiring board 110 through the solder balls 122. That is, the first semiconductor die 120 is stacked on the lower wiring board 110c in a face-down manner, and chip pads are connected to the first external terminal 116 of the first wiring board 110 through the first solder balls 122. Is electrically connected).

The second semiconductor die 130 is mounted face-up on the first semiconductor die 120. The first die pad 132 is disposed to face the top surface of the first wiring board 110, and the second semiconductor die 130 is disposed on the first semiconductor die 120. The first adhesive layer 134 is formed on the bottom surface of the die 130. Here, the first adhesive layer 134 may be formed in a liquid or film form, and is formed to coincide with the top surface of the first wiring board 110 and the top surface of the second semiconductor die 130.

In the present embodiment, the second semiconductor die 130 has been described as being mounted in a bare state, but the position of the first die pad 132 is changed to be electrically connected to the upper package 200, and the third In order to match the size of the solder ball 250, the redistribution layer may be formed on the second semiconductor die 130 such that the size of the first die pad 132 is changed.

The resin part 140 is filled to seal the cavity 118 in which the first semiconductor die 120 and the second semiconductor die 130 are mounted. The upper surface of the upper wiring board 110a of the first wiring board 110 is sealed. It is filled to the same height as.

The passive element 150 is formed on one layer inside the first wiring board 110. For example, the passive device 150 is mounted or embedded in the intermediate wiring board 110b. The passive element 150 may be a resistor (R), an inductor (L), and a capacitor (C) associated with the first semiconductor die 120 and the second semiconductor die 130.

In the present exemplary embodiment, the passive element 150 associated with the first semiconductor die 120 and the second semiconductor die 130 is embedded in the first wiring board 110, but the passive element 150 may be formed as necessary. It may not be built in.

The upper package 200 includes at least one semiconductor die and is stacked to be electrically connected to the first wiring board 110 and the second semiconductor die 130 through the third solder ball 250. A molding part for molding the third wiring board 210, the third semiconductor die 220 and the fourth semiconductor die 230 mounted on the third wiring board 210, and the entire upper surface of the third wiring board 210. 240.

The third wiring board 210 may include a second wiring terminal 212 electrically connected to the third semiconductor die 220 and a second wiring terminal 212 electrically connected to the second external terminal 216. And a second via hole 214 and a second external terminal 216 for connecting to the first wiring board 110 through the third solder ball 250. Here, the second via hole 214 is formed of a hole passing through the second wiring terminal 212 and the second external terminal 216, and the inside of the hole is filled with a conductive paste.

The upper package 200 may be a multichip package in which at least one semiconductor die is stacked up in a face-up manner. As shown in FIG. 1, the third semiconductor die 220 and the fourth semiconductor die 230 may be formed. 3 is laminated on the wiring board 210 in the form of a face-up step.

More specifically, the third semiconductor die 220 is stacked in the face-up form on the third wiring board 210, and the third wiring board is formed through the second die pad 222 and the first bonding wire 226. Is electrically connected to 210. A second adhesive layer 224 is formed on the bottom surface of the third semiconductor die 220, and the second adhesive layer 224 may be formed in a liquid or film form.

The fourth semiconductor die 230 is stacked on the third semiconductor die 220 in a step-up stepped manner, and the third wiring board 210 is formed through the third die pad 232 and the second bonding wire 236. Is electrically connected). A third adhesive layer 234 is formed on the bottom surface of the fourth semiconductor die 230, and the third adhesive layer 234 may be formed in a liquid or film form.

In the present embodiment, the upper package 200, as shown in Figure 1, has been described as a multi-chip package stacked in a plurality of steps, but is not limited to this, any form of a single chip or three or more stages as a single package May be laminated.

The molding part 240 is molded to completely cover the third semiconductor die 220 and the fourth semiconductor die 230 to protect the semiconductor dies 220 and 230 and the bonding wires 226 and 236 from external influences.

In such a configuration, the multilayer semiconductor package 10 may bond the pair of semiconductor dies 120 and 130 to each other in a face up-down manner and fill the first wiring substrate 110 with each other to reduce the overall thickness of the PoP package by a simple process. Can be.

2 is a cross-sectional view showing a modification of FIG.

The multilayer semiconductor package 20 is the same as the structure of the multilayer semiconductor package 10 of FIG. 1 except for the upper package 200 in which the third semiconductor die 320 is flip chip bonded onto the third wiring board 210. Detailed description thereof is omitted here.

The upper package 200 includes a third wiring substrate 210 on which wiring is formed, a third semiconductor die 320 flip-chip bonded onto the third wiring substrate 210, and a third semiconductor die 320. A fourth semiconductor die 230 is stacked and a molding part 240 for molding the entire upper surface of the third wiring board 210.

The third semiconductor die 320 is flip chip bonded onto the third wiring board 210 through the solder balls 322. That is, the third semiconductor die 320 is stacked on the third wiring board 210 by face-down, and the chip pads are connected to the second external terminal 216 of the third wiring board 210 through the solder balls 322. Is electrically connected to the

The fourth semiconductor die 230 is stacked on the third semiconductor die 320 in the form of face-up steps, and the third wiring board 210 is formed through the third die pad 232 and the second bonding wire 236. Is electrically connected).

In FIG. 2, the case in which the third semiconductor die 320 is larger than the fourth semiconductor die 230 has been described as an example. However, the third semiconductor die 320 is stacked on the flip chip bonded third semiconductor die 320 through the third adhesive layer 234. The four semiconductor die 230 may be the same size or larger than the third semiconductor die 320.

In the present embodiment, the third semiconductor die 320 is described as being stacked in a bare state. However, in order to reduce the wiring complexity of the third wiring board 210, the position of the chip pad is changed so as to change the position of the chip pad 320. It is also possible to form a redistribution layer.

Hereinafter, a method of manufacturing a multilayer semiconductor package according to a first embodiment of the present invention will be described with reference to FIG. 3.

3 is a cross-sectional view illustrating a process of manufacturing a multilayer semiconductor package according to a first embodiment of the present invention.

The manufacturing method of the multilayer semiconductor package 10 may include preparing a first wiring board 110, forming a cavity 118 on an upper surface of the first wiring board 110, and forming a first wiring board 118 in the cavity 118. Flip chip bonding the semiconductor die 120, laminating the second semiconductor die 130 on the first semiconductor die 120 in a face-up, filling the cavity 118 with resin; And stacking the upper package 200 including at least one semiconductor die on the first wiring board 110 and the second semiconductor die 130 to be electrically connected to each other through the first solder ball 122. .

More specifically, as shown in FIG. 3A, after the cavity or through-hole is formed in the intermediate wiring board 110b of the first wiring board 110 and the passive element 150 is inserted into the cavity or through-hole, And an upper wiring board 110c on which the first wiring terminal 112 and the first via hole 114a are formed, and a lower wiring board 110a on which the first external terminal 116 and the first via hole 114b are formed. Build-up may be performed to form the first wiring board 110. Here, the method of embedding the passive element 150 in the first wiring board 110 is not limited thereto, and may include various types of manufacturing methods capable of embedding the passive element 150 in the first wiring board 110. do.

As shown in FIG. 3B, a cavity 118 for mounting the first semiconductor die 120 and the second semiconductor die 130 is formed at the center of the upper surface of the first wiring board 110. Here, the cavity 118 formed on the first wiring board 110 may be formed such that the top surface of the second semiconductor die 130 stacked on the first semiconductor die 120 coincides with the top surface of the first wiring board 110. It is formed to a depth similar to the thickness of the first semiconductor die 120, for example, in order to ensure sufficient mounting space of the first semiconductor die 120 and the second semiconductor die 130, the lower side from the upper wiring board (110a) It is formed to a depth up to the wiring board 110c.

As illustrated in FIG. 3C, the first semiconductor die 120 is flip-chip bonded to the lower wiring board 110c of the first wiring board 110 through the first solder ball 122. In this case, after applying flux or solder printing to the first external terminal 116 of the first wiring board 110, the first semiconductor die 120 is face-down flip-bonded.

As shown in FIG. 3D, the second semiconductor die 130 is mounted face-up on the second semiconductor die 130. The second semiconductor die 130 is bonded through the first adhesive layer 134. The first die pad 132 having the first adhesive layer 134 formed on the upper surface of the first semiconductor die 120 is first wired. It is disposed to face the upper surface of the substrate 110. Here, the first adhesive layer 134 may be formed in a liquid or film form, and the upper surface of the first wiring board 110 and the upper surface of the second semiconductor die 130 are formed to match.

In FIG. 3, the case in which the first semiconductor die 120 is larger than the second semiconductor die 130 has been described as an example. However, the first semiconductor die 120 is stacked on the flip chip bonded first semiconductor die 120 through the first adhesive layer 134. The second semiconductor die 130 may be the same size or larger than the first semiconductor die 120.

In addition, in the present embodiment, the first semiconductor die 120 has been described as being mounted in a bare state, but the position of the first die pad 132 is changed or the third solder ball is electrically connected to the upper package 200. The size of the first die pad 132 may be changed to match the size of 250, in which case a redistribution layer is formed on the second semiconductor die 130. That is, before the second semiconductor die 130 is stacked on the first semiconductor die 120, a redistribution layer may be formed on the top surface of the first semiconductor die 120 according to the position and size of the third solder ball 250. It may be.

As shown in FIG. 3E, the first semiconductor die 120 and the second semiconductor die 130 are filled with resin to seal the cavity 118 mounted thereon, and the upper wiring board 110 of the first wiring board 110 is sealed. The resin part 140 is formed by filling the resin to the same height as the upper surface of the 110a.

As such, the first semiconductor die 120 is flip-chip bonded to the cavity 118 of the first wiring board 110, and the top surface of the second semiconductor die 130 is exposed on the first semiconductor die 120. Complete the embedded substrate 100.

Next, the upper package 200 is laminated on the embedded substrate 100.

As shown in FIG. 1, the upper package 200 including at least one semiconductor die is electrically connected to the first wiring board 110 and the second semiconductor die 130 through the third solder ball 250. It is stacked on the embedded substrate 100. Here, the upper package 200 stacked on the embedded substrate 100 may include a third wiring board 210 on which wiring is formed, a third semiconductor die 220 mounted on the third wiring board 210, and a third A fourth semiconductor die 230 stacked on the semiconductor die 220 and a molding part 240 for molding the entire upper surface of the third wiring board 210 are included.

In the present exemplary embodiment, at least one semiconductor die is described as a multi-chip stacked in a step-up step, but the present invention is not limited thereto. May be In addition, the third semiconductor die 220 stacked on the third wiring board 210 may be stacked by flip chip bonding on the third wiring board 210.

In this manner, a pair of semiconductor dies 120 and 130 are bonded to each other in a face up-down form and embedded in the first wiring board 110, thereby manufacturing a multilayer semiconductor package having a reduced overall thickness of the PoP package by a simple process. have.

4 is a cross-sectional view of a multilayer semiconductor package according to a second embodiment of the present invention.

In the present embodiment, since the configuration except for the package mounted on the embedded substrate 100 is the same as that of the first embodiment, the description thereof is omitted here.

The multilayer semiconductor package 40 is stacked on the first wiring board 110 and the second semiconductor die 130, and the second wiring board is stacked to be electrically connected through the upper package 200 and the third solder ball 250. 410.

The second wiring board 410 includes a third wiring terminal 412 and a third via hole 414, and is electrically connected to the second semiconductor die 130 mounted on the cavity 118 through the solder ball 136. To be laminated. Here, the solder ball 136, which is electrically connected between the second wiring board 410 and the second semiconductor die 130, is partially embedded in the resin part 140 and partially exposed to expose the second solder substrate 410 of the second wiring board 410. 3 is electrically connected to the wiring terminal 412.

In such a configuration, the multilayer semiconductor package 10 may bond the pair of semiconductor dies 120 and 130 to each other in a face up-down manner and fill the first wiring substrate 110 with each other to reduce the overall thickness of the PoP package by a simple process. Can be.

Hereinafter, a method of manufacturing a multilayer semiconductor package according to a second embodiment of the present invention will be described with reference to FIG. 5.

5 is a cross-sectional view illustrating a process of manufacturing a multilayer semiconductor package according to a second embodiment of the present invention.

The manufacturing method of the multilayer semiconductor package 40 includes preparing a first wiring board 110, forming a cavity 118 on an upper surface of the first wiring board 110, and forming a first wiring board 118 in the cavity 118. Flip chip bonding the semiconductor die 120, laminating the second semiconductor die 130 on the first semiconductor die 120 in a face-up, filling the cavity 118 with resin; Forming a second wiring board 410 on the first wiring board 110 and the second semiconductor die 130 to be electrically connected to the second semiconductor die 130 through the solder balls 136. Stacking the upper package 200 including one semiconductor die to electrically connect the second wiring board 410 and the third solder ball 250.

Since the configuration of the present embodiment is the same as that of the first embodiment except for the second wiring board 410 stacked on the first wiring board 110 and the second semiconductor die 130, the description thereof is omitted here.

5A through 5C, the first semiconductor die 120 is flip chip bonded to the cavity 118 of the first wiring board 110 and the second semiconductor die 120 is formed on the first semiconductor die 120. Stack 130 at face-up.

As shown in FIG. 5D, the first semiconductor die 120 and the second semiconductor die 130 are filled with resin to seal the cavity 118 mounted thereon, and the upper wiring board 110 of the first wiring board 110 is sealed. The resin part 140 is formed by filling the resin to the same height as the upper surface of the 110a. At this time, the resin is filled so that a part of the solder balls 136 electrically connected to the second wiring board 410 and the second semiconductor die 130 are exposed to the outside, or the resin is filled in the cavity 118 and then the second The resin part 140 is cut so that the solder balls 136 formed on the first die pad 132 of the semiconductor die 130 are exposed.

As shown in FIG. 5E, a second wiring board 410 having a third wiring terminal 412 and a third via hole 414 is stacked on the first wiring board 110 and the second semiconductor die 130. do. The second wiring board 410 is electrically connected through the solder balls 136 formed on the first die pad 132 of the second semiconductor die 130.

As described above, the first semiconductor die 120 is flip-chip bonded to the cavity 118 of the first wiring board 110, and the second semiconductor die 130 is stacked on the first semiconductor die 120 by face-up. Next, the second wiring board 410 is stacked to complete the embedded board 100, and then the upper package 200 is stacked in the same manner as described above.

In this manner, a pair of semiconductor dies 120 and 130 are bonded to each other in a face up-down form and embedded in the first wiring board 110, thereby manufacturing a multilayer semiconductor package having a reduced overall thickness of the PoP package by a simple process. have.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited thereto, and various modifications can be made within the scope of the technical idea of the present invention, and it is obvious that the present invention belongs to the appended claims. Do.

10: stacked semiconductor package 100: embedded substrate
110: first wiring board 112: first wiring terminal
114: first via hole 116: first external terminal
118: cavity 120: first semiconductor die
122: first solder ball 130: second semiconductor die
132: first die pad 134: first adhesive layer
140: resin portion 150: passive element
160: second solder ball 200: upper package
210: third wiring board 212: second wiring terminal
214: second via hole 216: second external terminal
220: third semiconductor die 222: second die pad
224: second adhesive layer 226: first bonding wire
230: fourth semiconductor die 232: third die pad
234: third adhesive layer 236: second bonding wire
240 molding part 250 third solder ball
410: second wiring board 412: third wiring terminal

Claims (14)

A first wiring board having a cavity formed on an upper surface thereof;
A first semiconductor die flip-chip bonded to the cavity;
A second semiconductor die mounted face-up on the first semiconductor die;
A resin part filled in the cavity; And
And an upper package including at least one semiconductor die and stacked to be electrically connected to the first wiring board and the second semiconductor die through solder balls.
The first wiring board includes an upper wiring board on which wiring terminals and a first via hole are formed, an intermediate wiring board on which passive elements are formed by forming a cavity or a through hole, and a lower wiring board on which a second via hole and an external terminal are formed. And build up, wherein the wiring terminal, the first via hole, the passive element, the second via hole, and the external terminal are electrically connected to each other. A first wiring board having a cavity formed on an upper surface thereof;
A first semiconductor die flip-chip bonded to the cavity;
A second semiconductor die mounted face-up on the first semiconductor die;
A resin part filled in the cavity;
A second wiring board stacked on the first wiring board and the second semiconductor die and electrically connected to the second semiconductor die through a first solder ball; And
And an upper package including at least one semiconductor die and stacked to be electrically connected to the second wiring board through a second solder ball.
The first wiring board includes an upper wiring board on which wiring terminals and a first via hole are formed, an intermediate wiring board on which passive elements are inserted by forming a cavity or a through hole, and a lower wiring board on which a second via hole and an external terminal are formed. And build up, wherein the wiring terminal, the first via hole, the passive element, the second via hole, and the external terminal are electrically connected to each other. The method according to claim 1 or 2,
And further comprising a redistribution layer formed on the second semiconductor die. delete The method according to claim 1 or 2,
And a bonding layer formed on a lower surface of the second semiconductor die. The method according to claim 1 or 2,
The upper package further comprises a third wiring board on which the at least one semiconductor die is stacked, and a molding part sealing the at least one semiconductor die. The method according to claim 6,
And the upper package is a multichip package in which the at least one semiconductor die is stacked face-up. The method according to claim 6,
And the upper package includes a third semiconductor die flip-chip bonded onto the third wiring board and a fourth semiconductor die stacked face-up on the third semiconductor die. Preparing a first wiring board;
Forming a cavity on an upper surface of the first wiring board;
Flip chip bonding a first semiconductor die to the cavity;
Stacking a second semiconductor die face-up on the first semiconductor die;
Filling a resin into the cavity; And
Stacking an upper package including at least one semiconductor die on the first wiring board and the second semiconductor die to be electrically connected through solder balls;
The preparing of the first wiring board may include: an upper wiring board on which wiring terminals and a first via hole are formed, an intermediate wiring board on which passive elements are inserted by forming a cavity or a through hole, and a lower side on which the second via hole and an external terminal are formed; And building up a wiring board, wherein the wiring terminal, the first via hole, the passive element, the second via hole, and the external terminal are electrically connected to each other. Preparing a first wiring board;
Forming a cavity on an upper surface of the first wiring board;
Flip chip bonding a first semiconductor die to the cavity;
Stacking a second semiconductor die face-up on the first semiconductor die;
Filling a resin into the cavity;
Forming a second wiring board on the first wiring board and the second semiconductor die to be electrically connected to the second semiconductor die through a first solder ball; And
Stacking an upper package including at least one semiconductor die to be electrically connected to the second wiring board through a second solder ball;
The preparing of the first wiring board may include: an upper wiring board on which wiring terminals and a first via hole are formed, an intermediate wiring board on which passive elements are inserted by forming a cavity or a through hole, and a lower side on which the second via hole and an external terminal are formed; And building up a wiring board, wherein the wiring terminal, the first via hole, the passive element, the second via hole, and the external terminal are electrically connected to each other. delete 11. The method according to claim 9 or 10,
And forming a redistribution layer on the second semiconductor die before the second semiconductor die deposition step. 11. The method according to claim 9 or 10,
In the stacking of the second semiconductor die, the second semiconductor die is bonded with an adhesive. 11. The method according to claim 9 or 10,
And wherein the upper package is a multichip package in which the at least one semiconductor die is stacked face-up.

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