KR100933442B1 - Line on glass liquid crystal display - Google Patents

Abstract

The present invention provides a LOG type liquid crystal display device capable of minimizing line resistance of a LOG signal line supplying a ground voltage and minimizing image degradation due to the line resistance.

A liquid crystal display device according to the present invention comprises: a liquid crystal display panel including a pixel matrix and a line on glass type signal line group formed in an outer region of the pixel matrix to supply control signals and power signals; A tape carrier package mounted on an outer region of the liquid crystal display panel by mounting a driving integrated circuit for driving the pixel matrix; A main supporter supporting the liquid crystal display panel; And a bottom cover which is grounded with the ground voltage while surrounding the rear edge portion of the main supporter and connected in parallel with the ground line for supplying the ground voltage among the line-on-glass type signal line group.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPLAY OF LINE-ON-GLASS TYPE}             

1 is a plan view showing a line-on-glass type liquid crystal display device.

FIG. 2 is a diagram for describing a horizontal stripe phenomenon in the liquid crystal display illustrated in FIG. 1.

3 is a view showing a specific pattern causing greenish in the conventional liquid crystal display.

4A and 4B show a comparison of the swing width of the gate voltage and the common voltage due to the specific pattern shown in FIG.

FIG. 5 is a view for explaining a greenish phenomenon due to the swing of the common voltage shown in FIGS. 4A and 4B.

FIG. 6 illustrates a specific pattern including a window causing horizontal crosstalk in a conventional liquid crystal display. FIG.

FIG. 7 is a diagram illustrating a comparison between swing widths of a common voltage and a gate low voltage in a section including a window region illustrated in FIG. 6 and a section including no window region.

FIG. 8 is a diagram for explaining a horizontal crosstalk phenomenon caused by the swing of the common voltage shown in FIG. 7. FIG.

9 is a plan view illustrating a LOG type liquid crystal display device according to an exemplary embodiment of the present invention;

FIG. 10 is an exploded perspective view illustrating a portion of a liquid crystal display module including the liquid crystal display shown in FIG. 9.

FIG. 11 is a cross-sectional view illustrating a vertical cross section of the liquid crystal display module illustrated in FIG. 10.

12 is a plan view illustrating a LOG type liquid crystal display device according to an exemplary embodiment of the present invention;

FIG. 13 is an exploded perspective view illustrating a portion of a liquid crystal display module including the liquid crystal display shown in FIG. 12.

<Description of main parts of drawing>

2, 52: thin film transistor array substrate 4, 54: color filter array substrate

6, 56: liquid crystal display panel 8, 58: gate TCP

10, 60: gate drive IC 12, 62: data TCP

14, 64: data drive IC 16, 66: data PCB

18: FPC 20: Main PCB

22: timing control unit 24: power supply unit

26, 76: LOG signal line group 32: horizontal line

58a: exposed area 80, 110: bottom cover

82: bottom cover side portion 84, 116: conductive tape

90: main supporter 92: light guide plate                 

94 optical sheets 96 upper polarizing plate

98: lower polarizer 100: top case

102: support pad 112: first protrusion

114: second protrusion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display capable of minimizing signal distortion caused by a line on glass type signal line by reducing a resistance of a ground line.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the liquid crystal cells display an image by adjusting the light transmittance according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal display panel and the driving. And a power supply unit supplying power signals necessary for driving the circuits.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP in a chip on film (COF) method, and a liquid crystal display panel and a tape automated bonding (TAB) method. Electrically connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal display panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

Drive ICs mounted on a liquid crystal display panel in a COG method control signals from a timing controller mounted on a main PCB through line on glass (LOG) type signal lines formed on the FPC and the liquid crystal display panel. And power signals from the pixel data and the power unit.

Recently, even when the drive ICs are connected to the liquid crystal display panel via TCP, the LOG type signal lines are adopted to eliminate the PCB, thereby making the liquid crystal display device even thinner. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed in a LOG type on the liquid crystal display panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied. In this case, the gate control signals and the gate power signals supplied to the gate drive IC are distorted by the line resistance of the LOG signal lines, thereby causing a problem in that the quality of the image displayed on the liquid crystal display panel is degraded.

In detail, the LOG type liquid crystal display device in which the gate PCB is removed includes a main PCB 20 including a timing controller 22 and a power supply unit 24 and a main PCB (FPC 22) as shown in FIG. 1. A data PCB 16 connected to the 20, a data driver IC 14 mounted thereon, a data TCP 12 connected between the data PCB 16 and the liquid crystal display panel 6, and a gate driver IC 10; And a gate TCP 8 connected to the liquid crystal display panel 6.

The liquid crystal display panel 6 is formed by bonding the thin film transistor array substrate 2 and the color filter array substrate 4 to each other with a liquid crystal interposed therebetween. The liquid crystal display panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal display panel 6. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 18. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal display panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 are supplied to the data TCP 12 via the FPC 18 and the data PCB 16. . Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via the LOG signal line group 26 formed in the edge region of the thin film transistor array substrate 2. Gate control signals and power signals supplied to the gate TCP 12 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10, and the gate drive mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26. It is supplied to the IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 such as the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. Direct current driving voltages; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The LOG signal line group 26 is formed in a fine pattern by using the same gate metal layer as the gate lines in a limited pad region of the thin film transistor array substrate 2. Further, as the LOG signal line group 26 is contacted with the gate TCP 8 through ACF bonding, the contact portion A with the gate TCP 8 increases, resulting in a large contact resistance. Accordingly, the LOG signal line group 26 has a larger line resistance than the signal lines of the conventional gate PCB. Due to this line resistance, the gate control signals GSP, GSC, and GOE transmitted through the LOG signal line group 26 and the power signals VGH, VGL, VCC, GND, and VCOM are distorted, thereby causing horizontal stripes, spots, and the like. The deterioration of image quality such as crosstalk of the dot pattern, greenish, etc. becomes worse.

For example, the LOG signal line groups 26 that supply the gate control signals GSP, GSC, GOE and power signals VGH, VGL, VCC, GND, VCOM are gated as shown in FIG. The first to fourth LOG signal line groups LOG1 to LOG4 are connected to each other between the TCPs 8. Each of the first to fourth LOG signal line groups LOG1 to LOG4 has a line resistance (aΩ, bΩ, cΩ, dΩ) that is proportional to the line length, and passes through the gate TCP 8 and the gate drive IC 10. Are connected in series. Due to the first to fourth LOG signal line groups LOG1 to LOG4, gate control signals GSP, GSC, and GOE input to each gate drive IC 10 and power signals VGH, VGL, VCC, GND, VCOM) will cause a level difference. As a result, a luminance difference is generated between the horizontal line blocks A to D driven by the different gate drive ICs 10, resulting in horizontal stripes 32.

Specifically, the first gate drive IC 10 is provided with the first line resistance aΩ of the first LOG signal line group LOG1, and the second gate drive IC 10 is provided with the first and second LOG signal line groups. Due to the first and second line resistances aΩ + bΩ of LOG1 and LOG2, the third gate drive IC 10 includes the first to third of the first to third LOG signal line groups LOG1 to LOG3. By the line resistance aΩ + bΩ + cΩ, the fourth gate drive IC 10 has the first to fourth line resistances aΩ + bΩ + cΩ + of the first to fourth LOG signal line groups LOG1 to LOG4. The gate control signals GSP, GSC, and GOE, which are dropped by dΩ, and the power signals VGH, VGL, VCC, GND, and VCOM are supplied. Accordingly, as the difference occurs between the gate signals VG1 to VG4 supplied to the gate lines of the first to fourth horizontal blocks A to D driven by different gate drive ICs 10, the horizontal Horizontal stripes 32 are generated between the line blocks A to D. FIG.                         

In addition, when a pattern in which black gray and 31 gray are alternated pixel by pixel is displayed on the liquid crystal panel driven by the dot inversion method as illustrated in FIG. 3, the data size of the transition between adjacent pixels is not canceled. And the gate low voltage VGL and the common voltage VCOM are supplied by the parasitic capacitor as shown in FIG. 4B. 4A and 4B respectively illustrate common voltage VCOM and gate low voltage VGL waveforms swinged by parasitic capacitors when a black gray signal and a 31 gray signal are supplied in a dot inversion manner to a specific data line. . Here, it can be seen that the common voltage VCOM and the gate low voltage VGL swing with the same phase as the black gray signal having a relatively large voltage.

As a result, as shown in FIG. 5, when the black pixel signal is supplied to each of R1, G1, and B1 shown in FIG. 3 and the pixel signal of 31 gray is supplied to each of R2, G2, and B2, the swing is performed along the black pixel signal. Due to the common voltage VCOM, the pixel signal charge values VG1, VR2, and VB2 of the pixel signals charge values VR1, VG1, and VB2 of R1, B1, and G2 become smaller than the pixel voltage charge values VG1, VR2, and VB2. Accordingly, the G1, R2, and B2 pixels appear relatively bright. R1 and B1 to which the black pixel signal is supplied cannot be visually detected, so only the G2 pixel to which 31 gray is supplied appears to be bright, causing a greenish phenomenon.

As shown in FIG. 6, when a pattern in which 31 grays and black grays alternate in sub pixel units is displayed on a liquid crystal panel and a window W displaying the same gray is displayed in a specific area, the window area W is displayed. Since the same gray is displayed, the pixel signal transition size between adjacent pixels cancels out. Accordingly, as illustrated in FIG. 7, the swing widths of the gate low voltage VGL and the common voltage VCOM in the T2 section including the window region W may include T1 not including the window region W. It becomes smaller than the interval. Therefore, the charge values of the pixels driven in the T2 section including the window region W and the pixels driven in the T1 section not included in the window region W are changed. Specifically, as shown in FIG. 8, when the lines R1, G1, and B1 are viewed, except for the G1 line (not visually sensed) to which the black pixel signal is supplied, the lines R1 and B1 are charged in the period T1 (VR1, VB1). It can be seen that the charge amounts VR2 and VB2 in the T2 section are smaller. As a result, horizontal crosstalk may be generated in which pixels driven in the T2 section including the window region W appear relatively brighter than pixels driven in the T1 section including the window region W. FIG.

As such, the swing voltages of the common voltage VCOM and the gate low voltage VGL according to the transition size of the pixel signal are induced to the ground line forming the current path. As a result, the swing width of the common voltage VCOM and the gate low voltage VGL is further increased by the relatively large resistance component of the LOG signal line supplying the ground voltage, thereby increasing the aforementioned greenish and horizontal crosstalk phenomena. It becomes clear.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display device capable of minimizing line resistance of a group of LOG signal lines to minimize image degradation due to the line resistance.                         

Another object of the present invention is to provide a LOG type liquid crystal display device capable of minimizing line resistance of a LOG signal line supplying a ground voltage and minimizing image degradation due to the line resistance.

In order to achieve the above object, the liquid crystal display according to the present invention is a liquid crystal display having a pixel matrix and a line-on-glass signal line group formed in an outer region of the pixel matrix to supply control signals and power signals. A display panel; A tape carrier package mounted on an outer region of the liquid crystal display panel by mounting a driving integrated circuit for driving the pixel matrix; A main supporter supporting the liquid crystal display panel; And a bottom cover which is grounded with the ground voltage while surrounding the rear edge portion of the main supporter and connected in parallel with the ground line for supplying the ground voltage among the line-on-glass type signal line group.

The tape carrier package is characterized in that it has a second ground line connected in series with the line on glass type ground line and having a relatively wide wiring width and partially exposed area.

The bottom cover may be connected to the second ground line through an exposed area of the tape carrier package.

The bottom cover may include a rear portion surrounding the rear portion of the main supporter; And a side portion protruding from the rear portion along the side portion of the main supporter wrapped by the tape carrier package to be in contact with the second ground line. Here, it characterized in that it further comprises a conductive tape applied along the side of the bottom cover attached to the second ground line of the tape carrier package.

The bottom cover may include a rear portion surrounding the rear portion of the main supporter; A first protrusion protruding from the rear portion along a side portion of the main supporter wrapped by the tape carrier package; And a side portion configured to further protrude from the first protrusion to be in contact with the second ground line. Here, it characterized in that it further comprises a conductive tape which is applied to the second protrusion and attached to the second ground line of the tape carrier package.

In addition, the present invention includes a top case surrounding an edge region of the liquid crystal display panel and a side portion of the main supporter; And a support pad for firmly contacting the second ground line and the bottom cover side part between the side part of the bottom cover overlapping the side part of the top case.

The tape carrier package may include a gate driving integrated circuit for driving a gate line of the pixel matrix.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 9 to 13.

9 is a plan view illustrating a LOG type liquid crystal display device with a gate PCB removed according to an exemplary embodiment of the present invention.

The liquid crystal display shown in FIG. 9 mounts the data driver IC 64 to mount the data TCP 62 and the gate driver IC 60 connected between the data PCB 66 and the liquid crystal display panel 56. Bottom cover 82 electrically connected to the gate TCP 58 connected to the liquid crystal display panel 56, the ground line TGND formed to be exposed to the gate TCP 58, and the conductive tape 84. It is provided.

The liquid crystal display panel 56 is formed by bonding the thin film transistor array substrate 52 and the color filter array substrate 54 with the liquid crystal interposed therebetween. The liquid crystal display panel 56 is provided with liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 64 are connected to the data lines DL via the data TCP 62 and the data pad portion of the liquid crystal display panel 56. Here, the data drive ICs 64 are mounted in the IC area opened in the data TCP 62 or mounted on the base film of the data TCP 62 in a COF manner. The data drive ICs 64 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 64 supply data control signals, pixel data, and power signals from a timing controller (not shown) and a power supply (not shown) on the main PCB (not shown) via the data PCB 66. Will receive.

The gate drive ICs 60 are connected to the gate lines GL via the gate TCP 58 and the gate pad portion of the liquid crystal display panel 56. Here, the gate drive ICs 60 are mounted in the IC region opened at the gate TCP 58 or mounted on the base film of the gate TCP 58 in a COF manner. The gate drive ICs 60 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 60 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing controller (not shown) and power supply (not shown) are supplied to the data TCP 62 via the data PCB 66. Gate control signals and power signals supplied through the data TCP 62 are supplied to the gate TCP 58 via the LOG signal line group 76 formed in the edge region of the thin film transistor array substrate 52. Gate control signals and power signals supplied to the gate TCP 58 are input into the gate drive IC 60 through the input terminals of the gate drive IC 60 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 60 to be mounted on the next gate TCP 58 via the gate TCP 58 and the LOG signal line group 76. It is supplied to IC 60.

The LOG signal line group 76 is normally provided from a power supply unit (not shown) such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND, and a base driving voltage VCC. Supplied DC drive voltages; A signal line is provided to supply each of the gate control signals supplied from a timing controller (not shown), such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate enable signal GOE.

In order to minimize the line resistance of the LOG ground line LGND supplying the ground voltage among the LOG signal line group 76, the TCP ground line TGND formed on the gate TCP 58 has a conductive ground voltage ( The bottom cover grounded to GND), that is, the side cover 82 of the bottom cover is connected in parallel.

For connection with the side portion 82 of the bottom cover, the wiring width of the TCP ground line TGND formed in the gate TCP 58 is set relatively wide, and the solder resist film formed of the protective layer thereon is removed so that the TCP ground line is removed. (TGND) is exposed. For example, as shown in FIG. 9, the TCP ground lines TGND connected to the input terminal and the output terminal of the gate drive IC 60 are removed from the gate TCP 58 by a symmetrical solder resist film. Exposed through area 58a. A conductive tape 84 is applied to the inner surface of the side portion 82 of the bottom cover which comes into contact with the gate TCP 58 so as to be connected to the exposed TCP ground line TGND through the solder resist film removing region 58a. do. Accordingly, the bottom cover made of a metal material and grounded to the ground voltage GND is connected in parallel with the TCP ground line TGND.

Specifically, the gate TCP 58 attached to the thin film transistor array substrate 54 is bent along the side of the main supporter 90 supporting the liquid crystal display panel 56 as shown in FIGS. 10 and 11. It has a form that is attached to the back of the supporter (90). In this case, the gate drive IC 60 mounted on the gate TCP 58 is located at the side of the main supporter 90. The exposed area 58a of the TCP ground line TGND connected to the LOG ground line (not shown) of the thin film transistor array substrate 54 is located at the lower side of the gate drive IC 60. A side portion 82 protruding from the bottom cover 80 surrounding the rear portion of the main supporter 90 is attached to the exposed area 58a of the TCP ground line TGND through the conductive tape 84. The top case 100 is seated along the side surface at the upper side of the liquid crystal display panel 56. In this case, the exposed TCP ground line TND and the side portion 82 of the bottom cover 80 are firmly attached between the side portions 82 of the bottom cover 80 overlapping the side portions of the top case 100. A support pad 102 is further inserted. Here, the main supporter 90 includes a backlight (not shown), a light guide plate 92, and a plurality of optical sheets 94, which diffuse the incident light from the backlight to be uniformly dispersed and incident toward the liquid crystal display panel 56. And a liquid crystal display panel 56 positioned with the backlight unit including the upper and lower polarizing plates 96 and 98 on the backlight unit.

As described above, in the LOG type liquid crystal display according to the exemplary embodiment of the present invention, the LOG ground line LGND is electrically conductive through the TCP ground line TGND and is parallel to the bottom cover 80 grounded to the ground voltage GND. As it is connected, its line resistance is significantly reduced. As the line resistance of the LOG ground line LGND is minimized, horizontal streaks or spots caused by the line resistance of the LOG signal lines can be minimized as described above. As the line resistance of the LOG ground line LGND is minimized, the swing voltage of the common voltage VCOM and the gate low voltage VGL according to the transition magnitude of the pixel signal is changed by the line resistance of the LOG ground line LGND. The increase can be prevented. As a result, it is possible to minimize the greenish and horizontal crosstalk due to the increase in the swing voltage of the common voltage VCOM and the gate low voltage VGL.

12 and 13 illustrate a plan view and an exploded perspective view of a portion of a LOG type liquid crystal display according to another exemplary embodiment of the present invention.

The LOG type liquid crystal display shown in FIGS. 12 and 13 has side portions 112 and 114 of the bottom cover 100 contacting the gate TCP 58 in contrast to the LOG type liquid crystal display shown in FIGS. 9 and 11. Except that the structure is provided with the same components except for the detailed description of the same components will be omitted.

The side portion 82 of the bottom cover 80 illustrated in FIGS. 9 and 11 protrudes along the side portion of the main supporter 90 in a continuous form. On the other hand, the side portion of the bottom cover 110 shown in FIGS. 12 and 13 has a first protrusion 112 protruding along the side portion of the main supporter 90 and a gate TCP 58 from the first protrusion 112. The second protrusion 114 protrudes only in the TCP ground line TGND exposed area 58a of the substrate. Here, the second protrusion 114 is in contact with the TCP ground line TGND through the conductive tape 116 applied to the inner surface thereof.

As such, even in a LOG type liquid crystal display according to another exemplary embodiment, the LOG ground line LGND is conductive with the TCP ground line TGND and is parallel to the bottom cover 110 grounded to the ground voltage GND. Since its line resistance is significantly reduced. As the line resistance of the LOG ground line LGND is minimized, horizontal streaks or spots caused by the line resistance of the LOG signal lines can be minimized as described above. As the line resistance of the LOG ground line LGND is minimized, the swing voltage of the common voltage VCOM and the gate low voltage VGL according to the transition magnitude of the pixel signal is changed by the line resistance of the LOG ground line LGND. The increase can be prevented. As a result, it is possible to minimize the greenish and horizontal crosstalk due to the increase in the swing voltage of the common voltage VCOM and the gate low voltage VGL.

As described above, the LOG type liquid crystal display according to the present invention allows the LOG ground line to be connected in parallel with the bottom cover, which is conductive and grounded to the ground voltage, through the ground line of the gate TCP, thereby remarkably increasing the line resistance of the LOG ground line. Can be reduced.

Accordingly, according to the LOG type liquid crystal display device according to the present invention, as the line resistance of the LOG ground line is minimized, horizontal streaks or spots caused by the line resistance of the LOG signal lines can be minimized.

In addition, according to the LOG type liquid crystal display according to the present invention, as the line resistance of the LOG ground line is minimized, the swing voltage of the common voltage and the gate low voltage according to the transition magnitude of the pixel signal is increased by the line resistance of the LOG ground line. Can be prevented. As a result, according to the LOG type liquid crystal display device according to the present invention, it is possible to minimize the greenish and horizontal crosstalk due to the increase of the swing voltage of the common voltage and the gate low voltage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A liquid crystal display panel having a pixel matrix and a line-on-glass type signal line group formed in an outer region of the pixel matrix to supply control signals and power signals; A tape carrier package mounted on an outer region of the liquid crystal display panel by mounting a driving integrated circuit for driving the pixel matrix; A main supporter supporting the liquid crystal display panel; A line-on-glass type comprising a bottom cover which is grounded with a ground voltage while surrounding the rear edge of the main supporter and connected in parallel with a ground line for supplying a ground voltage of the line-on-glass type signal line group. Liquid crystal display. The method of claim 1, The tape carrier package is And a second ground line connected in series with said line on glass type ground line and having a relatively wide wiring width and having a partially exposed area. The method of claim 2, The bottom cover is And a second ground line connected through the exposed area of the tape carrier package. The method of claim 3, wherein The bottom cover is A rear part surrounding the rear part of the main supporter; And a side portion protruding from the back portion along the side portion of the main supporter which the tape carrier package surrounds and contacting the second ground line. The method of claim 4, wherein And a conductive tape applied along a side surface of the bottom cover and attached to the second ground line of the tape carrier package. The method of claim 3, wherein The bottom cover is A rear part surrounding the rear part of the main supporter; A first protrusion protruding from the rear portion along a side portion of the main supporter wrapped by the tape carrier package; And a side portion including a second protrusion that protrudes further from the first protrusion and contacts the second ground line. The method of claim 6, And a conductive tape applied to the second protrusion and attached to the second ground line of the tape carrier package. The method according to claim 4 or 6, A top case surrounding an edge region of the liquid crystal display panel and a side portion of the main supporter; And a support pad for firmly contacting the second ground line and the bottom cover side portion between the side portion of the bottom cover overlapping the side portion of the top case. . The method of claim 1, The tape carrier package is And a gate driving integrated circuit for driving the gate lines of the pixel matrix.

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