KR100898792B1 - LCD Display - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof capable of improving dot crosstalk by compensating gamma voltage in N-dot inversion.

The present invention includes a liquid crystal panel including a plurality of liquid crystal cells formed at intersections of gate lines and data lines, the gate driving signal line being directly formed on a substrate, a data driver for driving the data lines, and driving the gate lines. A gate driver, a gamma voltage unit supplying gamma voltages having different voltage levels to the data driver, a power supply unit supplying the gate driving signal to the gate driver and supplying driving power to the data driver and the gamma voltage And a gamma voltage compensator for compensating the gamma voltage by using the gate driving signal.

By such a configuration, the present invention improves image quality by compensating gamma voltage using the swing voltage of the gate low voltage, thereby improving the crosstalk by equalizing the difference in the charge value of the liquid crystal cell by the voltage variation of the gate low voltage line. You can. In addition, the present invention can improve the image quality by compensating the gamma voltage using the swing voltage of the voltage of the common voltage to improve the crosstalk by equalizing the difference in the charge value of the liquid crystal cell due to the swing voltage of the common voltage.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF}             

1 is a plan view showing a line-on-glass type liquid crystal display device.

FIG. 2 is a diagram for describing a horizontal stripe phenomenon in the liquid crystal display shown in FIG. 1.

3 is a view showing a specific pattern causing greenish in the conventional liquid crystal display.

4A and 4B are diagrams showing swing widths of a common voltage and a gate low voltage signal due to a specific pattern shown in FIG. 3;

5 is a view for explaining a greenish phenomenon due to the swing of the common voltage shown in FIGS. 4A and 4B.

FIG. 6 illustrates a specific pattern including a window causing horizontal crosstalk in a conventional liquid crystal display. FIG.

FIG. 7 illustrates a comparison between swing widths of a common voltage and a gate low voltage signal in a section including the window region of FIG. 6 and a section not including the window region.

FIG. 8 is a view for explaining a horizontal crosstalk phenomenon caused by the swing of the common voltage shown in FIG.                 

9 is a block diagram schematically illustrating a liquid crystal display according to a first embodiment of the present invention.

FIG. 10 is a diagram illustrating a gamma compensator illustrated in FIG. 9. FIG.

FIG. 11 is a view showing a specific pattern causing greenish in the liquid crystal display; FIG.

12A and 12B are diagrams showing the swing widths of the common voltage and the gate low voltage signal due to the specific pattern shown in FIG.

FIG. 13 is a view for explaining a horizontal crosstalk phenomenon caused by the swing of the common voltage shown in FIG.

FIG. 14 is a diagram illustrating a comparison of swing widths of a common voltage and a gate low voltage signal in a section including a window region illustrated in FIG. 11 and a section including no window region; FIG.

FIG. 15 is a view for explaining a horizontal crosstalk phenomenon caused by the swing of the common voltage shown in FIG.

16 is a block diagram schematically illustrating a liquid crystal display according to a second embodiment of the present invention.

FIG. 17 is a diagram illustrating a gamma compensator illustrated in FIG. 16. FIG.

<Description of Symbols for Main Parts of Drawings>

2: thin film transistor array substrate 4: color filter array substrate

6, 102, 202: liquid crystal panel 8: gate TCP

10: gate drive IC 12: data TCP                 

14: data drive IC 16: data PCB

18: FPC 20: Main PCB

22: timing control unit 24: power supply unit

26: LOG signal line group 32: horizontal line

104, 204: data driver 106, 206: gate driver

108,208: gamma voltage unit 110,210: power supply unit

120, 220: gamma compensation unit 122, 222: timing control unit

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving dot crosstalk by compensating gamma voltage in N-dot inversion.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel displays an image by adjusting the light transmittance of the liquid crystal cells according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal panel and the driving circuits of the driving circuits. And a power supply unit supplying power signals required for driving.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP by a chip on film (COF) method, and electrically connected to a liquid crystal panel by a tape automated bonding (TAB) method. Is connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub-PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

The drive ICs mounted on the liquid crystal panel in the COG method are control signals and pixels from the timing controller mounted on the main PCB through line on glass (LOG) signal lines formed on the FPC and the liquid crystal panel. Power signals from the data and power supplies are supplied.

Recently, even when the drive ICs are connected to the liquid crystal panel via TCP, the LOG type signal lines are adopted to eliminate the PCB, thereby making the liquid crystal display device even thinner. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed on the liquid crystal panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied. In this case, the gate control signals and the gate power signals supplied to the gate drive IC are distorted by the line resistances of the LOG signal lines, thereby causing a problem that the quality of the image displayed on the liquid crystal panel is degraded.

In detail, the LOG type liquid crystal display device in which the gate PCB is removed includes a main PCB 20 including a timing controller 22 and a power supply unit 24 and a main PCB (FPC 22) as shown in FIG. 1. The data PCB 16 connected to the 20 and the data driver IC 14 are mounted to connect the data TCP 12 and the gate driver IC 10 connected between the data PCB 16 and the liquid crystal panel 6. It is provided with the gate TCP 8 mounted and connected to the liquid crystal panel 6. As shown in FIG.

The liquid crystal panel 6 is formed by bonding the thin film transistor array substrate 2 and the color filter array substrate 4 to each other with a liquid crystal interposed therebetween. The liquid crystal panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal panel 6. The data drive ICs 14 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 18. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage signal VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate gate control signals and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 are supplied to the data TCP 12 via the FPC 18 and the data PCB 16. do. Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via the LOG signal line group 26 formed in the edge region of the thin film transistor array substrate 2. Gate control signals and power signals supplied to the gate TCP 12 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10, and the gate drive mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26. It is supplied to the IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 such as the gate low voltage signal VGL, the gate high voltage VGH, the common voltage Vcom, the ground voltage GND, and the base driving voltage VCC. Supplied DC drive voltages; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

The LOG signal line group 26 is formed in a fine pattern by using the same gate metal layer as the gate lines in a limited pad region of the thin film transistor array substrate 2. Further, as the LOG signal line group 26 is contacted with the gate TCP 8 through ACF bonding, the contact portion A with the gate TCP 8 increases, resulting in a large contact resistance. Accordingly, the LOG signal line group 26 has a larger line resistance than the signal lines of the conventional gate PCB. Due to the line resistance, the gate control signals GSP, GSC, and GOE transmitted through the LOG signal line group 26 and the power signals VGH, VGL, VCC, GND, and Vcom are distorted, thereby causing horizontal stripes, spots, and the like. The deterioration of image quality such as crosstalk of the dot pattern, greenish, etc. becomes worse.

For example, the LOG signal line groups 26 that supply the gate control signals GSP, GSC, GOE and power signals VGH, VGL, VCC, GND, Vcom are gated as shown in FIG. The first to fourth LOG signal line groups LOG1 to LOG4 are connected to each other between the TCPs 8. Each of the first to fourth LOG signal line groups LOG1 to LOG4 has a line resistance (aΩ, bΩ, cΩ, dΩ) that is proportional to the line length, and passes through the gate TCP 8 and the gate drive IC 10. Are connected in series. Due to the first to fourth LOG signal line groups LOG1 to LOG4, gate control signals GSP, GSC, and GOE input to each gate drive IC 10 and power signals VGH, VGL, VCC, GND, Level difference between Vcom). As a result, a luminance difference is generated between the horizontal line blocks A to D driven by the different gate drive ICs 10, resulting in horizontal stripes 32.

Specifically, the first gate drive IC 10 is provided with the first line resistance aΩ of the first LOG signal line group LOG1, and the second gate drive IC 10 is provided with the first and second LOG signal line groups. Due to the first and second line resistances aΩ + bΩ of LOG1 and LOG2, the third gate drive IC 10 includes the first to third of the first to third LOG signal line groups LOG1 to LOG3. By the line resistance aΩ + bΩ + cΩ, the fourth gate drive IC 10 has the first to fourth line resistances aΩ + bΩ + cΩ + of the first to fourth LOG signal line groups LOG1 to LOG4. The gate control signals GSP, GSC, and GOE, which are dropped by d ?, and the power signals VGH, VGL, VCC, GND, and Vcom are supplied. Accordingly, as the difference occurs between the gate signals VG1 to VG4 supplied to the gate lines of the first to fourth horizontal blocks A to D driven by different gate drive ICs 10, the horizontal Horizontal stripes 32 are generated between the line blocks A to D. FIG.                         

In addition, when a pattern in which black gray and 31 gray are alternated pixel by pixel is displayed on the liquid crystal panel driven by the dot inversion method as illustrated in FIG. 3, the data size of the transition between adjacent pixels is not canceled. As shown in FIG. 4B, the gate low voltage signal VGL and the common voltage Vcom are supplied by the parasitic capacitor. 4A and 4B show the common voltage Vcom and gate low voltage signal VGL waveforms swinged by parasitic capacitors when the black gray signal and the 31 gray signal are supplied to a specific data line in a dot inversion manner. will be. Here, it can be seen that the common voltage Vcom and the gate low voltage signal VGL swing with the same phase as the black gray signal having a relatively large voltage.

As a result, as shown in FIG. 5, when the black pixel signal is supplied to each of R1, G1, and B1 shown in FIG. 3 and the pixel signal of 31 gray is supplied to each of R2, G2, and B2, it swings along the black pixel signal. Due to the common voltage Vcom, the pixel signal charging values VG1, VR2, and VB2 of the pixel signal charging values VR1, VG1, and VB2 of R1, B1, and G2 become smaller. Accordingly, the G1, R2, and B2 pixels appear relatively bright. R1 and B1 supplied with the black pixel signal cannot be detected by the naked eye, so only the G2 pixel supplied with 31 gray appears to be bright, causing a greenish phenomenon.

As shown in FIG. 6, when a pattern in which 31 grays and black grays alternate in sub pixel units is displayed on a liquid crystal panel and a window W displaying the same gray is displayed in a specific area, the window area W is displayed. Since the same gray is displayed, the pixel signal transition size between adjacent pixels cancels out. Accordingly, as shown in FIG. 7, the swing width of the gate low voltage signal VGL and the common voltage Vcom in the T2 section including the window region W does not include the window region W. It becomes smaller than the T1 section. Therefore, the driving value of the pixels in the T2 section including the window area W and the T1 section not included in the window area W are changed.

Specifically, as shown in FIG. 8, when the lines R1, G1, and B1 are examined, except for the G1 line (not visually sensed) to which the black pixel signal is supplied, the lines R1 and B1 are charged in the period T1 (VR1, VB1). It can be seen that the charge amounts VR2 and VB2 in the T2 section are smaller. As a result, horizontal crosstalk may be generated in which pixels driven in the T2 section including the window region W appear relatively brighter than pixels driven in the T1 section including the window region W. FIG.

As such, the swing voltage of the common voltage Vcom and the gate low voltage signal VGL according to the transition size of the pixel signal is induced to the ground line forming the current path. Accordingly, the swing width of the common voltage Vcom and the gate low voltage signal VGL is further increased by the relatively large resistance component of the LOG signal line supplying the ground voltage, so that the above-described greenish and horizontal crosstalk phenomena It becomes clearer.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of improving dot crosstalk by compensating gamma voltage in N-dot inversion.

In order to achieve the above object, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel including a plurality of liquid crystal cells formed at intersections of gate lines and data lines, and a gate driving signal line directly formed on a substrate. A data driver for driving data lines, a gate driver for driving the gate lines, a gamma voltage unit for supplying gamma voltages having different voltage levels to the data driver, and supplying the gate driving signal to the gate driver; In addition, the data driver and the power supply for supplying a driving power to the gamma voltage, and a gamma voltage compensation unit for compensating the gamma voltage by using the gate driving signal.

In the liquid crystal display, the gate driving signal is a gate low voltage signal.

The gamma voltage compensator may include a gate driving signal line connected between the power supply unit and the gate driver and a plurality of capacitors connected between the gamma voltage unit.

In the liquid crystal display, each of the plurality of capacitors may be connected to the gate driving signal line in common and to each of the output lines of the gamma voltage unit.                     

The gamma voltage compensator in the liquid crystal display may compensate for the gamma voltage by a capacitive capacitor between the gate driving signal and the capacitor.

An LCD according to an exemplary embodiment of the present invention includes a liquid crystal panel including a plurality of liquid crystal cells formed at intersections of gate lines and data lines, and a gate driving signal line is directly formed on a substrate, and a data driver driving the data lines. And a gate driver for driving the gate lines, a gamma voltage unit for supplying gamma voltages having different voltage levels to the data driver, the gate driver signal and the data driver and gamma voltage. And a gamma voltage compensator for compensating the gamma voltage using the common voltage output from the liquid crystal panel and supplying a driving power to the liquid crystal panel.

In the liquid crystal display, the gamma voltage compensator includes a plurality of capacitors connected between the common voltage output line of the liquid crystal panel and the gamma voltage part.

In the liquid crystal display, each of the plurality of capacitors may be connected to the common voltage output line in common and to each of the output lines of the gamma voltage unit.

In the liquid crystal display, the gamma voltage compensator compensates for the gamma voltage by a capacitive capacitor between the common voltage and the capacitor.                     

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes generating a gate driving signal supplied to gate lines of a liquid crystal panel; Generating a plurality of gamma voltages; Compensating the plurality of gamma voltages using the gate driving signal; And converting digital data into an analog data signal using the compensated gamma voltages and supplying the digital data to data lines of the liquid crystal panel.

In the driving method, the gate driving signal is a gate low voltage signal.

In the driving method, the gamma voltages are compensated by coupling with the gate driving signal.

A method of driving a liquid crystal display according to an exemplary embodiment of the present invention includes supplying a common voltage to a liquid crystal panel, and generating a plurality of gamma voltages; Compensating for the plurality of gamma voltages using the common voltage; And converting digital data into an analog data signal using the compensated gamma voltages and supplying the digital data to data lines of the liquid crystal panel.

In the driving method, the gamma voltages are compensated by coupling with the common voltage output from the liquid crystal panel.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 9 to 17.

9, the liquid crystal display according to the first exemplary embodiment of the present invention includes a liquid crystal panel 102, a data driver 104 for driving data lines DL of the liquid crystal panel 102, and a liquid crystal display. A gate driver 106 for driving the gate lines GL of the panel 102, a timing controller 122 for controlling driving timing of the data and gate drivers 104 and 106, and a drive of the liquid crystal display device; The power supply unit 110 for generating a driving voltage required for the operation, the gamma voltage unit 108 for supplying the gamma voltage to the data driver 104, and the gate low voltage signal VGL supplied from the power supply unit 110. The gamma compensation unit 120 compensates for the gamma voltage output from the gamma voltage unit 108.

The power supply unit 110 uses driving voltages (gate high voltage VGL), gate low voltage signal VGH, reference gamma voltage, and the like required for driving the liquid crystal display using a voltage input from a system power supply unit (not shown). The common voltage Vcom is generated and supplied to the timing controller 122, the data driver 104, the gate driver 106, the gamma voltage unit 108, and the like.

The liquid crystal panel 102 is a thin film transistor TFT formed at an intersection of a plurality of gate lines GL and a plurality of data lines DL, and a liquid crystal connected to the thin film transistor TFT and arranged in a matrix form. With cells. The thin film transistor TFT supplies video data from the data line DL to the liquid crystal cell in response to the gate pulse from the gate line GL. Since the liquid crystal cell is composed of a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor, the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc.

The timing controller 122 relays the video data R, G, and B from the graphics card and supplies the data driver 104 to the data driver 104. In addition, the timing controller 122 generates control signals such as timing signals and polarity inversion signals for controlling the timing of the data and the gate drivers 104 and 106 in response to the control signal from the graphics card.

In addition, the timing controller 122 supplies a gate start pulse GSP to the gate driver 106 to sequentially drive the gate lines GL. In this way, the polarity inversion signal POL of the unit of the vertical synchronization signal is set in the high section of the gate start pulse GSP supplied to the valid data section of the data enable signal DE from the timing controller 122. It changes from polarity (or negative) to negative (or positive).

The gate driver 106 sequentially supplies the gate high voltage signal VGH to the gate lines GL according to the gate start pulse GSP from the timing controller 122, and supplies the gate low voltage signal signal VGL. Supply.

The gamma voltage unit 108 receives the reference gamma voltage from the power supply unit 110 to generate the positive and negative gamma voltages set in advance to have different voltage levels according to the voltage level of the video signal. The gamma voltages generated in the gamma voltage unit 108 are supplied to the data driver 104.

The data driver 104 converts the R, G, and B data signals from the timing controller 122 into analog signals so that one horizontal line of video is provided for each horizontal period in which the gate high voltage signal is supplied to the gate lines GL. The signal is supplied to the data lines DL. The digital-to-analog converter of the data driver 104 is supplied with gamma voltages from the gamma voltage unit 108. The video signal added with the gamma voltages having positive and negative gamma voltages is selected by the polarity control signal POL from the timing controller 122, and the data is transmitted in response to the source output enable signal SOE signal. Supply to the lines DL.

The gamma compensator 120 includes n capacitors C1 to Cn connected to each of the gamma voltage output lines GMA1 to GMAn of the gamma voltage unit 108, as shown in FIG. 10. One end of the capacitors C1 to Cn is commonly connected to the gate low voltage signal VGL output line of the power supply 110, and may have different capacitance values. At this time, when the data transition of the data line DL increases in the gate low voltage signal VGL output line, the swing voltage of the gate low voltage signal VGL due to capacitive coupling between the source electrode and the gate electrode of the thin film transistor. Is output. Accordingly, each of the n capacitors C1 to Cn is output from the gamma voltage unit 108 by capacitive coupling with the gate low voltage signal VGL supplied to the gate low voltage signal VGL output line. To compensate the voltages. Accordingly, the gamma voltages output from the gamma voltage unit 108 through the gamma voltage output lines GMA1 to GMAn are the swing voltage of the gate low voltage signal VGL and the capacitance of each of the n capacitors C1 to Cn. It is swinged to have the same phase as the swing voltage by the gender coupling. The gamma compensation unit 120 swings the gamma voltages output from the gamma voltage unit 108 to have the same phase as the swing voltage of the gate low voltage signal VGL. To compensate for the fluctuations in voltage.

In detail, as shown in FIG. 11, when a pattern in which black gray and 31 gray are alternately displayed in pixel units is displayed on a liquid crystal panel driven by a dot inversion method, the capacitive coupling by the gamma compensator 110 is applied. The data size transitioned between adjacent pixels is canceled out so that the gate low voltage signal VGL and the common voltage Vcom are supplied by the parasitic capacitor as shown in FIGS. 12A and 12B. 12A and 12B illustrate a waveform of a common voltage Vcom and a gate low voltage signal VGL swinged by a parasitic capacitor and gamma compensation when a black gray signal and a 31 gray signal are supplied to a specific data line in a dot inversion manner. The gamma voltages swinged by the capacitive coupling of the unit 120 are illustrated. Here, the swing of the gate low voltage signal VGL is coupled to the gamma voltage output lines GMA1 to GMAn to the liquid crystal cell generated by the swing of the common voltage Vcom due to the swing of the gate low voltage signal VGL. It can be seen that the charging deviation is compensated using the gamma voltages swinging.

As a result, as shown in FIG. 13, when the black pixel signal is supplied to each of R1, G1, and B1 shown in FIG. 11 and the pixel signal of 31 gray is supplied to each of R2, G2, and B2, it swings along the black pixel signal. Since the gamma voltages due to the common voltage Vcom are swinged, the pixel signal charging values VR1, VG1, and VB1 of R1, G1, and B1 are the same. Therefore, the charging values of the R1, B1 supplied with the black pixel signal, and the G1 pixel supplied with the 31 gray are the same, and thus the greenish phenomenon and the crosstalk, in which the G1 pixel is relatively bright, do not occur.

As shown in FIG. 14, when a pattern in which 31 gray and black gray are alternately displayed in sub-pixel units and a window displaying the same gray in a specific area is displayed on the liquid crystal panel, the same gray is displayed in the window area. The pixel signal charging value between adjacent pixels becomes equal. Accordingly, the swing width of the gate low voltage signal VGL and the common voltage Vcom in the T2 section including the window region W is the same as the T1 section without the window region W. Therefore, in the driving cycle in the pixels driven in the T2 section including the window region W and in the T1 section not included in the window region W, the charging value of the charging value of the pixels is the same.

Specifically, as shown in FIG. 15, when the lines R1, G1, and B1 are looked at, except for the G1 line (not visually detected) to which the black pixel signal is supplied, the lines R1 and B1 are charged in the T1 section VR1 and VB1. It can be seen that the charge amounts VR2 and VB2 are equal to each other in the T2 section. As a result, horizontal crosstalk does not occur as in the prior art, in which pixels driven in the T2 section including the window region W appear relatively brighter than pixels driven in the T1 section not including the window region W. Will not.

Referring to FIG. 16, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 202, a data driver 204 for driving data lines DL of the liquid crystal panel 202, and a liquid crystal panel ( The gate driver 206 for driving the gate lines GL of the 202, the timing controller 222 for controlling the driving timing of the data and the gate drivers 204 and 206, and the driving necessary for driving the liquid crystal display device. The common voltage output from the power supply unit 210 for generating the driving voltage, the gamma voltage unit 208 for supplying the gamma voltage to the data driver 204, and the common voltage output line 230 of the liquid crystal panel 202. And a gamma compensator 220 to compensate the gamma voltages output from the gamma voltage unit 208 using Vcom.

The power supply unit 210 uses driving voltages (gate high voltage VGL), gate low voltage signal VGH, reference gamma voltage, and the like necessary for driving the liquid crystal display using a voltage input from a system power supply unit (not shown). The common voltage Vcom is generated and supplied to the timing controller 222, the data driver 204, the gate driver 206, the gamma voltage unit 208, and the like.

The liquid crystal panel 202 is a thin film transistor TFT formed at an intersection of a plurality of gate lines GL and a plurality of data lines DL, and a liquid crystal connected to the thin film transistor TFT and arranged in a matrix form. With cells. The thin film transistor TFT supplies video data from the data line DL to the liquid crystal cell in response to the gate pulse from the gate line GL. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc.

The timing controller 222 relays the video data (R, G, B) from the graphics card and supplies it to the data driver 204. In addition, the timing controller 222 generates control signals such as timing signals and polarity inversion signals for controlling the timing of the data and the gate drivers 204 and 206 in response to the control signal from the graphics card.

In addition, the timing controller 222 supplies a gate start pulse GSP to the gate driver 206 for sequentially driving the gate lines GL. In this way, the polarity inversion signal POL of the unit of the vertical synchronization signal is set in the high section of the gate start pulse GSP supplied to the valid data section of the data enable signal DE from the timing controller 222. It changes from polarity (or negative) to negative (or positive).

The gate driver 206 sequentially supplies the gate high voltage signal VGH to the gate lines GL according to the gate start pulse GSP from the timing controller 222, and supplies the gate low voltage signal signal VGL. Supply.

The gamma voltage unit 208 receives the reference gamma voltage from the power supply unit 210 to generate the predetermined positive and negative gamma voltages to have different voltage levels according to the voltage level of the video signal. The gamma voltages generated in the gamma voltage unit 208 are supplied to the data driver 204.

The data driver 204 converts the R, G, and B data signals from the timing controller 222 into analog signals so that one horizontal line corresponds to one horizontal line of video every one horizontal period when the gate high voltage signal is supplied to the gate lines GL. The signal is supplied to the data lines DL. The digital-to-analog converter of the data driver 204 is supplied with gamma voltages from the gamma voltage unit 208. In this way, the video signal having the added gamma characteristics with the positive and negative gamma voltages is selected by the polarity control signal POL from the timing controller 222 and responds to the source output enable signal SOE signal. Supply to the data lines DL.

The gamma compensator 220 includes n capacitors C1 to Cn connected to each of the gamma voltage output lines GMA1 to GMAn of the gamma voltage unit 208, as shown in FIG. 17. One end of the capacitors C1 to Cn is commonly connected to the common voltage output line 230 of the liquid crystal panel 202 and have different capacitance values. At this time, when the data transition of the data line DL increases, the common voltage output line 230 outputs the swing voltage of the common voltage Vcom generated by capacitive coupling between the video data and the common voltage Vcom. do. Accordingly, each of the n capacitors C1 to Cn compensates the gamma voltages output from the gamma voltage unit 108 by capacitive coupling with the common voltage Vcom supplied to the common voltage output line 230. do. Accordingly, as shown in FIGS. 12A and 12B, the gamma voltages output from the gamma voltage unit 108 through the gamma voltage output lines GMA1 to GMAn are the swing voltage of the common voltage Vcom and the n capacitors. (C1 to Cn) are swinged to have the same phase as the swing voltage by each capacitive coupling. The gamma compensation unit 120 swings the gamma voltages output from the gamma voltage unit 108 to have the same phase as the swing voltage of the common voltage Vcom, thereby changing the voltage of the video data by the common voltage Vcom. To compensate.

 As described above, the liquid crystal display according to the exemplary embodiment of the present invention compensates the gamma voltage by using the swing voltage of the gate low voltage to equalize the difference in the charge value of the liquid crystal cell by the voltage variation of the gate low voltage line. Image quality can be improved by improving crosstalk. In addition, the present invention can improve the image quality by compensating the gamma voltage using the swing voltage of the voltage of the common voltage to improve the crosstalk by equalizing the difference in the charge value of the liquid crystal cell due to the swing voltage of the common voltage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (14)

A liquid crystal panel comprising a plurality of liquid crystal cells formed at intersections of the gate lines and the data lines, the gate driving signal lines being directly formed on the substrate; A data driver for driving the data lines; A gate driver for driving the gate lines; A gamma voltage unit supplying gamma voltages having different voltage levels to the data driver; A power supply unit supplying the gate driving signal to the gate driver and supplying driving power to the data driver and the gamma voltage; And a gamma voltage compensator for compensating the gamma voltage using the gate driving signal. The method of claim 1, And the gate driving signal is a gate low voltage signal. The method of claim 1, And the gamma voltage compensation unit includes a gate driving signal line connected between the power supply unit and the gate driver and a plurality of capacitors connected between the gamma voltage unit. The method of claim 3, wherein And each of the plurality of capacitors is commonly connected to the gate driving signal line and is connected to each of the output lines of the gamma voltage unit. The method of claim 3, wherein And the gamma voltage compensator compensates for the gamma voltage by a capacitive capacitor between the gate driving signal and the capacitor. A liquid crystal panel comprising a plurality of liquid crystal cells formed at intersections of the gate lines and the data lines, the gate driving signal lines being directly formed on the substrate; A data driver for driving the data lines; A gate driver for driving the gate lines; A gamma voltage unit supplying gamma voltages having different voltage levels to the data driver; A power supply unit supplying the gate driving signal to the gate driving unit, supplying driving power to the data driving unit and the gamma voltage, and supplying a common voltage to the liquid crystal panel; A gamma voltage compensator for compensating the gamma voltage by using the common voltage output from the liquid crystal panel; And the gamma voltage compensator comprises a plurality of capacitors connected between the common voltage output line of the liquid crystal panel and the gamma voltage part. delete The method of claim 6, And each of the plurality of capacitors is commonly connected to the common voltage output line and to each of the output lines of the gamma voltage unit. The method of claim 6, And the gamma voltage compensator compensates for the gamma voltage by a capacitive capacitor between the common voltage and the capacitor. Generating a gate driving signal supplied to gate lines of the liquid crystal panel; Generating a plurality of gamma voltages; Compensating the plurality of gamma voltages using the gate driving signal; And converting the digital data into an analog data signal using the compensated gamma voltages and supplying the digital data to the data lines of the liquid crystal panel. The method of claim 10, And the gate driving signal is a gate low voltage signal. The method of claim 10, And the gamma voltages are compensated by the coupling with the gate driving signal. Supplying a common voltage to the liquid crystal panel; Generating a plurality of gamma voltages from the gamma voltage portion; Outputting a common voltage from the liquid crystal panel; Compensating for the plurality of gamma voltages using a common voltage output from the liquid crystal panel; Converting the digital data into an analog data signal using the compensated gamma voltages and supplying the digital data to data lines of the liquid crystal panel; Compensating the plurality of gamma voltages Coupling the gamma voltages to the common voltage using a plurality of capacitors connected between the common voltage output line to which the common voltage is output and the gamma voltage unit. . delete

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