JPS626361A - Data transfer method between multiple processors - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a plurality of local area networks (L
LAN (local area network, hereinafter abbreviated as LAN) is connected to multiple processors via multiple microprocessors, and in particular multiple processors that transfer data through 2-port memory provided for each processor. related to inter-data transfer methods.

[Background of the invention]

Conventionally, in a multi-processor system such as a LAN interconnection device or a packet switching device, a common memory that can be accessed from each processor is connected to a common bus that connects each processor, and reception data for each destination is stored in this common memory. There was a method in which an area was provided and data communication between processors was performed via a common memory. Japanese Patent Publication No. 58-9794
See Publication No. 4.

However, such a conventional method has a problem in that it is necessary to use the common bus twice for data transfer twice: writing data to the common memory and reading data from the common memory. Additionally, if the number of processors changes, the number of reception areas in the common memory must be changed, and furthermore, there is no special consideration for broadcast data transfer, and individual data transfers are required for broadcast data transfer. is necessary, and its overhead increases in proportion to the number of processors (
There were problems such as. However, when considering a LAN interconnection device, (1) when a processor receives a broadcast transfer frame (a frame sent from any station on the LAN to all other stations) from the LAN, the LAN interconnection (2) When a processor receives a transfer frame from a LAN and the destination LAN of this frame is unknown (generally, if the destination LAN in the frame is The destination address contains the station address, and L
(Because it does not contain AN identification information, the destination LAN may be unknown), and a broadcast data transfer function is required to forward this frame to all LANs. It is essential to have a transfer function.

[Purpose of the invention]

An object of the present invention is to solve the above-mentioned problems in the prior art, to reduce the number of accesses to a common bus, and to change the number of processors and broadcast data transfer. It is an object of the present invention to provide a data transfer method between multiple processors that allows easy data transfer and has improved processing capacity during LAN interconnection.

[Summary of the invention]

The present invention arose from consideration of the similarities between multiple processor systems and LANs. In a LAN, each node is independent, so adding nodes is relatively easy.

In addition, in broadcast communication, "broadcast" is written in the address part of the frame.
If you write this, each node will import it. More than L
The idea was to incorporate the features of AN into a LAN interconnection device consisting of a plurality of bus-coupled processors. The target multiple processor system has a configuration in which each processor is connected by a common bus, so all data exchanged between processors flows through the interface between each processor and the common bus. Become. Therefore, for broadcast data transfer, all processors need to take in the data on the bus, and in order to take in data on the data bus, the address on the address bus must indicate itself, so each processor We devised a method to make the corresponding memory addresses the same.

In view of the above, the present invention employs the following method. That is, a plurality of microprocessors (hereinafter simply referred to as processors) that connect a plurality of LANs and perform data transfer processing between the LANs, a local memory that has an area for storing programs that define the operation of the processors, and a work area; A local bus that connects the processor and local memory individually, and a
In a local area network interconnection device consisting of an interface circuit that performs interface processing with an AN and a common bus that interconnects each processor, a A 2-port memory for writing and reading through a bus is provided for each processor, a data receiving area is provided in each 2-port memory, and each data receiving area has a different address on the common bus, so that data between processors is In the case of transfer, the source processor is the 2nd processor of the destination processor.
Data is written to the address of the data reception area in the port memory through the common bus, and the transfer destination processor reads the contents of the data reception area in the two-port memory through the local bus. Furthermore, for broadcast data communication, a broadcast data reception area is provided in each 2-port memory, and each broadcast data reception area has the same address on the common bus, so that one processor can communicate with all other processors. When transferring broadcast data, the transfer source processor writes data to the address of the broadcast data reception area via the common bus, and each other processor reads the contents of the broadcast data reception area via the local bus. shall be.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment. The device of this embodiment has a configuration in which LAN connection processor modules LCP (#1 to #n), which are LAN compatible connection modules, are connected by a common bus CB (31).Each module LCP is connected to a processor CPU (1-a-n- a
), LAN:I:/Troller LC(l-d-n-
d), local memory LM (1-c-n-c) for storing programs and work data during program execution;
, 2, which is an area for data exchange with other modules LCP.
Point memo! JCM (1-b to n-b), 2-bot memory controller MC (l-
e~ne-e), bus interface unit BIU (1-f-
n-f).

FIG. 2 shows a memory map on the common bus CB+31. In this embodiment, the maximum data length is 256 bytes. The memory map on common bus CB (31 is QH-QF)
Broadcast data reception area up to FH (common to each LCP),
(100x m)H~((IOQ x m)H+QFF
H) Consists of CP#m data reception area. FIG. 3 shows a memory map seen from the LCP 9m. From the processor CPU(a), addresses on the common bus CB(3) can be seen as they are from addresses Q to 2FFFFH. However, when viewed from the processor CPU (a), the reception area on the common bus CB (3) becomes the transmission area. Up to 10000H-101FFH is the address of 2-port memory CM (bl) from the local bus side.In other words, 0H-FF from the common bus CB(3) side
Address H, (100X m)H~((100X m
)HQFFH) Address is 1000 from the local bus side
Address 0H~1QQFFH, l0100H-101F
Corresponds to FH address.

The operation of the embodiment will be explained. First, from LCP #1 to LCP
The case of transferring data to #2 will be described.

The processor CPU (1-a') of LCP @l receives data received from the connected LAN1 [local memory L
M(1-C)], and if it is recognized as data addressed to LCP #2, it writes this data to the data transmission area (addresses 200H to 2FFH) addressed to LCP #2. This data is written to the data receiving area in the LCP#2 boat memory (2-b) through the common bus CB (31).
) processes this data through the local bus (the above data is 10100H~1QI from the local bus).
(You can see it if it is at address FFH). After that, data is sent to the connected LAN2.

As the next operation example, broadcast data transfer will be described. L
It is assumed that data is transferred from CP #l to all other LCPs. When LCP$l receives broadcast data from LANI, it writes this data into the broadcast data transmission area (address Q, FFH). This data is written to the broadcast data reception area in the two-point memory CM of each LCP through the common bus CB (31).
), and sends it to each LAN.

If you want to actually execute the above operation, please follow the 3 steps below.
points need to be resolved.

(1) In the case of individual transfer, how do you check the availability of the receiving area of the other party's LCP?

(2) In the case of broadcast transfer, how to check the availability of the broadcast receiver IJ of each LCP?

(3) In the case of broadcast transfer, ACK (
An acknowledgment (affirmative response) is returned, but how should it be processed?

Hereinafter, one solution to the above three problems will be explained.

<For problem l> Provide F/E (Full/Empty) 7 lags in the receiving area. FIG. 4 shows the reception area when the F/E flag is provided. The first byte of the reception area is set as the F/E flag, and data is entered from the second byte onward.

Fig. 5 shows a flowchart of the transmission processing of the sending processor, and Fig.
The figure shows a flowchart of reception processing by the receiving processor. On the transmitting side, first, it is determined whether the F/E flag is 0 (zero) or not, and if it is not 0, it waits for it to become 0. When it becomes O, data is written to the receiving area and the F/E flag is set to 1. The receiving side recognizes reception when the F/E bit changes to 1, and processes the received data. After processing is completed, turn the F/E flag to O.
Make it.

<Regarding Problem 2> (Solution 1) A broadcast enable flag and a broadcast notification counter are provided in the broadcast data receiving area. FIG. 7 shows a flowchart of transmission processing by the processor on the broadcast data transmission side. On the transmitting side, first, it is determined whether the multicast flag is O or not, and if it is not O, it waits for it to become zero. If it becomes 0, set it to 1. This checking of 0 and setting to 1 is performed by check and set to avoid contention between processors. After setting the broadcast enable flag to 1, broadcast data is written, and then the broadcast counter is incremented. After incrementing the broadcast counter,
Wait for a certain amount of time. This fixed time is the time it takes for the receiving side to finish processing the broadcast data, and is a value determined at the time of system design. Thereafter, the broadcast enable flag is set to 0 to enable other broadcast transfers. On the receiving side, the broadcast counter is checked at regular intervals, and the reception of broadcast data is known from the change in the broadcast counter value. After that, the received data is processed.

(Solution 2) There are also solutions to problem 2 as follows.

A main processor is provided on the common bus CB(3), and a broadcast request flag and a broadcast enable flag are provided in the 2-port memory of each processor LCP. First, the broadcast data transmission source processor sets a broadcast request flag in its own 2-port memory. The main processor on the common bus searches for each broadcast request flag, and if the flag is set, sets the broadcast enable flag in this two-port memory. After setting the broadcast request flag, the source processor searches for the broadcast enable flag, and if the flag is set, it starts broadcast transfer.

When a certain period of time has elapsed after the end of the broadcast transfer, the source processor clears the broadcast enable flag and the broadcast request flag to notify the main processor of the end of the broadcast transfer. Of course, these flags can also be placed in a common memory provided on the common bus 3.

and the topic of the story 1. τ5 In the case of broadcast transfer, since writing is performed to multiple memories, multiple ACKs are returned from the memories. Those A
Since the CK is returned via the bus, when the first ACK is returned, the sending CPU determines that the ACK has been returned and ends the write cycle. Therefore,
In the case of broadcast transfer, the write cycle is terminated after a certain period of time rather than an ACK from the memory. This certain period of time is a value determined at the time of system design, taking into consideration the contention time in each 2-port memory.

FIG. 8 shows a circuit diagram for realizing the above. The circuit of FIG. 8 operates as follows - first, the CPU 101
Consider the case where the data is written to a location other than the broadcast area. C.P.
When U outputs the write address to AO%A, . . . and activates the address strobe AS, the address decoder 102 examines the address.

In this case, since writing is not to a broadcast area, the address detect station does not become active. Then, the AND gate 105 is selected from the two AND gates 104 and 105. In other words, when Ishita returns from the common bus, the CPU 101's λCπ-
becomes active. Next, consider the case of writing to the broadcast area. In this case, address detect becomes active because the address decoder 102 recognizes the address. In that case, the AND gate 104 is selected and the common bus ACK is ignored. AD is divided into two parts, one directly entering the AND gate 104 and the other entering the delay circuit 103. Delay circuit 103
In this case, the enable signal ■ is active, so
After a certain period of time, the input signal is sent to the output side. As a result, the ACK of the CPU 101 becomes active after a certain period of time. Note that when the enable signal EN becomes inactive, the delay circuit 103 does not perform a delay operation and immediately outputs the input to the output side.

FIG. 9 shows a time chart of various signals in the case of writing to the broadcast area. When AS becomes active, the minds from each memory become active, but are ignored because AD is active.

After a certain period of time from the time when AD becomes active, the CPU side becomes active due to the operation of the delay circuit. This makes the AS inactive and then each ACK,
, AD, ACK on the CPU side becomes inactive one after another. Next, the R/W becomes the read side and ends the write cycle.

So far, solutions to each of the three problems have been explained.

〔Effect of the invention〕

According to the present invention, (1) the common bus is only used once for data transmission between processors, which reduces data transfer time by about half; (2) the number of processors can be easily increased or decreased;
(3) L is flexible and has high processing power because data can be transferred to multiple parties at once without increasing overhead.
This has the effect that an AN interconnection device can be constructed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a memory map on the common bus in the embodiment, Fig. 3 is the same memory map (as seen from the CPU), and Fig. 4 is the configuration of the reception area of the embodiment. 5 is a flowchart of transmission processing in individual communication of the embodiment, FIG. 6 is a flowchart of reception processing, FIG. 7 is a flowchart of transmission processing in broadcast communication of the embodiment, and FIG. 8 is a flowchart of transmission processing in broadcast communication of the embodiment. ACK circuit diagram, Figure 9 is a time chart of each part signal in Figure 8. Explanation of symbols> LAN...Local area network CB +
31...Common bus LCP,...LAN connection processor CPU.
... Processor LC ... LAN controller LM ... Local memory CM ... 2-port memory BIU ... Bus interface unit 101 ...
CPU 102...address decoder 103...delay circuit

Claims (2)

[Claims] (1) Multiple microprocessors that connect multiple local area networks and perform data transfer processing between the local area networks, and a local memory that has an area for storing programs that define the operations of the processors and a work area. , a local bus that individually connects the processors and local memories, an interface circuit that is connected to the local bus and performs interface processing with the local area network, and a common bus that interconnects the processors. In a local area network interconnection device consisting of a bus and A data receiving area is provided in the data receiving area, and each data receiving area has a different address on the common bus.In the case of data transfer between processors, the transfer source processor is connected to the other processor's 2nd address.
Data is written to the address of the data reception area in the port memory through the common bus, and the transfer destination processor reads the contents of the data reception area in the 2-port memory through the local bus, thereby transferring data via the 2-port memory. A method for transferring data between multiple processors. (2) A broadcast data reception area is provided in each of the two-port memories, and the address on the common bus for each broadcast data reception area is the same, so that broadcast data is transferred from one processor to all other processors. When performing this, the transfer source processor writes data to the address of the broadcast data reception area through the common bus, and each other processor reads the contents of the broadcast data reception area through the local bus, and writes the data to the address of the broadcast data reception area via the 2-port memory. 2. A data transfer system between multiple processors according to claim 1, wherein the multi-processor data transfer is carried out in a multi-processor system.