JP2021002279A - Control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To transfer data between an arithmetic module and two or more sub arithmetic modules at the same time. A control system includes a connection unit to which an arithmetic module is connected and a bus associated with a plurality of sub-connection units to which a plurality of sub-arithmetic modules are connected. In the arithmetic module, the bus space includes two or more individual spaces, which are two or more spaces corresponding to two or more sub-connections, and a common space, which is a space common to two or more sub-connections. When two or more sub-arithmetic modules are connected to two or more sub-connection units, the arithmetic module corresponds to the single access that is to transfer data to or from any of the sub-arithmetic modules. Selectively perform the broadcast access using the individual space, which is the simultaneous data transfer between the two or more sub-operation modules, and the broadcast access using the common space. [Selection diagram] Fig. 1

Description

The present invention generally relates to control systems such as programmable controllers (PLCs) that control the operation of equipment and mechanical systems by sequence programs, and particularly to improved data transfer between arithmetic modules and sub-arithmetic modules.

Patent Document 1 (Japanese Unexamined Patent Publication No. 2004-362327) states that "in a distributed monitoring and control system in which a monitoring personal computer and a control PLC in a plant monitoring and control facility are connected by a network, a general-purpose monitoring personal computer is used for control. An information management file of the general-purpose PLC is provided, and an information automatic sweeping tool of the general-purpose PLC for control is provided in the general-purpose PLC for control, and information input to the general-purpose personal computer and process information of the general-purpose control PLC are input. A distributed monitoring and control system characterized by integrated management by general-purpose software. ”(See claim 1).

Patent Document 2 (Japanese Unexamined Patent Publication No. 2006-178818) states that "a real-time OS, a memory, an execution means for executing a ladder language program in synchronization with a motion control cycle, and both the ladder language program and the C language program". In a motion controller equipped with a microprocessor that operates, if the C language program loaded according to the project setting file of the engineering tool is a task type project, it is operated as a task of the real-time OS, and the C language program is a functional type. If it is a project, a motion controller is stored in the memory in a state where it can be called as a function from another task. ”(See claim 1).

Patent Document 3 (Japanese Unexamined Patent Publication No. 2017-27539) states that "a CPU module, one or more IO modules, and an external bus connecting both modules are provided, and the CPU module has an address space for each IO module. The IO module specifies an arbitrary address of, and the IO module increments or decrements the address from the specified arbitrary address to execute IO processing for a continuous address space in the IO module. Controller. ”(See claim 1).

Japanese Unexamined Patent Publication No. 2004-362327 Japanese Unexamined Patent Publication No. 2006-178818 Japanese Unexamined Patent Publication No. 2017-27539

Patent Document 1 states, "However, the conventional distributed monitoring and control system 41 includes operator displacement 50a to 50n, digital control devices 60a to 60n, transmission lines 52a to 52n, trunk transmission lines 42, transmission lines 61a to 61n, and the like. It is a dedicated device for each distributed monitoring and control system manufacturer, and it is expensive and incompatible with other manufacturers' products, so it is inferior in expandability, and with the recent improvement in the performance of general-purpose devices such as personal computers, it is also dedicated in terms of capacity. No general-purpose equipment is used, even though some are superior to the equipment. ”(See paragraph 0004).

The dedicated equipment for each distributed monitoring and control system manufacturer is a programmable logic controller, and in the background of such a device configuration, the programmable logic controller controls the I / O unit, etc., and is used for production in factories. Since it is connected to a device used for transportation or the like, if a delay occurs in control, the operation of the device or the like in the factory may become unstable or unexpected operation may occur. Therefore, the conventional programmable logic controller has been prevented from performing complicated processing. Similarly, the invention disclosed in Patent Document 1 is prevented from being complicatedly processed, and the control of the programmable logic controller is not affected by providing the information management file of the general-purpose programmable logic controller for control in the general-purpose personal computer for monitoring. It is disclosed to do so.

Therefore, Patent Document 1 does not consider performing information processing in the programmable logic controller.

In the problem column of Patent Document 2, there is also a problem that "because the ladder language application program and the C language application program operate on different microprocessors, the C language application program cannot be called as a function from the ladder language application. It is stated.

That is, Patent Document 2 aims at a ladder language application program calling a C language application program as a function on the same microprocessor.

Patent Document 3 discloses a method of performing high-speed continuous access to a continuous address space between a CPU module and an IO module. However, at the time of access, it is premised that the arithmetic module such as the CPU module and the sub arithmetic module such as the IO module have a one-to-one relationship. This is because the arithmetic module and the sub arithmetic module are connected to an external bus, and in general, 1: 1 communication is premised on the bus. On the other hand, a control system having an arithmetic module and a sub arithmetic module (for example, an industrial controller) is usually installed in a field such as a factory where a controlled device is present, but for application of edge computing or other reasons. In some cases, it may be desirable for the control system to process the data instead of sending the data acquired from the sensor or other device over the network to a remote system such as a cloud system. For example, in the control performed by the control system, high real-time performance is required in which a scan operation for reading or writing (acquiring or updating) the state of the controlled device must be performed within the scan time. Therefore, data in the control system is required. There may be cases where it is desirable to be processed. In such a case, if simultaneous data transfer between the arithmetic module and a plurality of sub arithmetic modules is realized, it is expected that the speed of data processing in the control system will be increased.

The present invention has been made in consideration of the above points, and an object of the present invention is to simultaneously transfer data between an arithmetic module and two or more sub arithmetic modules.

The control system includes a calculation module and a bus associated with a connection unit to which the calculation module is connected and a plurality of sub-connection parts which are a plurality of connection parts to which the plurality of sub-calculation modules are connected to each other. In the arithmetic module, the bus space includes two or more individual spaces, which are two or more spaces corresponding to two or more sub-connections, and a common space, which is a space common to two or more sub-connections. When two or more sub-calculation modules are connected to two or more sub-connection units, the arithmetic module corresponds to the single access that transfers data to or from any of the sub-operation modules. Selectively perform the broadcast access using the individual space, which is the simultaneous data transfer between the two or more sub-operation modules, and the broadcast access using the common space.

According to the present invention, it is possible to simultaneously transfer data between an arithmetic module and two or more sub arithmetic modules.

FIG. 1 is a configuration diagram of a programmable controller according to an embodiment of the present invention. FIG. 2 is a configuration diagram of an internal block of a BUS controller included in the sub CPU module. FIG. 3 is a time chart at the time of write access to a normal IO module. FIG. 4 is a time chart at the time of read access to a normal IO module. FIG. 5 is a time chart of high-speed continuous access to the sub CPU module at the time of writing. FIG. 6 is a time chart of high-speed continuous access at the time of reading to the sub CPU module. FIG. 7 is a flowchart showing the operation of the programmable controller (PLC). FIG. 8 is an image diagram showing the relationship between the address map of the external bus space of the CPU module and the slot selection signal. FIG. 9 is an image diagram showing a modified example of the relationship shown in FIG.

Hereinafter, examples of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a PLC according to an embodiment of the present invention.

This PLC has a CPU slot and two or more sub CPU slots. The CPU module 1 is mounted in the CPU slot, and the sub CPU module 2 is mounted in the sub CPU slot.

The CPU module 1 includes an MPU (MicroProcessor Unit) 11 that calculates a sequence program, a communication port 12 for communicating with peripheral devices such as a personal computer, and a ROM (Read Only Memory) 13 for storing a sequence program and a system program. Data transfer (for example, DMA (Direct Memory Access)) between a RAM (Random Access Memory) 14 for storing data used for calculation of a sequence program, and a sub CPU module connected to the RAM 14 and an external bus 3 (an example of a bus). ), A BUS controller M16 (M represents a "master") which is an interface with the external bus 3 and has an address output unit and a data input / output unit. Further, the CPU module 1 includes a counter that counts the number of continuous accesses for high-speed continuous access to the sub CPU module 2 described later. This counter can be configured hard or soft. Therefore, it is not shown in the CPU module 1 of FIG. MPU 11 is an example of a calculation unit. At least one of the ROM 13 and the RAM 14 is an example of the memory unit.

The CPU module 1 needs to know in advance what kind of sub CPU module 2 is connected to the sub CPU slot # 0, the sub CPU slot # 1, ..., The sub CPU slot # n. Therefore, the sub CPU module 2 holds information such as an input / output type and a data size as status information in, for example, a ROM, and transmits the status information to the CPU module 1 via the external bus 3. This status information includes information on whether or not high-speed continuous access can be supported. As a result, it is possible to determine from the CPU module 1 which sub CPU slot the sub CPU module 2 capable of supporting high-speed continuous access is mounted. The status information includes information on whether or not the broadcast can be supported, and it may be possible to determine from the CPU module 1 which sub CPU slot the sub CPU module 2 that can support the broadcast is mounted.

Modules such as IO modules (input modules and output modules) and communication modules for digital signals and analog signals are examples of the sub CPU module 2. The sub CPU module 2 includes, for example, a 2-port RAM 21 inside the module, and data is transferred between the CPU module 1 and the sub CPU module 2 via the 2-port RAM 21. At the time of access from the CPU module 1 side at that time, the sub CPU module 2 accesses the internal 2-port RAM 21 by the address acquired via the external bus 3, or sends from the CPU module 1 to the address. The internal 2-port RAM 21 is accessed by sending an incremented or decremented address corresponding to the number of consecutive accesses. To enable this access, the sub CPU module 2 includes a BUS controller S22 (S stands for "slave"). The address is also called the street address. The sub CPU module 2 also has an MPU and a ROM in addition to the RAM 21. The MPU of the sub CPU module 2 is an example of the sub calculation unit. At least one of the sub CPU module 2 ROM and the RAM 21 is an example of the sub memory unit.

The external bus 3 connects the CPU module 1 and various sub CPU modules 2 connected to the sub CPU slots # 0 to # n, and exchanges addresses, data, and control information. In this embodiment, the external bus 3 is a multiplex bus shared by addresses and data. Note that, in FIG. 1, among the signal lines constituting the external bus 3, the signal lines for the mode signal (mode_n) and the strobe signal (strobe_n), which will be described later, are shown in a separated form. Further, the external bus 3 may be included in a base board such as a backplane. In this case, connecting the CPU module 1 or the sub CPU module 2 to the external bus 3 may be performed by connecting the CPU module 1 or the sub CPU module 2 to the base board. The external bus 3 is associated with a connection portion (for example, a port) to which the CPU module 1 is connected and a plurality of sub connection portions (for example, a port) which are a plurality of connection portions to which a plurality of sub CPU modules 2 are connected to each other. Has been done. As a result, if the CPU module 1 is connected to the connection portion or the sub CPU module 2 is connected to the sub connection portion, the CPU module 1 and the sub CPU module 2 are electrically connected to the external bus 3. Two or more sub CPU modules 2 are connected to each of two or more sub connection portions that are all or a part of the plurality of sub connection portions. Each connection may be an element that includes a slot.

The present invention does not limit the external bus to this multiplex bus, and may be a separate type bus form. However, the multiplex bus can reduce the number of pins by reducing the number of signal lines required as compared with the separate type bus.

FIG. 2 is a configuration diagram of an internal block of the BUS controller S22 included in the sub CPU module 2.

The BUS controller S22, which is an interface with the external bus 3, has a flip-flop (FF) 31 that stores an address, an increase / decrease counter 32 that increments or decrements the address output by the flip-flop (FF), and a selector 33 for address selection. It is composed. Since the external bus 3 is a multiplex bus, among the input data from the external bus 3, the data is sent to the 2-port RAM as it is, and the address is sent to the selector 33. Note that in FIG. 2, the signal lines for the mode signal (mode_n) and the strobe signal (strobe_n) are omitted.

The flip-flop (FF) 31 increments or decrements the address input from the CPU module 1 via the external bus 3 or the address stored by the flip-flop (FF) 31 itself as its input by the increase / decrease counter 32. The address is selected by the selector 33. That is, at the time of normal access, the flip-flop (FF) 31 selects and stores and / or outputs the address from the external bus 3, and at the time of high-speed continuous access, the incremented or decremented address is selected and sequentially stored. And / or output. A mode signal (mode_n) described later is used for selection by the selector 33. Further, a mode signal (mode_n) and a strobe signal (strobe_n), which will be described later, are used to increment or decrement the increase / decrease counter 32.

Data access (data transfer) differs between the CPU module 1 and each sub CPU module 2 depending on whether or not the sub CPU module 2 can support high-speed continuous access. The difference in data access will be explained using a time chart.

First, FIGS. 3 and 4 show a time chart (normal access (normal I / O access)) when the CPU module 1 performs a refresh process on a normal sub CPU module (a sub CPU module that cannot support high-speed continuous access). ) Is performed (time chart). FIG. 3 is a time chart at the time of writing, and FIG. 4 is a time chart at the time of reading.

The external bus 3 is a multiplex bus shared by addresses and data, and the signals to be exchanged are a selection signal (cs_n), an address strobe signal (as_n), a data strobe signal (wr_n / rd_n), and 16 bits of each slot. Address / data signal (ad [15: 0]). The external bus 3 includes a plurality of signal lines through which these signals flow. For example, the external bus 3 includes a signal line through which a selection signal (cs_n) flows.

For example, in the refresh process for the output module of 32 points (bits), the write access shown in FIG. 3 is performed twice. Further, in the refresh process for the 8-channel analog input module, since one channel has 16 bits, the read access shown in FIG. 4 is performed eight times.

Next, FIGS. 5 and 6 are time charts when high-speed continuous access is performed between the CPU module 1 and the sub CPU module 2. FIG. 5 is a time chart at the time of writing, and FIG. 6 is a time chart at the time of reading.

The CPU module 1 specifies the address (ADR) of the address space to be accessed to the sub CPU module 2 (designation of an arbitrary address), and also a mode signal (mode_n) for identifying normal access or high-speed continuous access. Is output at the same timing as the address output. When the address strobe signal (as_n) rises, the sub CPU module 2 side determines whether the CPU module 1 is accessing by normal access or high-speed continuous access depending on the level of the mode signal (mode_n) (FIG. 5 and FIG. In FIG. 6, high-speed continuous access occurs at the L level of the mode signal (module_n)).

During the high-speed continuous access data cycle, the address inside the communication module is updated according to the level change of the strobe signal (strobe_n). That is, increment or decrement is selected depending on the level of the mode signal (mode_n) at the start of the level change of the strobe signal (strobe_n) (at the time of rising from the L level to the H level) (in FIGS. 5 and 6, the strobe is selected. When the mode signal (mode_n) starts to change from the L level to the H level of the signal (strobe_n), the mode signal (mode_n) is incremented if it is L level, and decremented if it is H level).

Then, the CPU module 1 specifies the number of continuous accesses (continuous address space) related to high-speed continuous access. The CPU module 1 uses a counter provided inside to transmit a strobe signal (strobe_n) pulsed by the number of continuous accesses corresponding to the continuous address space to the sub CPU module 2. The increase / decrease counter 32 of the BUS controller S22 included in the sub CPU module 2 receives the pulsed strobe signal and increments or decrements by the number of continuous accesses from the designated arbitrary address.

Further, even if a CPU module that does not support high-speed continuous access is adopted instead of the CPU module 1, and a sub CPU module that supports high-speed continuous access is adopted as the sub CPU module, normal access is possible. Since the output methods of the required control signals (cs_n, as_n, wr_n and rd_n) are compatible, normal access is possible between the CPU module and the sub CPU module.

In this embodiment, the sub CPU module 2 is provided with a 2-port RAM internally, but is provided with a 1-port RAM and an arbitration circuit (arbiter) added to the 1-port RAM instead of the 2-port RAM. May be good.

FIG. 7 is a flowchart showing the operation of the PLC. The PLC normally performs a series of processing flows of input refresh related to data input, sequence operation based on input data, and output refresh related to output of data accompanying the calculation result until a stop operation such as power off occurs. In the meantime, run cyclically. The time required for a series of cyclic processes by executing IO refresh (input refresh + output refresh) and sequence operation is called "scan time". Then, if the execution time of the sequence operation is constant, the scan time depends on the time required for IO refresh.

Next, according to the above flowchart, how much the cyclic calculation performance, that is, the scan time will differ depending on the presence or absence of high-speed continuous access will be described. Here, as a configuration example of the PLC, as shown in FIG. 1, a sub CPU module 2 that handles 8,192 words of data is mounted in the sub CPU slot # 0 and the sub CPU slot # 1, and the sub CPU module 2 is mounted. A sub CPU module 2 as an input module that handles one word of data is mounted in # 2, and a sub CPU module 2 as an output module that handles one word of data is mounted in sub CPU slot # 3. It shall be. Further, assuming that the unit time of IO access is "1 μsec", the scan time required for a series of cyclic processes shown in the flowchart of FIG. 7 is calculated. Further, in the following description, the sub CPU module 2 mounted in the sub CPU slot # x may be referred to as "sub CPU module # x".

It is assumed that the sub CPU module shown in FIGS. 3 and 4 (the sub CPU module that cannot support high-speed continuous access) is accessed. Since each of the sub CPU modules # 0 and # 1 handles a maximum of 8,192 words of data, when input refresh and output refresh are performed by normal access, the maximum IO refresh is "16,384 μsec" (about 16 msec). ) Will be required. Further, the time required for the sequence calculation depends on the capacity of the sequence program created by the user, and is usually "1 msec (= 1,000 μsec)" as a guideline. Then, the maximum scan time is "17,384 μsec", which is about 17 msec.

On the other hand, when the IO refresh for the sub CPU module 2 is performed by the high-speed continuous access shown in FIGS. 5 and 6, only the address is updated inside the sub CPU module 2. Then, the address can be updated at a higher speed than the address is sequentially acquired from the CPU module 1. Since the address update time inside the sub CPU module 2 is usually about 120 nsec, if it is set to "0.1 μsec", the time required for IO refresh of the sub CPU module 2 can be regarded as about "819 μsec" at the maximum. By adding the normal IO access (2 μsec) as the sub CPU module # 2 (input module) and the sub CPU module # 3 (output module) to this, the maximum IO refresh is “1,640 μsec”. Further, the scan time including the sequence calculation time (1 msec) is a maximum of "2,640 μsec". That is, it can be seen that the performance is improved by about 6.6 times as compared with the scan time in the case of the above-mentioned normal IO access.

In data communication, the address is specified once, and after data communication is performed to the specified address, read or write sequential data communication can be performed to the address after or before the specified address. It is not necessary to specify the address when performing this sequential data communication. This makes it possible to reduce the time required for the communication of specifying the address. That is, when one sub CPU module starts communication, after specifying the address for data communication before performing data communication, the one and the other sub CPU modules sequentially perform data communication. Since it has the settings or its information, data communication will be repeated. For example, a communication that specifies a designated address n is performed, and after data communication at the designated address n, a communication that specifies an address is performed for addresses n + 1, n + 2 ... Or n-1, n-2 ... Since it is unnecessary, it is possible to improve the overall data communication speed. Although it is described as n + 1, n + 2, etc. for convenience, the addresses after or before the designated address are appropriately changed depending on the number of buses for data communication, etc. Therefore, when generalized, the addresses where data communication is sequentially performed are It becomes n + m and n + 2m.

As described above, according to the description with reference to FIGS. 1 to 7, in the present embodiment, in the IO refresh process of the CPU module 1, the access to the continuous area (address space) is set to the above-mentioned high-speed continuous access. It is possible to speed up the processing. That is, after bus access from the CPU module 1 to the continuous address space is output once at an arbitrary address, the data strobe signal is toggled by the access size to enable read or write, and high-speed data transfer can be performed. Further, by performing the data transfer at high speed, the calculation cycle in the CPU module 1 becomes fast, and it becomes possible to process and execute the control for the external device at high speed.

As described above, the description with reference to FIGS. 1 to 7 can be summarized as follows, for example.

A control system (for example, PLC) has an arithmetic module (for example, CPU module 1), one or more sub arithmetic modules (for example, one or more sub CPU modules 2), and a bus (for example, an external bus) connecting those modules. 3) and. The operation module specifies an arbitrary address in the address space of each sub-operation module or the number of consecutive accesses corresponding to the consecutive address spaces in the sub-operation module. The sub-calculation module increments or decrements the address from any specified address by the number of continuous accesses, and executes IO processing on the continuous address space in the sub-operation module. The bus has a first signal line that communicates a mode signal that specifies the execution of IO processing and address increment or decrement on a contiguous address space, and a strobe signal that specifies the update timing for incrementing or decrementing the address. A second signal line for communication is attached.

The update timing for incrementing or decrementing the address may be when the level of the strobe signal changes.

The sub-calculation module may output a pulsed signal for the number of continuous accesses as a strobe signal.

In this embodiment, both normal access and high-speed continuous access may be single access (1: 1 data transfer between the CPU module 1 and the sub CPU module 2) via the external bus 3, or via the external bus 3. It may be a broadcast access (1: multiple simultaneous data transfer between CPU module 1 and CPU module 2). Broadcast access via the external bus 3 is realized as follows.

FIG. 8 is an image diagram showing the relationship between the address map of the external bus space of the CPU module 1 and the slot selection signal (cs_n).

The address map of the external bus space 800 is provided to the MPU 11 of the CPU module 1 by the BUS controller M16. The external bus space 800 may be a part of the address space described above. According to the address map, the external bus space 800 includes a plurality of individual IO spaces 801 mapped to the plurality of sub CPU slots and a common IO space 802 mapped to all the sub CPU slots. The individual IO space 801 is associated with one corresponding selection signal (for example, a selector 803 that asserts the selection signal), and the common IO space 802 is associated with a full selection signal (for example, a full selection signal). All selectors 803) for selection are associated. The association of selection signals corresponds to the association of selection signal lines.

Normally, when the CPU module 1 accesses the sub CPU module # n mounted in the sub CPU slot # n, a selection signal (cs_n) for selecting the sub CPU slot # n (sub CPU module # n) is asserted. By doing so, the sub CPU module #n is selected. As a result, even if any of the sub CPU modules 2 is mounted in any sub CPU slot, the sub CPU module 2 can be accessed from the CPU module 1 side. This is performed by selecting one sub CPU slot from the module selection signals individually prepared for each sub CPU slot by decoding the address according to the address map shown in FIG. 8 on the CPU module 1 side. it can.

Specifically, for example, the MPU 11 of the CPU module 1 performs IO to the individual IO space 801-1 when performing single access with the sub CPU module # 1. As a result, the selection signal (cs_n) for selecting the sub CPU slot # 1 is asserted, and the access according to any one of FIGS. 3 to 6 is performed as a single access between the CPU module 1 and the sub CPU module # 1. More specifically, for example, when the CPU module 1 individually specifies the sub CPU module # 0 that performs high-speed continuous access, by accessing the IO space 801-0, the target slot # 0 can be accessed. Only cs_n is output.

Further, for example, the MPU 11 of the CPU module 1 performs IO in the common IO space 802 when performing broadcast access with all the mounted sub CPU modules 2. As a result, the all-select signal is asserted, and as a broadcast access between the CPU module 1 and all the sub CPU modules 2 mounted, at the same time, between the CPU module 1 and each of the sub CPU modules 2 mounted, FIGS. Access is made according to any of FIG. That is, all cs_n are output at the same time, and data can be transferred from the CPU module 1 to all the sub CPU modules 2 at the same time. For example, when only the sub CPU modules # 0 and # 1 capable of high-speed continuous access are mounted in addition to the CPU module 1, the CPU module 1 is the sub CPU module through the common IO space 802 (broadcast IO space). High-speed continuous access to # 0 and # 1 can be performed at the same time. Therefore, the scan time of the maximum "2,642 μsec" can be increased to the maximum "1,823 μsec" which is 819 less. Note that "simultaneous" may mean that at least one of the start and end of data transfer is simultaneous, and even if at least one of the start and end of data transfer is different, data transfer to all sub CPU modules 2 is parallel. It may be done by.

As described above, broadcast access is realized in the data transfer via the external bus 3.

As described above, in the IO refresh process of the CPU module, the processing time can be significantly increased by setting the access to the continuous area (address space) as the above-mentioned high-speed continuous access in the IO refresh process as described above. Further, since data can be transferred to a plurality of modules at the same time, it is possible to easily support the construction of a synchronization system represented by motion control and the like. For example, by simultaneously lighting all the mounted sub CPU modules 2 according to high-speed continuous access, data common to all the mounted sub CPU modules 2 (for example, data from one or more sensors). Are lit at the same time, and all sub CPU modules 2 can process (for example, analyze) the data in parallel.

As illustrated in FIG. 9, the individual IO space 801 may be divided into a space 801a for normal access and a section 801b for high-speed continuous access. The common IO space 802 may also be divided into a space 802a for normal access and a section 802b for high-speed continuous access. In this case, at least one of the following may be performed.
-When the CPU module 1 normally accesses the sub CPU module # n, it accesses the space 801a of the individual IO spaces 801 corresponding to the sub CPU module # n.
-When the CPU module 1 performs high-speed continuous access with the sub CPU module # n, it accesses the space 801b of the individual IO spaces 801 corresponding to the sub CPU module # n.
-When the CPU module 1 normally accesses all the sub CPU modules 2 at the same time (for example, when at least one of all the sub CPU modules 2 is a module that cannot support high-speed continuous access), the common IO space 801 Access the space 802a of.
-When the CPU module 1 simultaneously performs high-speed continuous access with all the sub CPU modules 2, it accesses the space 802b of the common IO space 801.

When the CPU module 1 specifies that two or more sub CPU modules 2 are connected to the external bus 3, the CPU module 1 selects whether to use single access or broadcast access, and performs the selected access. .. For example, the CPU module 1 determines whether the data to be accessed is a target only with one sub CPU module 2 or a target common to all the mounted sub CPU modules 2 and determines the former. In the latter case, single access may be selected, and in the latter case, broadcast access may be selected. In the latter case, at least one of the following may be performed.
-The CPU module 1 selects single access if there is even one sub CPU module 2 that cannot support broadcast, and selects broadcast access if all sub CPU modules can support broadcast.
-If there is even one sub CPU module 2 that cannot be accessed continuously at high speed, the CPU module 1 can select normal access as broadcast access to all sub CPU modules 2 and all sub CPU modules can support high speed continuous access. If so, high-speed continuous access as broadcast access to all sub CPU modules 2 may be selected.

Further, in this embodiment, the following configuration may be adopted. That is, the CPU module 1 is connected to the I / O port by accessing at least one I / O port of one or more I / O ports (for example, a communication port) connected to one or more controlled devices. It has an MPU 11 that is connected to a sub CPU module 2 (for example, an I / O module) that controls the operation of the controlled target device via an external bus 3 and calculates information on the controlled target device, and a RAM 14 that stores the calculation result of the MPU 11. .. The sub CPU module 2 connected to the external bus 3 has an MPU (an example of a sub calculation unit) that calculates information on a controlled device and a RAM 21 (an example of a sub memory unit) that stores the calculation result of the MPU. Two or more sub CPU modules may be connected to the external bus 3. The CPU module 1 identifies all connected (mounted) sub CPU modules 2. Each sub CPU module 2 sequentially reads or writes data from the designated address of the RAM 21 toward the next or previous address (for example, by DMA) in a first communication mode (for example, a mode for single access). ). In addition to the CPU module 1, the sub CPU module 2 may also have the address map illustrated in FIG. 8 or 9. In other words, in each of the CPU module 1 and the sub CPU module 2, the individual area in which the individual data for the sub CPU module 2 is written and the common area in which the common data for all the sub CPU modules 2 are written are the logical addresses. It may exist as a space. The logical address space may be a space based on RAM 14 or 21. Each of the two or more sub CPU modules 2 reads or writes the information of the specified address of the RAM 21 for reading or writing the area for storing the common data (for example, the common IO space 802). It has a communication mode (for example, a mode for broadcast access).

1 ... CPU module, 2 ... Sub CPU module, 3 ... External bus,
11 ... MPU, 12 ... communication port, 13 ... ROM, 14 ... RAM, 15 ... DMAC,
16 ... BUS controller M, 21 ... 2-port RAM, 22 ... BUS controller S,
31 ... Flip-flop (FF), 32 ... Increase / decrease counter, 33 ... Selector

Claims (6)

Arithmetic module and
It is provided with a connection portion to which the arithmetic module is connected and a bus associated with a plurality of sub-connection portions which are a plurality of connection portions to which a plurality of sub arithmetic modules are connected.
In the arithmetic module, two or more individual spaces in which the space of the bus is two or more spaces corresponding to two or more sub-connections which are all or a part of the plurality of sub-connections, and two or more individual spaces. Including the common space, which is a common space in the sub-connection part of
When two or more sub-operation modules are connected to the two or more sub-connection units, the operation module makes a single access to transfer data to or from any of the sub-operation modules. Selectively perform broadcast access using the common space, which is to simultaneously transfer data between the two or more sub-operation modules, and to use the individual space corresponding to the above.
Control system. Each of the two or more individual spaces is associated with a selection signal for selecting a sub-calculation module connected to the sub-connection unit corresponding to the individual space.
All of the two or more selection signals corresponding to the two or more sub-connections are associated with the common space.
The arithmetic module
When the single access is selected, the selection signal associated with the individual space is asserted by accessing the individual space corresponding to the sub-arithmetic module that follows the single access.
When the broadcast access is selected, the all-selection signals associated with the common space are simultaneously asserted by accessing the common space.
The control system according to claim 1. The arithmetic module
If the data to be transferred is data for one of the sub-operation modules, select single access to that sub-operation module, and select
When the data to be transferred is the data common to the two or more sub-arithmetic modules, broadcast access is selected.
The control system according to claim 1. When the data to be transferred is the data common to the two or more sub-calculation modules, the arithmetic module is
If there is at least one sub-operation module that cannot be accessed continuously at high speed in the two or more sub-operation modules, normal access as the broadcast access is selected.
If any of the two or more sub-arithmetic modules can be accessed continuously at high speed, high-speed continuous access as the broadcast access is selected.
The control system according to claim 3. The arithmetic module is designed to specify an arbitrary address in the address space of each sub arithmetic module or the number of continuous accesses corresponding to the continuous address space in the sub arithmetic module.
Each sub-operation module increments or decrements the address from any specified address by the number of continuous accesses, and executes IO processing for the continuous address space in the sub-operation module.
The bus contains a first signal line that communicates a mode signal that specifies the execution of IO processing and address increment or decrement on a continuous address space, and a strobe signal that specifies the update timing for incrementing or decrementing the address. A second signal line, which communicates with, is attached,
The arithmetic module uses the first signal line and the second signal line to select either normal access or high-speed continuous access.
The control system according to claim 4. The arithmetic module operates the control target device connected to the I / O port by accessing at least one I / O port of the one or more I / O ports connected to the control target device. It has a calculation unit that is connected to the sub-calculation module to be controlled via the bus and calculates information of the controlled device, and a memory unit that stores the calculation result of the calculation unit.
The sub-calculation module has a sub-calculation unit that calculates information on a controlled device and a sub-memory unit that stores the calculation result of the sub-calculation unit.
Each sub-calculation module has a first mode of communication for single access that reads or writes data sequentially from a specified address to the next or previous address.
The sub-arithmetic module has a second communication mode for broadcast access that reads or writes data at a designated address for reading or writing data to the common space.
The control system according to claim 2.

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