JPS55135927A - Memory write-in control system - Google Patents

Memory write-in control system

Info

Publication number
JPS55135927A
JPS55135927A JP4359479A JP4359479A JPS55135927A JP S55135927 A JPS55135927 A JP S55135927A JP 4359479 A JP4359479 A JP 4359479A JP 4359479 A JP4359479 A JP 4359479A JP S55135927 A JPS55135927 A JP S55135927A
Authority
JP
Japan
Prior art keywords
peripheral
write
control signal
instruction
memory write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4359479A
Other languages
Japanese (ja)
Inventor
Tatsuhiro Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4359479A priority Critical patent/JPS55135927A/en
Publication of JPS55135927A publication Critical patent/JPS55135927A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE: To make it possible to reduce a program and to shorten the processing time, by executing a peripheral write-in instruction and a peripheral read-out instruction in order that the peripheral write-in information and the peripheral read- out information can be stored in the memory simultaneously.
CONSTITUTION: A gate circuit G1 is provided in order to take logical sum of a control signal of the memory write-in control signal line MEMW, a control signal of the peripheral read-out control line IOR, and a control signal of the peripheral write-in control signal IOW, and simultaneously an output signal of the circuit G1 is provided to the memory write-in control signal input terminal WE of RAM. Thus, in case of the peripheral write-in instruction, simultaneously the peripheral write-in information to the output device OD can be stored in RAM without executing the memory write-in instruction. Moreover, in case of the peripheral read-out instruction, simultaneously the peripheral read-out information from the input device ID can be stored in RAM without executing the memory write-in instruction.
COPYRIGHT: (C)1980,JPO&Japio
JP4359479A 1979-04-12 1979-04-12 Memory write-in control system Pending JPS55135927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4359479A JPS55135927A (en) 1979-04-12 1979-04-12 Memory write-in control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4359479A JPS55135927A (en) 1979-04-12 1979-04-12 Memory write-in control system

Publications (1)

Publication Number Publication Date
JPS55135927A true JPS55135927A (en) 1980-10-23

Family

ID=12668116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4359479A Pending JPS55135927A (en) 1979-04-12 1979-04-12 Memory write-in control system

Country Status (1)

Country Link
JP (1) JPS55135927A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011956A (en) * 1983-06-30 1985-01-22 Fujitsu Ltd Register control system
JPH02268355A (en) * 1989-04-10 1990-11-02 Fujitsu Ltd Output system for control signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011956A (en) * 1983-06-30 1985-01-22 Fujitsu Ltd Register control system
JPH02268355A (en) * 1989-04-10 1990-11-02 Fujitsu Ltd Output system for control signal

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