JPH02268355A - Output system for control signal - Google Patents

Abstract

PURPOSE:To increase the execution speed of a control signal output device and to simplify the control by holding control data to be written by a register and outputting a control signal corresponding to this data to store it in a memory means and updating the control signal on the basis of control data read out from the memory means. CONSTITUTION:The address of a RAM 12 is designated through an address bus AB for the purpose of accessing the address area assigned for storage of control data D7 to D0. A read signal RE is used to read out control data D7 to D0 corresponding to control signals S7 to S0, which an output control register 11 outputs, from the RAM 12, and this control data is referred to generate control data D7 to D0 for the purpose of updating control signals S7 to S0. Thereafter, a specific address is given to a bus AB for the purpose of outputting control signals S7 to S0 corresponding to data D7 to D0, and the output control register 11 and the RAM 12 are simultaneously addressed, and new control data is written through a data bus DB.

Description

[Detailed Description of the Invention] [Summary] Regarding a control signal output method for controlling a peripheral device in a computer system or controlling an output device in a peripheral device, the present invention relates to increasing the execution speed and controlling the execution speed of a control signal output device. The purpose is to provide a method for outputting control signals that can be made into a cylinder, and the control data D7 to D7 to be written via the data bus DB.
A register 11 that holds 0 and outputs control signals 37-O corresponding to the control data D7-0, and a memory means 12 that stores the control data D7-O,
The control data D7 read from the memory means 12
This is an output method of a control signal that updates the control signals S7 to S0 based on 0 to 0, in which the register 11 and the memory means 12 are addressed by the same address AD, and the register 11 and the memory means 12 are The control data D7-O are configured to be written into the memory means 12 at the same time.

[Industrial application field]

The present invention relates to a control signal output method for controlling a peripheral device in a computer system or controlling an output device in the peripheral device.

Peripheral devices that make up the system together with the CPU (Central Processing Unit), such as displays, printers, and FDDs
(Floppy disk drive) devices and the like are controlled by control signals output from the CPU. In addition, output devices in peripheral devices, such as motors, solenoids,
Display lamps and the like are turned on and off by control signals output from a processing device (processor) built into a CPU or a peripheral device.

In order to improve the processing efficiency of the entire system, it is desired to simplify the processing operations performed by a CPU or a processing device for outputting control signals.

[Prior Art] A peripheral device is provided with a plurality of output devices such as a motor, a solenoid, and an indicator lamp. Control data for controlling the plurality of output devices is input from the processing device via the data bus to the control signal output device connected to these output devices at a predetermined timing.

The control data is written and held in an output control register within the control signal output device, and is sent from the output control register to the output device as a control signal.

The processing device outputs control data of the number of bits of the data bus (for example, 8 bits) in one data output operation. Generally, an output control register has a data holding capacity corresponding to the number of bits of control data, and can output a number of control signals (binary signals) equal to the number of bits of control data.

The control signals are updated in a timely manner according to the operation of the peripheral device, but among the multiple control signals output from the output control register, there are some whose states should be changed when updating and others whose status should be maintained. In addition, the output device may be controlled by changing the control signal to the opposite state depending on the current situation.

Therefore, in order to update the control signal, it is necessary to detect the current state of the control signal.

Therefore, data (control data) having the same content as the control data held by the output control register is written and stored in another memory, and the content of this memory is read out and referenced.

In other words, in the conventional control signal output method, a reference memory for storing reference data with the same contents as the output control register is provided in an address area different from the address area of the output control register. , When outputting (updating) a control signal, the processing device first obtains the address of the reference memory from the address corresponding to the output control register, specifies the address for the reference memory, and reads the control data. .

Next, the read control data is subjected to a logical sum or logical product operation to generate new control data in which only the bit corresponding to the control signal to be changed is changed.

Then, the generated control data is written to the reference memory and then to the output control register.

From the output control register, the changed control signal and the control signal in which the previous state is maintained are output to the respective output devices, and the predetermined output devices are turned on and off.

[Problem to be solved by the invention]

As described above, in the conventional control signal output method, the address for the output control register and the address for the reference memory are respectively assigned separately.

Therefore, it is necessary to specify the address of the output control register and the address of the reference memory twice, independently of each other, and when reading data from the reference memory and writing data to the output control register. , it is necessary to perform processing to obtain each address, and the control of the control signal output device is complicated.

Therefore, there is a problem in that the execution speed of the control signal output device cannot be increased, and that it takes a lot of time and effort to develop a program for controlling the control signal output device.

Additionally, in order to detect the state of the control signal, the control data held in the output control register can be directly retrieved by the processing unit without intervening memory, but for this purpose, the data bus and output A transceiver or the like is required to switch data transmission/reception between the control register and the hardware and its control becomes complicated.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a control signal output method that can increase the execution speed of a control signal output device and simplify control.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention, as shown in FIG. a register 11 that outputs 0;
A control signal output method comprising a memory means 12 for storing the control B data D7-0, and updating the control signals 87-0 based on the control data D7-0 read from the memory means 12. , the register 11 and the memory means 12 are addressed by the same address AD, and the control data D7 to D0 are written into the register 11 and the memory means 12 at the same time.

[For production]

The register 11 holds control data D7 to D0 written via the data bus DB, and also holds control data D7.
A control signal 87-0 corresponding to ~0 is output.

The memory means 12 stores control data D7-0.

Based on the control data D7-0 read from the memory means 12, the control signals 87-0 are updated.

The register 11 and the memory means 12 are written at the same address AD when the control data D7 to D0 are written therein.
Address designation is performed by , and control data D7 to D0 are written at the same time.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a control signal output device 1 according to the present invention, and FIG. 2 is a flowchart showing control signal output processing according to the present invention.

In FIG. 1, the control signal output device 1 includes a processing device 20
It is also incorporated into the printer as a peripheral device.

The control signal output device 1 holds 8-bit control data D7 to 0 written via the data bus DB, and outputs 8 types of control signals (binary signals) 37 to 0 corresponding to the control data D7 to 0. an output control register 11 consisting of a D-flimb flow controller, a RAM 12 that stores control data D7 to D0 in the address area designated by the processing device 20 via the address bus When input, the chip select signal C is sent to the output control register 11.
It consists of a decoder 13 that outputs 5.

Writing to and reading from the RAM 12 is controlled by a write signal WR and a read signal RE from the processing device 20, and control data D7 to D0 are written to the output control register 11 by the write signal WR. That is, the output control register 11
From this point of view, it is treated as write-only memory.

The output control register 11 is connected to an output device (not shown) for printing. That is, the control signals 37 to 5 are used to control the drive motor MA- for feeding paper and moving the print head.
The control signals 84 to 0 are output to the display lamps LA-H.
These control signals 37-'0 individually control the on/off of the drive motors MA-MC and indicator lamps LA-LE.

A decoder 13 inputs a chip select signal C to the RAM 12.
An address area accessed by the same address AD as the address AD that outputs 3 is allocated. That is, when a specific address is output from the processing device 20 onto the address bus AB, the output control register 11 is chip-selected, and at the same time, an address area is created in the RAM 12 that stores the same control data D7 to D0 as the output control register 11. is accessed, and the control data D7 to D0 can be read and written.

Next, the control signal output processing that the processing device 20 performs on the control signal output device 1 will be described with reference to FIG.

In FIG. 2, first, steps #1 and #2 are executed to detect the current state of each control signal 37 to 0 output from the output control register 11.

In step #1, RAMI2 is addressed via address bus AB in order to access the address area allocated for storing control data D7-0.

In step #2, control data D7-0 corresponding to each control signal 37-0 outputted by the output control register 11 is read from the RAM 12 in response to the read signal RE.

Before the control of the output device starts, such as immediately after the power is turned on, the value of each bit of the read control data D7-O is all "0", and the control of the output device has already started. If it has been started, the control signal 37 in the on state
The bit for ~0 is "1", and the bit for control signals S7-0 in the off state is "0".

Next, in step #3, the read control data D7-0
With reference to , new control data D7-0 for updating control signals S7-0 is generated.

In other words, when changing any of the bits of the control signals 87 to 0 from the OFF state to the ON state, the 8-bit operation data in which the bit to be changed is "1" and the other bits are "0" is changed.・When performing a bit-by-bit logical OR operation between control signal D7 and control data D7 to D0, and changing any of the bits of control signals D7 to D0 from the on state to the off state, the bit to be changed is set to "0". ", and the other bits are "1", and the control data D7-0 are logically ANDed for each bit. As a result, the bits corresponding to the control signals S7-0 to be changed are New control data D7 in which only the value is inverted and the current values are maintained for other bits.
~0 is generated.

Next, the new control data D7~ generated in step #3
Step #4 and step #5 for outputting control signals 37 to 0 corresponding to 0 are executed.

In step #4, a specific address is output onto the address bus AB, and addresses of the output control register 11 and RAM 12 are simultaneously specified.

In step #5, the write signal WR is made active,
Step #3 is stored in the output control register 11 and RAM 12.
The new control data D7-0 generated by
Write via.

The output control register 11 outputs control signals 37 to 0 that are updated corresponding to the new control data D7 to 0 that have been written.
is output.

Such control signal output processing is performed by the output control register 11.
control signals 37 to 0 depending on the operation of the output device connected to
It is executed in a timely manner when it becomes necessary to update the output device, and the output device is controlled accordingly.

According to the embodiment described above, the same address AD is assigned to the output control register 11 and the address area of the RAM 12 for storing the control data D7 to D0, so that the output control register 11 and the address area of the RAM 12 for storing the control data D7 to D0 are assigned the same address AD. control register 11
There is no need to provide an address conversion table for associating an address with an address in RAM, or to obtain the address by calculation, and by specifying the address once, control data D7 to D0 can be sent to the output control register 11 and RAM 12 at the same time. Can be written. Therefore, the execution speed of the output processing by the processing device 20 is increased, the processing time required for outputting the control signals 37 to 0 can be shortened, and the time and effort required for creating a program for output processing can be reduced. can do.

In the embodiment described above, a plurality of output control registers 11 can be provided depending on the number of control signals required to control the output device. In that case, a plurality of address areas corresponding to each output control register 11 are allocated within the RAM 12.

In the above-mentioned embodiment, the control signal output device l incorporated in the peripheral device was illustrated and the output method of the control signals D7 to O for controlling the output device was explained.
The present invention can also be applied to control signals output from the PU to peripheral devices.

〔Effect of the invention〕

According to the present invention, it is possible to increase the execution speed of the control signal output device and simplify control.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a control signal output device according to the present invention, and FIG. 2 is a flowchart showing control signal output processing according to the present invention. In the figure, 11 is an output control register (register), 12 is a RAM (memory means), AD is an address, D7-0 are control data, DB is a data bus, and SO-S7 are control signals.

Claims (1)

[Claims] (1) Holds control data (D7 to 0) written via a data bus (DB) and
A register (11) that outputs control signals (S7) to (S0) corresponding to the control data (D7 to 0);
) for storing the control data (D7 to 0) read from the memory means (12).
), the control signal output method updates the control signals (S7) to (S0) based on the control signals (S7) to (S0), the register (11) and the memory means (12) being addressed by the same address (AD). A control signal output method characterized in that the control data (D7 to D0) are simultaneously written into the register (11) and the memory means (12).