JP2006041397A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain the manufacturing method of a semiconductor device that manufactures a high-quality semiconductor device by equalizing the heights of each element isolation from the surface of a semiconductor substrate, when an insulating film is embedded in different depth grooves to form the device isolation. <P>SOLUTION: First to third mask layers are formed on the semiconductor substrate, regions corresponding to a first deep device separation and a second shallow device separation are etched in the third and the second mask layers, a region corresponding to a first device isolation is etched in the first mask layer, the forming region of the first element isolation in the semiconductor substrate is etched with the third and the first mask layers as the masks to form a first groove, a region corresponding to the second element isolation is etched in the first mask layer, the forming regions of the first and the second device isolation on the semiconductor substrate are etched with the third mask layer as the mask to form a second groove, and the first groove is deepened to embed the insulating film in the first and the second grooves, thereby planarize the insulating film. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including an element isolation technique for electrically isolating semiconductor elements.

  Due to rapid miniaturization in recent years, semiconductor integrated circuits have been increasingly densified. Along with this, in order to increase the degree of integration per unit area in the state-of-the-art integrated circuit, it is required to miniaturize the element isolation region while maintaining the element isolation capability. In response to such a demand for miniaturization, a trench isolation method is widely used as an element isolation method instead of the conventional LOCOS (Local Oxidation of Silicon) method. The trench isolation method is a method of achieving electrical isolation of elements by filling a groove provided between the elements with an insulating film. However, in order to realize the miniaturization of the element isolation region, it is necessary to miniaturize only the isolation width without changing the depth of the trench in order to maintain the element isolation capability. The difficulty is increasing.

  Further, among the most advanced integrated circuits, a large-capacity device has a memory cell portion and a peripheral circuit portion. In such a large-capacity device, when a groove having the same depth as that of the peripheral circuit portion is used in the memory cell portion in order to greatly increase the integration degree of the memory cell portion, there is a situation that the filling of the insulating film cannot be achieved. It will occur. For this reason, as a trench isolation method used for manufacturing such a large-capacity memory device, a relatively shallow groove is used in a highly integrated memory cell portion, and deep in a peripheral circuit portion having a relatively low integration degree. A dual trench isolation method using grooves is used.

  Here, a method for forming an element isolation region by a conventional dual trench isolation method will be described. In the conventional dual trench isolation method, first, a silicon oxide film and a silicon nitride film are formed on the surface of a silicon substrate. Next, the silicon nitride film and the silicon oxide film on the region where element isolation is to be formed are selectively removed by anisotropic etching using a photoresist mask. Then, after removing the photoresist mask, shallow trench grooves and deep trench grooves are formed by anisotropic etching using the silicon nitride film as a mask.

  Next, a region including the shallow trench is covered with a photoresist, and a deep trench is formed by anisotropic etching using the photoresist and the silicon nitride film as a mask. Thereafter, the sidewalls and bottom surfaces of the shallow trench groove and the deep trench groove are oxidized by a heating oxidation method to remove a damaged layer caused by etching. Further, a silicon oxide film is deposited on the entire surface by a CVD (Chemical Vapor Deposition) method and buried in a shallow trench groove and a deep trench groove, and the surface is flattened by a CMP (Chemical Mechanical Polishing) method using a silicon nitride film as a stopper. Thus, the silicon oxide film is left only in the shallow trench groove and the deep trench groove.

  Thereafter, the silicon nitride film is removed, well formation and ion implantation for determining the threshold value of the transistor are performed, and the silicon oxide film is further removed to complete the element isolation region. Thereafter, gate oxidation is performed to form a gate electrode, a source / drain region, and the like, so that a semiconductor element is formed and connected to each other by a wiring layer.

  In addition, as a dual trench isolation method for obtaining a shallow trench and a deep trench, for example, a method of defining each trench in a well isolation region and an element isolation region, that is, a shallow trench and a deep trench on the same photomask, A technique for forming both regions by self-alignment has been proposed (see, for example, Patent Document 1).

JP 60-226136 A

  However, in the conventional dual trench isolation method as described above, since the etching selectivity between silicon and silicon nitride film is small, the silicon substrate is covered with a photoresist when the silicon substrate is etched to form a deep groove. The silicon nitride film which is not etched is also etched. For example, when a silicon substrate is etched at a depth of 150 nm, the silicon nitride film is etched by about 40 nm. Therefore, when a silicon oxide film is buried in shallow trench grooves and deep trench grooves and the surface is planarized by CMP using a silicon nitride film as a stopper, a shallow trench groove forming region and a deep trench groove are formed. The state in which the height of the silicon nitride film serving as the hard mask differs depending on the region to be processed, and as a result, the thickness of the silicon oxide film embedded in the element isolation region from the surface of the silicon substrate differs.

  The difference in film thickness of the buried insulating film (silicon oxide film) from the surface of the silicon substrate has a great influence on the fine processing after element isolation formation. In particular, it affects the exposure accuracy of lithography when processing the gate electrode, and also causes variations in etching. For example, a situation occurs in which the gate electrode becomes thin in a region where a shallow trench is formed, and as a result, a transistor having the same characteristics cannot be obtained in a region where a shallow trench and a deep trench are formed.

  Further, after processing the gate electrode, a side wall of the gate electrode material is formed on the shoulder of the portion where the element isolation height is relatively high, which causes a short circuit. In order to eliminate the cause of this short-circuit, if the height of the element isolation is lowered, the element isolation edge is recessed at a portion where the element molecule height is relatively low, and the threshold value of the transistor surrounded by the element isolation is lowered. Occurs and causes variation in transistor characteristics.

  Further, when the silicon oxide film buried in the trench groove is planarized by CMP using the silicon nitride film as a stopper, the silicon oxide film on the boundary portion between the region where the shallow trench groove exists and the region where the deep trench groove exists In other words, the silicon oxide film may remain, or the silicon nitride film around the boundary portion may be further scraped due to the polishing by the CMP method. Also in this case, as a result, the film thickness of the silicon oxide film embedded in the element isolation region from the surface of the silicon substrate is different.

  Further, in the above-mentioned Patent Document 1, a manufacturing method is disclosed in which a silicon oxide film embedded in an element isolation region has a structure in which a film thickness from the surface of the silicon substrate is equal to that of a shallow groove and a deep groove. When etching a silicon nitride film that is a hard mask on a region to be formed, a situation occurs in which the silicon oxide film that is a film below the silicon nitride film is scraped because the selection ratio between the silicon nitride film and the silicon oxide film is small. . In particular, in recent years, thinning of the inner wall oxidation is progressing in order to secure an active region. Along with this, it is necessary to reduce the thickness of the silicon oxide film on the silicon substrate in order to reduce the drop of the separation end. For this reason, in the case of the manufacturing method described in the above-mentioned Patent Document 2, the silicon oxide film is burned out, which causes a problem that dual trench isolation cannot be formed.

  The present invention was devised in view of the above problems, and when isolating elements by embedding insulating films in trenches having different depths, the height of each element isolation from the surface of the semiconductor substrate is equalized, An object of the present invention is to obtain a semiconductor device manufacturing method for manufacturing a high-quality semiconductor device.

  In order to solve the above-described problems and achieve the object, a manufacturing method of a semiconductor device according to the present invention forms a first mask layer on an semiconductor substrate, which serves as an etching mask when etching the semiconductor substrate. A step of forming a second mask layer having a high etching selectivity with respect to the first mask layer on the first mask layer, a first mask layer on the second mask layer, and A step of forming a third mask layer serving as an etching mask when the semiconductor substrate is etched, and a first trench element isolation and a depth which are deep in the third mask layer and the second mask layer; Etching the region corresponding to the shallow second trench element isolation formation region, and etching the region corresponding to the first trench element isolation formation region in the first mask layer; Using the third mask and the first mask as an etching mask to etch away the first trench element isolation formation region in the semiconductor substrate to form a first trench groove for first trench element isolation formation; Etching the region corresponding to the formation region of the second trench element isolation in the first mask layer, and the first trench element isolation and the second trench in the semiconductor substrate using the third mask layer as an etching mask Forming a second trench groove for forming a second trench element isolation by etching away the formation region of the element isolation, and further deepening the first trench groove; and the first trench groove and the second trench The method includes a step of embedding an insulating film in the groove and a step of planarizing the insulating film.

  According to the present invention, in the area around the first trench groove for forming the first trench element having a deep depth and the area around the second trench groove for forming the second trench element having a shallow depth. Thus, there is no difference in the height of the mask layer serving as an etching mask when the groove is formed by etching. As a result, when the insulating film is embedded in the first trench groove and the second trench groove, which are element isolation formation regions, and planarized, the height (film thickness) of the insulating film from the surface of the semiconductor substrate is substantially equal. Become.

  Furthermore, the insulating film is prevented from remaining on the third mask when the insulating film is planarized at the boundary between the region where the first trench groove exists and the region where the second trench groove exists. . Further, the polishing for planarization of the insulating film causes the third mask around the boundary between the region where the first trench groove is present and the region where the second trench groove is present to be scraped. A difference in height between shallow element isolation and deep element isolation is prevented.

  According to the present invention, the height of each element isolation having different depths from the surface of the semiconductor substrate can be made uniform, and a semiconductor device for manufacturing a high-quality semiconductor device free from variations in characteristics caused by element isolation. There is an effect that a manufacturing method can be obtained.

  Embodiments of a method for manufacturing a semiconductor device according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited by the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

Embodiment 1 FIG.
1 to 14 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to the first embodiment of the present invention. Below, the manufacturing method of the semiconductor device concerning this Embodiment is demonstrated, referring FIGS. In the method of manufacturing a semiconductor device according to the present embodiment, first, as shown in FIG. 1, a silicon oxide film 12 serving as a first mask is formed on the surface of a silicon substrate 10 which is a semiconductor substrate by, for example, 5 nm by a thermal oxidation method. The film is formed to a thickness of about ˜15 nm.

  Next, as shown in FIG. 2, a non-single crystal silicon film 14 serving as a second mask is deposited on the silicon oxide film 12 by a CVD method with a film thickness of, for example, about 10 nm to 200 nm, and further shown in FIG. Thus, the silicon nitride film 16 serving as the third mask is deposited by the CVD method with a film thickness of about 20 nm to 250 nm, for example. Here, the silicon oxide film 12 functions as an etching mask as will be described later, and stress relaxation for avoiding the influence of stress on the silicon substrate 10 by directly forming the silicon nitride film 16 on the silicon substrate 10. Form as a film. Further, when the non-single crystal silicon film 14 is anisotropically etched, the non-single crystal silicon film 14 takes advantage of the high etching selectivity between the non-single crystal silicon film 14 and the silicon oxide film 12. The silicon oxide film 4 is formed in order to prevent the silicon oxide film 4 from being scraped and lost.

  Next, using the photoresist mask, the silicon nitride film 16 and the non-single-crystal silicon film 14 on the region where element isolation is to be formed are selectively removed by anisotropic etching. That is, first, as shown in FIG. 4, a photoresist 18 is formed on a portion of the silicon nitride film 16 corresponding to a region where no element isolation is to be formed. Next, as shown in FIG. 5, using the photoresist 18 as an etching mask, the silicon nitride film 16 and the non-single-crystal silicon film 14 in the region where element isolation is to be formed are removed by etching to form the opening 19 and the opening 21. . At this time, the opening widths of the silicon nitride film 16 and the non-single-crystal silicon film 14 are about 50 nm to 500 nm. The opening 19 corresponds to a shallow element isolation formation region, and the opening 21 corresponds to a deep element isolation formation region.

  Next, the photoresist 18 is removed, and the region including the opening 19 corresponding to the region where the shallow groove is formed is covered with the photoresist 20 as shown in FIG. 6, and the photoresist 20 and the silicon nitride film 16 are used as a mask. As shown in FIG. 7, the silicon oxide film 12 corresponding to the region where deep element isolation is to be formed is removed by etching. At this time, a photoresist edge may be present in a region where element isolation is formed.

  Thereafter, the photoresist 20 is removed as shown in FIG. 8, and deep element isolation is formed as shown in FIG. 9 using the silicon oxide film 12 and the silicon nitride film 16 on the region where shallow element isolation is to be formed as a mask. The silicon substrate 10 in the region to be etched is excavated by etching to about 50 nm to 300 nm to form a trench groove 22 for deep element isolation formation. The depth at which the silicon substrate 10 is etched in this step, that is, the depth of the trench groove 22 is the amount of difference between the deep element isolation depth finally formed and the shallow element isolation depth. Further, the amount of the silicon oxide film 12 on the region where shallow element isolation is formed at this time is small because the etching selectivity between the silicon oxide film 12 and the silicon substrate 10 is extremely high.

  Next, as shown in FIG. 10, the silicon oxide film 12 on the region where shallow element isolation is to be formed is removed by etching. Then, using the silicon nitride film 16 as a mask as shown in FIG. 11, the silicon substrate 10 in the region for forming shallow element isolation and the region for forming deep element isolation is excavated by about 50 nm to 300 nm by etching to form shallow element isolation. A trench 24 for forming a deep element isolation and a trench 22 for deep element isolation are further deepened. The depth at which the silicon substrate 10 is etched in this step is the amount of shallow element isolation.

  By passing through the above process, the trench groove | channel 22 for deep element isolation formation and the trench groove | channel 24 for shallow element isolation formation can be formed in desired depth. In the present embodiment, trench groove 22 and trench groove 24 can be formed to a desired depth without causing a difference in height of silicon nitride film 16. Further, here, a case where two types of trench grooves having different depths are formed has been described. However, three or more types of trench grooves having different depths can be formed by repeating the same process.

  Next, the sidewalls and bottom surfaces of the trench groove 22 and the trench groove 24 are oxidized to a depth of about 2 nm to 30 nm by a thermal oxidation method, and the damaged layer due to etching is removed. Further, as shown in FIG. 12, a silicon oxide film 26, which is an insulating film, is deposited to a thickness of 300 nm to 600 nm in a region including the trench groove 22 and the trench groove 24 by, for example, a CVD method. 24 is embedded. Then, the surface of the silicon oxide film 26 is planarized by a CMP (Chemical Mechanical Polishing) method using the silicon nitride film 16 as a stopper to remove the unnecessary silicon oxide film 26 on the silicon nitride film 16, and as shown in FIG. The silicon oxide film 26 is left only in the trench groove 22 and the trench groove 24.

  Thereafter, the silicon nitride film 16 and the non-single-crystal silicon film 14 are removed, ion implantation for determining well formation and a transistor threshold value is performed by a conventionally known method, and the silicon oxide film 12 is removed. As shown in FIG. 14, the deep element isolation 28 and the shallow element isolation 30 are completed. The completed deep element isolation 28 and shallow element isolation 30 have substantially the same height from the surface of the silicon substrate 10. After this, a gate oxide film is formed by a conventionally known method, a semiconductor element is formed by forming a gate electrode, a source / drain region, and the like, and a semiconductor device is completed by being connected to each other by a wiring layer. To do. In the above description, the case where three mask layers are formed on the silicon substrate 10 has been described. However, in the present invention, the mask layer formed on the silicon substrate 10 is not limited to three layers. It can be changed as appropriate.

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, when forming trench grooves having different depths, the mask layer around the region for forming shallow element isolation, that is, the shallow trench groove, is formed. There is no difference in height from the surface of the silicon substrate 10 between the peripheral mask layer and the mask layer in the vicinity of the region for forming the deep element isolation, that is, the mask layer in the vicinity of the deep trench groove.

  In the element isolation forming step, the mask layer around the shallow element isolation region, that is, the mask layer around the shallow trench groove 24, and the mask layer around the region that forms the deep element isolation, ie, the deep trench groove 22 are formed. Since there is no difference in height between the peripheral mask layer and the peripheral mask layer, silicon nitridation is performed at the boundary between the region where the shallow trench groove 24 is present and the region where the deep trench groove 22 is present during polishing by the CMP method. The silicon oxide film 26 is prevented from remaining on the film 16. Further, the silicon nitride film 16 in the vicinity of the boundary portion is further scraped due to the polishing by the CMP method, so that there is no difference in height between shallow element isolation and deep element isolation.

  Thereby, according to the manufacturing method of the semiconductor device according to the present embodiment, the silicon oxide film 26 is embedded in the trench groove 22 and the trench groove 24 which are element isolation formation regions, and after the polishing by the CMP method, the silicon oxide film 26 is formed. The film thickness from the surface of the silicon substrate 10 can be reliably made substantially equal. Therefore, the heights of the finally formed shallow element isolation 30 and deep element isolation 28 from the surface of the silicon substrate 10 can be reliably made substantially the same. Further, even when the silicon oxide film 12 on the silicon substrate 10 is a thin film, shallow element isolation and deep element isolation, that is, dual trench isolation can be surely formed.

  As a result, it is possible to eliminate the influence on the microfabrication due to the difference in height between the formed shallow element isolation 30 and deep element isolation 28 from the surface of the silicon substrate 10, and to manufacture a high-quality semiconductor device. it can. In particular, it is possible to reduce lithography exposure accuracy and etching variation when processing a gate electrode, and to reduce variation in transistor characteristics. Therefore, according to the method for manufacturing a semiconductor device according to the present embodiment, it is possible to manufacture a high-quality semiconductor device in which the height from the surface of the semiconductor substrate of each element isolation is made uniform and the variation in characteristics is suppressed. .

  Even when the height of the element isolation is lowered to avoid the formation of a sidewall of the gate electrode material on the shoulder of the element isolation when processing the gate electrode, the transistor characteristics do not vary. It is possible to manufacture a high-quality semiconductor device without variations in the above.

Embodiment 2. FIG.
15 to 25 are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention. Hereinafter, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. In addition, about the same structural member as the case of Embodiment 1 mentioned above, the same code | symbol is attached | subjected for easy understanding. In the method of manufacturing a semiconductor device according to the present embodiment, first, as shown in FIG. 15, a silicon oxide film 12 serving as a first mask is formed on the surface of a silicon substrate 10 which is a semiconductor substrate by, for example, 5 nm by a thermal oxidation method. The film is formed to a thickness of about ˜15 nm.

  Next, as shown in FIG. 16, a silicon nitride film 16 serving as a second mask is deposited on the silicon oxide film 12 with a film thickness of, for example, about 50 nm to 250 nm. Here, the silicon oxide film 12 is formed as a stress relaxation film for avoiding the influence of stress on the silicon substrate 10 by forming the silicon nitride film 16 directly on the silicon substrate 10.

  Next, using the photoresist mask, the silicon nitride film 16 and the silicon oxide film 12 on the region where element isolation is to be formed are selectively removed by anisotropic etching. That is, first, as shown in FIG. 17, a photoresist 18 is formed on a portion of the silicon nitride film 16 corresponding to a region where no element isolation is formed. Next, as shown in FIG. 18, using the photoresist 18 as an etching mask, the silicon nitride film 16 and the silicon oxide film 12 in the region where element isolation is to be formed are removed by etching to form an opening 32 and an opening 34. At this time, the opening width of the silicon nitride film 16 and the silicon oxide film 12 is about 50 nm to 500 nm. The opening 32 corresponds to a shallow element isolation formation region, and the opening 34 corresponds to a deep element isolation formation region.

  Next, the photoresist 18 is removed, and the silicon substrate 10 in the region for forming the deep element isolation and the region for forming the shallow element isolation is anisotropically etched using the silicon nitride film 16 as an etching mask as shown in FIG. Excavation at a depth of about 50 nm to 300 nm. Thereby, a trench groove 36 for forming shallow element isolation and a trench groove 38 for forming deep element isolation are formed. In this step, the depth of etching the silicon substrate 10 is the depth of a shallow trench groove, which is a shallow element isolation depth. The depth is, for example, about 50 nm to 300 nm from the surface of the silicon substrate 10.

  Next, as shown in FIG. 20, the region including the trench groove 36 is covered with a photoresist 40 to such an extent that the trench groove 36 is filled. At this time, the photoresist 40 is prevented from entering the trench groove 38. Then, as shown in FIG. 21, the photoresist 40 is etched so that the photoresist 40 does not remain on the silicon nitride film 16 in the active region. At this time, if the etching amount of the photoresist 40 is small, the scraping amount of the silicon nitride film 16 in the region where the deep groove is formed is also small.

  Next, as shown in FIG. 22, using the photoresist 40 and the silicon nitride film 16 as a mask, the silicon substrate 10 in the trench groove 38 in the region where deep element isolation is to be formed is further excavated by etching. Here, when the silicon substrate 10 is etched, the photoresist 40 is also etched, but the film thickness of the photoresist 40 does not reach the silicon substrate 10 with respect to the etching amount of the silicon substrate 10. If the thicknesses of the silicon oxide film 12 and the silicon nitride film 16 are formed, the silicon substrate 10 at the bottom of the shallow trench groove 36 is not excavated.

  The amount of etching of the silicon substrate 10 in this step is the amount of difference in depth between the deep trench groove 38 and the shallow trench groove 36, and the amount of difference in depth between the deep element isolation and the shallow element isolation. It is. For example, the depth below the surface of the silicon substrate 10 of the deep trench 38 after etching is about 100 nm to 400 nm. Thereafter, the photoresist 40 is removed.

  Through the above steps, the deep element isolation formation trench groove 38 and the shallow element isolation formation trench groove 36 can be formed to a desired depth. In the present embodiment, the trench groove 36 and the trench groove 38 can be formed to a desired depth without causing a difference in height of the silicon nitride film 16. Further, here, a case where two types of trench grooves having different depths are formed has been described. However, three or more types of trench grooves having different depths can be formed by repeating the same process.

  Next, the sidewalls and bottom surfaces of the trench groove 36 and the trench groove 38 are oxidized to a depth of about 2 nm to 30 nm by a thermal oxidation method, and the damaged layer due to etching is removed. Further, as shown in FIG. 23, a silicon oxide film 26, which is an insulating film, is deposited to a thickness of 300 nm to 600 nm in a region including the trench groove 36 and the trench groove 38 by, for example, the CVD method. 38 is embedded. Then, the surface of the silicon oxide film 26 is planarized by a CMP (Chemical Mechanical Polishing) method using the silicon nitride film 16 as a stopper to remove the unnecessary silicon oxide film 26 on the silicon nitride film 16, and as shown in FIG. The silicon oxide film 26 is left only in the trench groove 36 and the trench groove 38.

  Thereafter, the silicon nitride film 16 is removed, and well formation and ion implantation for determining the threshold value of the transistor are performed by a conventionally known method. Further, the silicon oxide film 12 is removed and a deep element as shown in FIG. Isolation 28 and shallow element isolation 30 are completed. The completed deep element isolation 28 and shallow element isolation 30 have substantially the same height from the surface of the silicon substrate 10. After this, a gate oxide film is formed by a conventionally known method, a semiconductor element is formed by forming a gate electrode, a source / drain region, and the like, and a semiconductor device is completed by being connected to each other by a wiring layer. To do.

  As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, when forming trench grooves having different depths, the mask layer around the region for forming shallow element isolation, that is, the shallow trench groove, is formed. There is no difference in height from the surface of the silicon substrate 10 between the peripheral mask layer and the mask layer in the vicinity of the region for forming the deep element isolation, that is, the mask layer in the vicinity of the deep trench groove.

  Further, in the element isolation forming step, the mask layer around the region for forming shallow element isolation, that is, the mask layer around the shallow trench groove 36, and the mask layer around the region for forming deep element isolation, that is, the deep trench groove 38 Since there is no difference in height between the peripheral mask layer and the peripheral mask layer, silicon nitridation is performed at the boundary between the region where the shallow trench groove 36 is present and the region where the deep trench groove 38 is present during polishing by the CMP method. The silicon oxide film 26 is prevented from remaining on the film 16. Further, the silicon nitride film 16 in the vicinity of the boundary portion is further scraped due to the polishing by the CMP method, so that there is no difference in height between shallow element isolation and deep element isolation.

  Thereby, according to the manufacturing method of the semiconductor device according to the present embodiment, when the silicon oxide film 26 is buried in the trench groove 36 and the trench groove 38 which are element isolation formation regions, the silicon substrate 10 of the silicon oxide film 26 is filled. The film thickness from the surface can be made substantially equal. Therefore, the heights of the finally formed shallow element isolation 30 and deep element isolation 28 from the surface of the silicon substrate 10 can be reliably made substantially the same. Further, even when the silicon oxide film 12 on the silicon substrate 10 is a thin film, shallow element isolation and deep element isolation, that is, dual trench isolation can be surely formed.

  As a result, it is possible to eliminate the influence on the microfabrication due to the difference in height between the formed shallow element isolation 30 and deep element isolation 28 from the surface of the silicon substrate 10, and to manufacture a high-quality semiconductor device. it can. In particular, it is possible to reduce lithography exposure accuracy and etching variation when processing a gate electrode, and to reduce variation in transistor characteristics. Therefore, according to the method for manufacturing a semiconductor device according to the present embodiment, it is possible to manufacture a high-quality semiconductor device in which the height from the surface of the semiconductor substrate of each element isolation is made uniform and the variation in characteristics is suppressed. .

  Even when the height of the element isolation is lowered to avoid the formation of a sidewall of the gate electrode material on the shoulder of the element isolation when processing the gate electrode, the transistor characteristics do not vary. It is possible to manufacture a high-quality semiconductor device without variations in the above.

  As described above, the method of manufacturing a semiconductor device according to the present invention is a case of manufacturing a semiconductor device in which the degree of integration of the memory cell portion is significantly increased in a large capacity device having a memory cell portion and a peripheral circuit portion. Useful for.

It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 1 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention. It is process sectional drawing explaining the manufacturing process of the manufacturing method of the semiconductor device concerning Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 12 Silicon oxide film 14 Non-single crystal silicon film 16 Silicon nitride film 18 Photoresist 20 Photoresist 22 Trench groove 24 Trench groove 26 Silicon oxide film 28 Deep element isolation 30 Shallow element isolation 32 Opening 34 Opening 36 Trench groove 38 trench groove 40 photoresist

Claims (6)

Forming a first mask layer on the semiconductor substrate, which serves as an etching mask when etching the semiconductor substrate;
Forming a second mask layer having a high etching selectivity with respect to the first mask layer on the first mask layer;
Forming a third mask layer on the second mask layer, which serves as an etching mask when etching the first mask layer and the semiconductor substrate;
Etching and removing a region corresponding to a formation region of the first trench element isolation having a deep depth and a second trench element isolation having a shallow depth in the third mask layer and the second mask layer; ,
Etching the region corresponding to the first trench element isolation formation region in the first mask layer;
Using the third mask and the first mask as an etching mask, the formation region of the first trench element isolation in the semiconductor substrate is removed by etching to form a first trench groove for forming the first trench element isolation. And a process of
Etching and removing a region corresponding to the formation region of the second trench element isolation in the first mask layer;
Using the third mask layer as an etching mask, the region for forming the first trench element isolation and the second trench element isolation in the semiconductor substrate is removed by etching to form a second trench for forming the second trench element isolation. Forming a groove and further deepening the first trench groove;
Embedding an insulating film in the first trench groove and the second trench groove;
Planarizing the insulating film;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first mask layer is a stress relaxation film that relieves stress generated between the semiconductor substrate and the third mask layer. 3.   The first mask layer is a silicon oxide film layer, the second mask layer is a non-single crystal silicon film layer, and the third mask layer is a silicon nitride film layer. A method for manufacturing a semiconductor device according to 1 or 2. Forming a stress relaxation film on a semiconductor substrate for relaxing stress generated between the semiconductor substrate and the film formed on the semiconductor film;
Forming a mask layer to be an etching mask when etching the semiconductor substrate;
Etching and removing a region corresponding to a formation region of the first trench element isolation having a deep depth and a second trench element isolation having a shallow depth in the stress relaxation film and the mask layer;
Using the mask layer as an etching mask, the formation region of the first trench element isolation and the second trench element isolation in the semiconductor substrate is removed by etching, and the first trench groove for forming the first trench element isolation and the Forming a second trench groove for forming a second trench element isolation;
Embedding a photoresist only in the second trench groove;
Etching the semiconductor substrate in the first trench groove using the mask layer and the photoresist as an etching mask to further deepen the first trench groove;
Removing the photoresist;
Embedding an insulating film in the first trench groove and the second trench groove;
Planarizing the insulating film;
A method for manufacturing a semiconductor device, comprising: The step of embedding the photoresist;
Forming a photoresist on the mask layer and in a region around the second trench groove including the inside of the second trench groove;
Removing the photoresist on the mask layer to leave the photoresist only in the second trench groove;
The method of manufacturing a semiconductor device according to claim 4, comprising:   6. The method of manufacturing a semiconductor device according to claim 4, wherein the stress relaxation film is a silicon oxide film, and the mask layer is a silicon nitride film layer.

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