JP2005340602A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce poor breakdown voltage between wirings in the process for fabricating a semiconductor device employing a Cu wiring. <P>SOLUTION: The semiconductor device comprises a Cu film 260 becoming a plurality of Cu wirings employing Cu as a conductive material, a barrier metal film 240 arranged on each side face of a Cu film 260 becoming the plurality of Cu wirings, and a low-k film 220 arranged between the Cu films 260 becoming the plurality of Cu wirings through the barrier metal film 240. An area where the side face of the Cu film 260 becoming the Cu wiring is in contact with the barrier metal film 240 exists over a distance of 2 nm or longer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using Cu wiring.

  In recent years, new microfabrication techniques have been developed along with higher integration and higher performance of semiconductor integrated circuits (LSIs). The chemical mechanical polishing (CMP) method is one of them, and is frequently used in the LSI manufacturing process, particularly in the flattening of the interlayer insulating film, the formation of the metal plug, or the embedding process in the multilayer wiring forming process. (See, for example, Patent Document 1).

  In particular, recently, in order to achieve high-speed performance of LSIs, there has been a movement to replace the wiring technology from conventional aluminum (Al) alloy to low resistance Cu or Cu alloy (hereinafter collectively referred to as Cu). . Since Cu is difficult to finely process by the dry etching method frequently used in the formation of Al alloy wiring, Cu film is deposited on the insulating film subjected to the groove processing, and other than the portion embedded in the groove A so-called damascene method in which the Cu film is removed by CMP to form a buried wiring is mainly employed (see, for example, Patent Document 2). In general, a Cu film is formed by forming a thin seed layer by sputtering or the like and then forming a laminated film having a thickness of about several hundreds of nanometers by electrolytic plating.

Furthermore, recently, it has been studied to use a low-k film having a low relative dielectric constant as an interlayer insulating film. That is, by using a low-k film having a relative dielectric constant k of 3.5 or less from a silicon oxide film (SiO ₂ ) film having a relative dielectric constant k of about 4.2, parasitic capacitance between wirings is reduced. It has been tried. In addition, low-k film materials having a relative dielectric constant k of 2.5 or less have been developed, and many of these materials are porous materials having pores in the material. A method of manufacturing a semiconductor device having a multilayer wiring structure in which such a low-k film (or porous low-k film) and a Cu wiring are combined is as follows.

FIG. 13 is a process sectional view showing a method of manufacturing a semiconductor device having a multilayer wiring structure in which a conventional Low-k film and a Cu wiring are combined.
In FIG. 13, a method for forming a device portion or the like is omitted.
In FIG. 13A, a first insulating film 221 is formed on a silicon substrate 200 by a method such as chemical vapor deposition (CVD).
In FIG. 13B, a groove structure (opening H) for forming a Cu metal wiring or a Cu contact plug is formed in the first insulating film 221 by a photolithography process and an etching process.
In FIG. 13C, a barrier metal film 240, a Cu seed film, and a Cu film 260 are formed in this order on the first insulating film 221, and annealed at a temperature of 150 ° C. to 400 ° C. for about 30 minutes.
In FIG. 13D, the Cu film 260 and the barrier metal film 240 are removed by CMP to form a Cu wiring in the opening H that is a groove.
In FIG. 13E, a second insulating film 281 is formed after the surface of the Cu film 260 is subjected to reducing plasma treatment.
Furthermore, when forming multilayer Cu wiring, it is common to repeat these processes and to laminate. Here, most of the first insulating film 221 and the second insulating film 281 are Low-k films.

  In addition, dishing that is isotropically corroded in the center of the surface of the embedded metal wiring and is recessed like a dish, and the insulating film is polished in a portion with high wiring density to reduce the thickness of the metal wiring. A technique related to CMP for forming a wiring is disclosed in Patent Document 3, and a technique related to reducing plasma processing after CMP is disclosed in Patent Document 4.

In addition, a technique for forming a cap barrier only directly on an embedded metal wiring is disclosed (for example, see Patent Document 5).
US Pat. No. 4,944,836 JP-A-2-278822 JP 2002-198333 A JP 2002-110679 A JP 11-1111843 A

FIG. 14 is a cross-sectional view showing an example of semiconductor devices stacked by the method of FIG.
In FIG. 14, the SiC film 212, the low-k film 280, and the SiO ₂ film 222 are formed as the first insulating film, and after the SiC film 275 is formed on the Cu film 260 as the second insulating film, the low film is formed. An example in which a −k film 280 is formed is shown.
Even when the Cu wiring as shown in FIG. 14 is formed on the silicon wafer, it is difficult to ensure a sufficient withstand voltage when the space between the Cu wiring is 0.2 microns or less.
FIG. 15 is a diagram for explaining dielectric breakdown.
As shown in FIG. 15, in particular, when Cu-CMP is performed before forming the second insulating film, fine damage such as micro scratches is applied to the surface of the insulating film due to the abrasive grains contained in the CMP slurry, There was a problem that dielectric breakdown was induced from there. In addition, when a low-k film is used as the insulating film to be the CMP surface, the problem of deterioration of the withstand voltage is serious. This is because the mechanical strength of the low-k film is low and is easily damaged.

  An object of the present invention is to overcome such problems and reduce insulation breakdown voltage defects between wirings.

The semiconductor device of the present invention is
A plurality of conductive parts using a conductive material;
A barrier metal film disposed on each side surface of the plurality of conductive portions;
An insulating film disposed between the plurality of conductive portions via the barrier metal film;
With
A region where the side surface of the conductive portion and the barrier metal film are not in contact exists at a distance of 2 nm or more.

  By providing a non-contact region (recess) having a depth of 2 nm or more between the barrier metal film and the conductive portion, the distance between the conductive portion and the damaged layer on the surface of the insulating film can be increased.

Alternatively, the semiconductor device of the present invention is
A plurality of conductive parts using a conductive material;
A barrier metal film disposed on each side surface of the plurality of conductive portions;
An insulating film disposed between the plurality of conductive portions via the barrier metal film;
With
The region where the side surface of the conductive portion and the barrier metal film are not in contact exists at a distance of 1/100 or more of the height of the conductive portion.

  By providing a recess having a depth of 1/100 or more of the height of the conductive portion between the barrier metal film and the conductive portion, the distance between the conductive portion and the damaged layer on the surface of the insulating film can be increased.

Alternatively, the semiconductor device of the present invention is
A plurality of conductive parts using a conductive material;
A barrier metal film disposed on each side surface of the plurality of conductive portions;
An insulating film disposed between the plurality of conductive portions via the barrier metal film;
With
The conductive part has a region that is not in contact with the side surface of the barrier metal film inclined at 5 degrees or more.

  By providing a recess inclined at least 5 degrees with respect to the side surface of the barrier metal film between the barrier metal film and the conductive part, the distance between the conductive part and the damaged layer on the surface of the insulating film can be increased.

  In particular, the region is located at an upper portion of the side surface of the conductive part.

  Further, the upper surface of the conductive portion is a region not in contact with the barrier metal film.

  Since the dielectric breakdown drifts at a potential between the upper end of the wiring and the adjacent wiring, it is effective to increase the distance between the upper end of the wiring and the damaged layer on the surface of the insulating film.

  Further, copper (Cu) was used as the conductive material.

  With the Cu wiring that has come to be used with the miniaturization of the wiring, the distance between the wirings is small, which is particularly effective in such a case.

  Further, a material having a relative dielectric constant of 3.5 or less was used as the material for the insulating film.

  Along with the miniaturization of the wiring along with the Cu wiring, the low dielectric constant material that has been used has a small distance between the wirings and a small width of the insulating film. Since the width of the insulating film is reduced, dielectric breakdown is likely to occur. Therefore, it is particularly effective in such a case.

A method for manufacturing a semiconductor device of the present invention includes:
A first insulating film forming step of forming an insulating film on the substrate;
An opening forming step of forming an opening in the insulating film;
A barrier metal film forming step of forming a barrier metal film on the surface of the opening;
A deposition step of depositing a conductive material in the opening in which the barrier metal film is formed on the surface;
A polishing step of polishing the substrate surface on which the conductive material is deposited;
An etching step of etching the substrate surface polished by the polishing step using an etching solution;
A second insulating film forming step of forming an insulating film on the substrate surface etched by the etching step;
It is provided with.

  A recess can be formed in the conductive material deposited in the opening by etching the surface of the substrate polished by the polishing step using an etching solution. By forming the recess, the distance between the conductive material to be the conductive portion and the damaged layer on the surface of the insulating film can be increased.

  In the etching step, a mixed solution of an oxidizing agent and an organic acid is used as the etching solution.

  A desired recess can be efficiently formed by using a mixed liquid of an oxidizing agent and an organic acid as the etching liquid.

  Since the distance between the conductive portion and the damaged layer on the surface of the insulating film can be increased, the withstand voltage between the wirings by the conductive portion can be increased. Since the withstand voltage between the wirings can be increased, the reliability between the wirings can be improved.

Embodiment 1 FIG.
In the first embodiment, a method for solving the problem of the breakdown voltage degradation between narrow pitch Cu wirings by securing the distance of the region where the Cu film and the barrier metal film are not in contact with each other on the upper side wall of the damascene Cu wiring. Will be explained.
FIG. 1 is a cross-sectional view illustrating an example of the semiconductor device according to the first embodiment.
In FIG. 1, a SiO ₂ film 210 is formed on a substrate 200, and a first insulating film is formed on the SiO ₂ film 210. As the first insulating film, a low-k film 220 is formed on the SiC film 212 and the SiC film 212 serving as a base film, and a SiO ₂ film 222 is formed on the low-k film 220. The first insulating film is formed with a Cu film 260 to be a plurality of Cu wirings having a height R using Cu as a conductive material, and a barrier metal film 240 that covers the side and bottom surfaces of the Cu film 260 to be each Cu wiring. The Here, a recess 270 exists in the depth direction as a non-contact region where the upper end of the side surface of the Cu film 260 to be the Cu wiring is not in contact with the barrier metal film. Alternatively, and / or as the recess 270, a region where the side surface of the Cu film 260 serving as the Cu wiring is not in contact with the side surface of the barrier metal film 240 is inclined at an angle θ. An SiC film 275 is formed on the upper ends of the SiO ₂ film 222, the barrier metal film 240, and the upper surface of the Cu film 260 serving as a Cu wiring, and the SiC film 275 fills the recess 270. On the SiC film 275, the next low-k film 280 is formed for multilayer wiring.

  The problem of the breakdown voltage degradation between the Cu films 260 forming the narrow pitch Cu wiring is that the recess 270 is provided on the upper side wall of the damascene Cu wiring, and the distance at which the Cu film and the surface of the barrier metal film are not in contact by the recess 270. In the case of the low-k film 220 having a relative dielectric constant of 3.5, the distance r is 2 nm or more. Further, if the distance r in the depth direction of the recess 270 is 5 nm or more, the withstand voltage is high even if a low-k film having a relative dielectric constant of 2.9 is exposed on the CMP surface. Even if a low-k film having a relative dielectric constant of 2.5 is exposed on the CMP surface, a high withstand voltage can be secured.

  Alternatively, in the case of the low-k film 220 having a relative dielectric constant of 3.5 by providing a recess 270 on the side wall of the Cu film 260 to be a damascene Cu wiring, the surfaces of the Cu film and the barrier metal film are Cu wiring. This is solved by not contacting with a distance r that is 1/100 or more of the height R. Furthermore, if the depth r of the recess is separated by a distance of 1/50 or more of the Cu wiring height R, a low-k film having a relative dielectric constant of 2.9 is exposed on the CMP surface. If the dielectric strength is high and the depth r of the recess is 1/10 or more of the Cu wiring height R, a low-k film having a relative dielectric constant of 2.5 is exposed to the CMP surface. Even in such a case, it is possible to ensure a high withstand voltage.

  Alternatively, in the case of the low-k film 220 having a relative dielectric constant of 3.5 at the upper portion of the side wall of the Cu film 260 serving as the damascene Cu wiring, the angle θ between the Cu film surface and the barrier metal film surface has an angle of 5 degrees or more. It is desirable to be away. Furthermore, if the angle θ is 10 degrees or more, the dielectric breakdown voltage is high even if a low-k film having a relative dielectric constant of 2.9 is exposed on the CMP surface, and the angle θ is 25 degrees or more. As long as the low-k film having a relative dielectric constant of 2.5 is exposed on the CMP surface, a high withstand voltage can be secured. It is even better if both the angle θ and the distance r in the depth direction not in contact are provided.

A method for manufacturing the semiconductor device of FIG. 1 will be described below.
2, of the structure of the semiconductor device of FIG. 1 is a process cross-sectional view showing a from the underlying SiO ₂ film forming step to the SiO ₂ film formation process on the low-k film. Subsequent steps will be described later.

In FIG. 2A, as the SiO ₂ film forming step, for example, a base SiO ₂ film having a film thickness of 200 nm is deposited on the base body 200 by a CVD method to form the SiO ₂ film 210. Here, the film is formed by the CVD method, but other methods may be used. As the substrate 200, for example, a silicon wafer having a diameter of 300 mm is used. Here, the formation of the device portion is omitted.

In FIG. 2B, as a SiC film formation step, a SiC film 212 is formed by depositing a 30-nm-thick underlying SiC film using SiC on the SiO ₂ film 210 by a CVD method. Here, the film is formed by the CVD method, but other methods may be used. The SiC film 212 also has a function as an etching stopper. Since it is difficult to generate a SiC film, a SiOC film may be used instead of the SiC film. Alternatively, a SiCN film or a SiN film can be used.

In FIG. 2C, as a low-k film forming step, a low-k using a porous insulating material on the SiC film 212 formed by the SiC insulating film forming step formed on the substrate 200. The k film 220 is formed with a thickness of 200 nm. By forming the low-k film 220, an interlayer insulating film having a relative dielectric constant k lower than 3.5 can be obtained. As a material of the low-k film 220, for example, porous methyl silsesquioxane (MSQ) can be used. As the formation method, for example, an SOD (spin on selective coating) method in which a thin film is formed by spin-coating a solution and performing heat treatment can be used. Here, the spinner was formed at a rotation speed of 900 min ⁻¹ (900 rpm). This wafer was baked on a hot plate in a nitrogen atmosphere at a temperature of 250 ° C., and finally cured on a hot plate at a temperature of 450 ° C. in a nitrogen atmosphere for 10 minutes. A porous insulating film having a predetermined physical property value can be obtained by appropriately adjusting the MSQ material, formation conditions, and the like. For example, the density is 0.7 g / cm ³ and the relative dielectric constant k is 1.8. The composition ratio of Si, O, and C in the low-k film is as follows. A membrane 220 is obtained. Then, as a He plasma treatment step, the surface of the low-k film 220 is modified by helium (He) plasma irradiation in a CVD apparatus. By modifying the surface by He plasma irradiation, the adhesion between the low-k film 220 and a CVD-SiO ₂ film 222 as a cap film to be described later formed on the low-k film 220 can be improved. . The gas flow rate was 1.7 Pa · m ³ / s (1000 sccm), the gas pressure was 1000 Pa, the high frequency power was 500 W, the low frequency power was 400 W, and the temperature was 400 ° C. When the cap CVD film is formed on the low-k film, it is effective to improve the adhesion with the cap CVD film by subjecting the surface of the low-k film to plasma treatment. As types of plasma gas, ammonia (NH ₃ ), nitrous oxide (N ₂ O), hydrogen (H ₂ ), He, oxygen (O ₂ ), silane (SiH ₄ ), argon (Ar), nitrogen (N ₂ ) Among these, He plasma is particularly effective because it causes little damage to the low-k film. The plasma gas may be a mixture of these gases. For example, it is effective to use He gas mixed with other gases.

In FIG. 2 (d), the as SiO ₂ film forming step, said after the He plasma treatment, as a cap film, the SiO ₂ by a thickness of 50nm is deposited on the low-k film 220 by the CVD method, SiO ₂ A film 222 is formed. By forming the SiO ₂ film 222, the low-k film 220 that cannot be directly lithographically protected can be protected, and a pattern can be formed in the low-k film 220. Such cap CVD films include SiO ₂ films, SiC films, SiOC films, SiCN films, etc., but from the viewpoint of reducing damage, the SiO ₂ film is excellent, and from the viewpoint of reducing the dielectric constant, the SiOC film has improved breakdown voltage. From the viewpoint, the SiC film and the SiCN film are excellent. Furthermore, a laminated film of SiO ₂ film and SiC film, a laminated film of SiO ₂ film and SiCO film, or a laminated film of SiO ₂ film and SiCN film can be used. Further, a part or all of the cap CVD film may be removed by CMP in a planarization step described later. The dielectric constant can be further reduced by removing the cap film. The thickness of the cap film is preferably 10 nm to 150 nm, and 10 nm to 50 nm is effective in reducing the effective relative dielectric constant.

  In the above description, the interlayer insulating film in the lower layer wiring may not be a low-k film having a relative dielectric constant of 3.5 or less, but is particularly effective when a low-k film is included. This is because the low-k film is not only a material with a low withstand voltage but also easily damaged by the CMP process.

FIG. 3 is a process cross-sectional view illustrating the process from the opening forming process for wiring formation to the plating process. Subsequent steps will be described later.
In FIG. 3A, as the opening forming process, the opening 150 which is a wiring groove structure for producing a damascene wiring by a lithography process and a dry etching process is formed by using an SiO ₂ film 222, a low-k film 220, and a base SiC film. 212. An exposed SiO ₂ film 222 and a low-k film positioned below the exposed SiO ₂ film 222 with respect to the substrate 200 on which the resist film is formed on the SiO ₂ film 222 through a lithography process such as a resist coating process and an exposure process (not shown). 220 may be removed by anisotropic etching using the underlying SiC film 212 as an etching stopper, and then the opening SiC 150 may be formed by etching the underlying SiC film 212. By using the anisotropic etching method, the opening 150 can be formed substantially perpendicular to the surface of the substrate 200. For example, as an example, the opening 150 may be formed by a reactive ion etching method.

In FIG. 3B, as a barrier metal film forming step, a barrier metal film 240 using a barrier metal material is formed on the surface of the opening 150 and the SiO ₂ film 222 formed by the opening forming step. A tantalum nitride (TaN) film having a thickness of 2 nm and an atomic layer deposition (ALD method) or a sputtering method using a sputtering method, which is one of physical vapor deposition (PVD) methods, Then, a tantalum (Ta) film is deposited to a thickness of 1 nm by an atomic layer chemical vapor deposition (ALCVD method), and a Ta film is deposited to a thickness of 2 nm by a sputtering method to form a barrier metal film 240. By stacking the TaN film and the Ta film, the TaN film can prevent diffusion of Cu into the low-k film 220, and the Ta film can improve the adhesion of Cu. As a method for depositing the barrier metal material, the coverage can be improved by using an ALD method, an ALCVD method, a CVD method, or the like as compared with the case of using the PVD method.
The barrier metal film is preferably a Ta film, a TaN film, or a laminated film thereof. The film formation method of the barrier metal film is preferably a CVD method or an ALD method from the viewpoint of coverage, but is effective even with a PVD method such as the sputtering method described above.

  In FIG. 3C, as a seed film forming process, a barrier metal film 240 is formed by using a Cu thin film serving as a cathode electrode in an electroplating process as a next process as a seed film 250 by a physical vapor deposition (PVD) method such as sputtering. Are deposited (formed) on the inner wall of the opening 150 and the surface of the substrate 200. Here, the seed film 250 is deposited to a thickness of 75 nm.

  In FIG. 3D, as a plating process, a Cu film 260 is deposited on the surface of the opening 150 and the substrate 200 by an electrochemical growth method such as electrolytic plating using the seed film 250 as a cathode electrode. Here, a Cu film 260 having a thickness of 300 nm was deposited, and after the deposition, annealing treatment was performed at a temperature of 250 ° C. for 30 minutes.

  FIG. 4 is a process cross-sectional view showing a polishing process for planarization to a low-k film forming process as the second insulating film shown in FIG.

In FIG. 4A, as a polishing step, the Cu film 260, the seed film 250, and the barrier metal film 240, which become a wiring layer as a conductive portion deposited on the surface of the SiO ₂ film 222 by the CMP method, are removed by polishing. As a result, a buried structure as shown in FIG. Here, as an example, the CMP apparatus is an orbital method, and Momentum 300 manufactured by Novellus Systems Co., Ltd. is used. The CMP load is 1.03 × 10 ⁴ Pa (1.5 psi), the orbital rotation speed is 600 min ⁻¹ (600 rpm), the head rotation speed is 24 min ⁻¹ (24 rpm), and the slurry supply speed is 0.3 L / min (300 cc / Min), the polishing pad is a single layer pad made of polyurethane foam (IC1000 from Rodel), the CMP slurry is abrasive-free slurry for Cu (HS-C430-TU made by Hitachi Chemical), and the colloidal silica abrasive for barrier metal A grain slurry (HS-T605-8 manufactured by Hitachi Chemical Co., Ltd.) was used. CMP was performed under the above conditions to remove the Cu film and the barrier metal film outside the trench, thereby forming a damascene Cu wiring.

  In FIG. 4B, as the etching process, the substrate surface polished by the polishing process is etched using an etchant to form a recess 270. After the CMP step and immediately before entering the post-cleaning step, the rinse is performed using an aqueous solution in which 0.1% citric acid, 9% hydrogen peroxide, and 0.5% benzotriazole (BTA) are mixed as an etchant. Perform on the platen. Thereby, a recess 270 is formed at the upper end of the Cu wiring as shown in FIG. For example, by rinsing for 30 seconds, a recess having a depth direction distance r of 10 nm was formed at the upper end of the Cu wiring. The angle θ in the recess 270 between the Cu film 260 surface and the barrier metal film 240 surface is 30 degrees apart. A wafer that was not rinsed (FIG. 13) was also prepared as a comparative sample (reference) to compare the electrical characteristics with the rinsed wafer.

FIG. 5 is a conceptual diagram for explaining the configuration of an apparatus for forming a recess.
As shown in FIG. 5A, as part of the steps of the CMP process, in a rotary type CMP apparatus, the substrate 300 is carrier-mounted on the polishing pad 525 disposed on the platen 520 with the polishing surface facing downward. 510 holds. After the polishing process using the slurry is completed, the slurry on the polishing pad 525 is flushed with pure water and replaced, and then the etching solution is supplied from the supply nozzle 530 as the supply solution 540. As shown in FIG. 5B, the substrate 510 is rotated by rotating the carrier 510 as shown in the figure, and the platen 520 is also rotated. The supply liquid 540 is supplied into the surface of the substrate 300 by supplying the supply liquid 540 to the front of the substrate 300 (the position indicated by 540 in FIG. 5B) positioned ahead of the platen 520 in the rotation direction.

Alternatively, the recess may be formed as follows.
FIG. 6 is a conceptual diagram for explaining the configuration of another apparatus for forming a recess.
In FIG. 6, as a rinsing process step immediately after CMP, the substrate 300 is held by the four holders 710 arranged on the rotary table 720. Then, the rotating table 720 is rotated by the rotation of the rotating shaft 760, whereby the supply liquid 740 is supplied from the supply port 730 while rotating the substrate 300. For example, as the supply liquid 740, pure water is flowed for 15 seconds as rinse cleaning, then the etching liquid is flowed for 15 seconds, and pure water is again flowed for 30 seconds as rinse cleaning. When supplying the etching solution, 5 × 10 ⁻¹ Pa · m ³ / s (300 sccm) is flowed at a rotation speed of 200 min ⁻¹ (200 rpm).

Alternatively, the recess may be formed as follows.
FIG. 7 is a conceptual diagram for explaining the configuration of another apparatus for forming a recess.
In FIG. 7, as part of the post-CMP cleaning process step, the substrate 300 is held with the polishing surface polished by the four holders 610 disposed on the turntable 620 facing up. Then, the rotation table 620 is rotated by the rotation of the rotation shaft 660, so that the supply liquid 640 is supplied from the supply port 630 while rotating the substrate 300. The surface of the substrate 300 is brush scrubbed with a brush 650 that is rotated by a rotation shaft 652 that is disposed at the tip of an arm 654 that can be swung by a rotation shaft 656. For example, as the supply liquid 640, pure water is flowed for 15 seconds as rinse cleaning, then the etching liquid is flown for 15 seconds, and pure water is again flowed for 30 seconds as cleaning of the etching liquid. When supplying the etching solution, 5 × 10 ⁻¹ Pa · m ³ / s (300 sccm) is flowed at a rotation speed of 100 min ⁻¹ (100 rpm).

Alternatively, the recess may be formed as follows.
FIG. 8 is a conceptual diagram for explaining the configuration of another apparatus for forming a recess.
As part of the post-CMP cleaning process step, the substrate 300 is held with the polishing surface polished by the holder 710 shown in FIG. Then, the supply port 730 supplies the supply liquid 740 toward the upper surface while the substrate 300 is rotated by rotation of a rotation shaft (not shown), and the supply port 732 supplies the supply liquid 742 toward the lower surface. As shown in FIGS. 8A and 8B, the surface of the substrate 300 is sandwiched between a brush 750 and a brush 752 that rotate, and is scrubbed. For example, as in FIG. 7, pure water is supplied as the supply liquid 640 for 15 seconds as the rinse cleaning, then the etching solution is supplied for 30 seconds, and pure water is again supplied as the rinse cleaning for 30 seconds. When supplying the etching solution, 5 × 10 ⁻¹ Pa · m ³ / s (300 sccm) is flowed at a rotation speed of 100 min ⁻¹ (100 rpm). Here, the polishing surface (surface on which the recess is formed) is directed upward, but may be directed downward. In that case, an etchant may be flowed as the supply liquid 742.

Alternatively, the recess may be formed as follows.
FIG. 9 is a conceptual diagram for explaining the configuration of another apparatus for forming a recess.
As shown in FIG. 9A, as part of the steps of the CMP process, in an orbital rotating CMP apparatus, the substrate 300 is placed on the polishing pad 825 disposed on the platen 820 with the polishing surface facing downward. Carrier 810 holds. Then, after the polishing process using the slurry is completed, the slurry on the polishing pad 825 is flushed with pure water and replaced, and then the platen 820 is rotated orbitally as shown in the figure as shown in FIG. 9B. In addition, the etching solution is supplied from the lower side of the polishing pad 825 as a supply solution 840. By supplying the supply liquid 840 from below the polishing pad 825, the supply liquid 840 is supplied into the surface of the substrate 300. The supplied liquid 840 is discharged from the outer peripheral portion as the platen 820 rotates.

As described above, the formation of these recess structures can be achieved by using an etchant as a part of a CMP process step, a rinse process step immediately after CMP, and a post-CMP cleaning process step. As shown in FIGS. 5 and 9, it is also possible to rinse the polishing surface while flowing an etching solution on the CMP platen, or while brush scrubbing in the post-cleaning process as shown in FIGS. It is also possible by flowing an etching solution. It is also possible to simply immerse in an etching solution. The etching solution is preferably a mixed aqueous solution of an oxidizing agent and an organic acid. The oxidizing agent is preferably hydrogen peroxide, and the organic acid is preferably a hydroxy acid (an organic acid containing an OH group) or a carboxylic acid (an organic acid containing a COOH group), and the hydroxycarboxylic acid (an OH group and a COOH group in one molecule). Organic acids) are most desirable. For example, citric acid, malic acid, succinic acid, tartaric acid, phthalic acid, malonic acid, maleic acid, fumaric acid, lactic acid, pimelic acid, adipic acid, glutaric acid, oxalic acid, salicylic acid, glucholic acid, benzoic acid, butyric acid, Yoshi Examples include herbic acid, propionic acid, acetic acid, formic acid and the like. The concentration of the chemical can be optimized so as to be the above-mentioned distance and angle. The concentration of the organic acid can be optimized within the range of 0.01 to 1%. The concentration of the oxidizing agent can be optimized within a range of 1 to 30%.
In order to control the depth of etching, it is effective to add an anticorrosive or a surfactant. As the anticorrosive agent, beizotriazole (BTA), imidazole, or a derivative thereof is desirable. As the surfactant, polyacrylic acid or ammonium polyacrylate is desirable. The concentration of the anticorrosive can be optimized within the range of 0.01 to 0.5%. The surfactant concentration can be optimized within the range of 0.001 to 1%.

In FIG. 4C, ammonia (NH ₃ ) plasma treatment is performed in the CVD apparatus as a reducing plasma treatment step. By this treatment, the Cu surface complex formed by the reaction with the slurry during Cu-CMP in the planarization step in FIG. 4A is reduced, and the residual organic substances present on the cap SiO ₂ film are removed. Can do. By this treatment, the Cu surface complex formed by reaction with the slurry during Cu-CMP is reduced, and residual organic substances on the cap SiO 2 film are also removed, so that the withstand voltage is improved. As the reducing plasma, ammonia plasma or hydrogen (H ₂ ) plasma is effective, and ammonia plasma is particularly preferable because of easy handling of gas in the processing apparatus.

In the reducing plasma processing step, a semiconductor substrate serving as the base 200 is placed on a substrate holder whose temperature serving as the lower electrode is controlled to 400 ° C. inside a chamber in a CVD apparatus (not shown). Then, gas is supplied into the chamber from the upper electrode. The gas flow rate to be supplied was 11.8 Pa · m ³ / s (7000 sccm). Plasma is generated using a high frequency power source between the upper electrode and the lower electrode inside the chamber evacuated to a gas pressure of 233 Pa by a vacuum pump. The high frequency power was 560 W, the low frequency power was 250 W, and the processing time was 10 seconds.

Then, as the SiC film forming process which is a part of the second insulating film forming process in the next layer, an SiC film 275 having a thickness of 30 nm is formed at the temperature of 400 ° C. in the same CVD apparatus subjected to the reducing plasma treatment. . The SiC film 275 is also embedded in the recess 270. The SiC film 275 functions as a diffusion preventing film, and by forming this SiC film 275, diffusion of Cu can be prevented. In addition to the SiC film 275 formed by the CVD method, a SiCN film, a SiCO film, a SiN film, or a SiO ₂ film can be used.

  In FIG. 4D, the low-k film forming process is a low dielectric constant film having a relative dielectric constant lower than that of the SiC film 275 on the SiC film 275, as in the process described with reference to FIG. Then, a low-k film 280 using a porous insulating material is formed. Thereafter, multilayer wiring is sequentially formed as necessary.

  A protective film and a pad electrode were formed on two types of wafers, a wafer having these recesses and a wafer having no recesses, and a dielectric strength test between Cu wirings was performed. With respect to the above-described two types of wafers, the withstand voltage was examined in a structure in which the width of the Cu wiring was 0.13 micrometers and the space between the wirings was 0.13 micrometers. As a result, the dielectric breakdown voltage was hardly deteriorated in the wafer subjected to the rinsing process of the present invention. With a yield of 99% or more, there was a breakdown voltage of 2MV / cm or more. On the other hand, the withstand voltage of the same wiring structure was reduced to 50% in the wafer not subjected to the above-described rinsing (recess formation). As a result of observing the deteriorated Cu wiring with TEM, breakdown as shown in FIG. 15 was observed. That is, dielectric breakdown occurred from the upper end of Cu. On the other hand, no dielectric breakdown was found in the wafer subjected to the rinsing process (recess formation). In other words, it is considered that the rinsed wafer prevented the electric field diffusion of Cu at the upper end portion of the wiring and suppressed the breakdown voltage.

FIG. 10 is a conceptual diagram for explaining that the distance between the damaged layer of CMP and the upper end of the Cu film is separated by the recess.
As shown in FIG. 10, the decrease in the dielectric breakdown voltage can be suppressed because the distance between the CMP damage layer and the upper end of the Cu film is separated by the recess, thereby suppressing the Cu electric field diffusion. it is conceivable that.
FIG. 11 is a diagram showing the results of examining the relationship between the recess depth and the withstand voltage.
As a result of investigating the relationship between the depth of the recess and the withstand voltage, it has been found that it is effective that the depth of the recess is 2 nm or more. Further, if the thickness was 5 nm or more, the effect was great. If the recess is 20 nm or more, the effect of insulation resistance is enhanced, but there is a problem that an increase in wiring resistance cannot be ignored. Therefore, the depth of the recess is 1/100 or more of the height of the Cu wiring, and 1/5. The following is desirable. In the case of the upper end portion of the Cu wiring, it is desirable that the Cu film surface and the barrier metal film surface be separated from each other with an angle of 5 degrees or more.
The same effect could be confirmed even when this experiment was carried out on a wafer with a device mounted. This is effective not only in the first Cu wiring layer but also in the second Cu wiring layer, and also in the third and higher Cu wiring layers.
As the low-k material, the same result was obtained even when using a SiOC film formed by HSQ (Hydrogen Silsesquioxane), polymer, or CVD.

Embodiment 2. FIG.
FIG. 12 is a cross-sectional view illustrating an example of the semiconductor device in the second embodiment.
As shown in FIG. 12, the shape of the recess 270 may extend over the entire surface of the Cu film 260 that becomes the Cu wiring, even at the upper end of the Cu film 260 that becomes the Cu wiring.

  In each of the above embodiments, when the relative dielectric constant k is 2.6 or less, it is desirable that the sidewall of the low-k film is covered with a CVD film having a thickness of 20 nm or less. The reason is that when the relative dielectric constant is 2.6 or less, the film is often a porous film, and pore sealing needs to be performed on the side wall of the Cu wiring. This is particularly necessary when a barrier metal film is formed by the aforementioned ALD method or CVD method. As the kind of the pore sealing CVD film, a SiC film, a SiCN film, a SiCO film, and a SiN film are desirable. In particular, a SiC film is optimal from the viewpoint of a low dielectric constant.

  In the above description, the above embodiments are particularly effective when the wiring pitch is 300 nm or less. It is more effective when it is 200 nm or less. As the wiring pitch decreases, the problem of dielectric breakdown increases, and the above-described embodiments become more effective as the wiring pitch decreases.

  In the above description, the barrier metal is not limited to Ta and TaN, but a nitride film of a refractory metal such as TaCN (tantalum carbonitride), WN (tungsten nitride), WCN (tungsten carbonitride), or TiN (titanium nitride) A carbon nitride film may be used. Alternatively, titanium (Ti), WSiN, or the like may be used.

  Here, as a material of the wiring layer in each of the above embodiments, a material mainly containing Cu used in the semiconductor industry, such as a Cu—Sn alloy, a Cu—Ti alloy, and a Cu—Al alloy, is used in addition to Cu. The same effect can be obtained.

  In the case of forming a multilayer wiring structure or the like, the substrate 200 in each drawing is formed by forming a lower wiring layer and an insulating film.

In each of the embodiments described above, the material of the porous insulating film is not limited to the MSQ as the porous dielectric thin film material, and other porous inorganic insulating film materials and porous organic insulating film materials are used. The same effect can be obtained.
In particular, when the above-described embodiments are applied to a porous low dielectric constant material, a remarkable effect can be obtained as described above. Examples of materials that can be used as the material for the porous insulating film in each of the above embodiments include various silsesquioxane compounds, polyimide, fluorocarbon, parylene, benzocyclobutene, and the like. Various insulating materials can be mentioned.

  The embodiments have been described above with reference to specific examples. However, the present invention is not limited to these specific examples.

  For example, the substrate 200 on which an interlayer insulating film is formed in each embodiment can have various semiconductor elements or structures not shown. Further, an interlayer insulating film may be further formed on a wiring structure having an interlayer insulating film and a wiring layer instead of the semiconductor substrate. The opening may be formed so that the semiconductor substrate is exposed, or may be formed on the wiring structure.

  Further, the film thickness of the interlayer insulating film and the size, shape, number, and the like of the opening can be appropriately selected from those required in the semiconductor integrated circuit and various semiconductor elements.

  In addition, any semiconductor device manufacturing method that includes the elements of the present invention and whose design can be changed as appropriate by those skilled in the art is included in the scope of the present invention.

  In addition, for the sake of simplicity of explanation, techniques usually used in the semiconductor industry, such as a photolithography process, cleaning before and after processing, are omitted, but it goes without saying that these techniques are included.

4 is a cross-sectional view illustrating an example of a semiconductor device in Embodiment 1. FIG. FIG. ₂ is a process cross-sectional view illustrating a process from a lower SiO ₂ film formation process to a SiO ₂ film formation process on a low-k film in the configuration of the semiconductor device of FIG. 1. It is process sectional drawing which shows from the opening part formation process for wiring formation to a plating process. It is process sectional drawing which shows from the grinding | polishing process which planarizes to the low-k film | membrane formation process as a 2nd insulating film shown in FIG. It is a conceptual diagram for demonstrating the structure of the apparatus which forms a recess. It is a conceptual diagram for demonstrating the structure of another apparatus which forms a recess. It is a conceptual diagram for demonstrating the structure of another apparatus which forms a recess. It is a conceptual diagram for demonstrating the structure of another apparatus which forms a recess. It is a conceptual diagram for demonstrating the structure of another apparatus which forms a recess. It is a conceptual diagram for demonstrating that the distance of the damaged layer of CMP and the upper end part of Cu film | membrane leaves | separates by a recess. It is a figure which shows the result of having investigated the relationship between the depth of a recess and a withstand voltage. FIG. 6 is a cross-sectional view illustrating an example of a semiconductor device in a second embodiment. It is process sectional drawing which shows the manufacturing method of the semiconductor device which has the multilayer wiring structure which combined the conventional Low-k film | membrane and Cu wiring. It is sectional drawing which shows an example of the semiconductor device laminated | stacked by the method of FIG. It is a figure for demonstrating a dielectric breakdown.

Explanation of symbols

150 Opening 200 Base 210, 222 SiO ₂ film 212, 275 SiC film 220, 280 Low-k film 221, 281 Insulating film 240 Barrier metal film 250 Seed film 260 Cu film 270 Recess 300 Substrate 510, 810 Carrier 520, 820 Platen 525, 825 Polishing pad 530 Supply nozzle 540, 640, 740, 742, 840 Supply liquid 610, 710 Holder 620, 720 Rotary table 630, 730 Supply port 650, 750, 752 Brush 652, 656, 660, 760 Rotating shaft 654 arm

Claims (9)

A plurality of conductive parts using a conductive material;
A barrier metal film disposed on each side surface of the plurality of conductive portions;
An insulating film disposed between the plurality of conductive portions via the barrier metal film;
With
A semiconductor device characterized in that a region where the side surface of the conductive portion and the barrier metal film are not in contact exists at a distance of 2 nm or more. A plurality of conductive parts using a conductive material;
A barrier metal film disposed on each side surface of the plurality of conductive portions;
An insulating film disposed between the plurality of conductive portions via the barrier metal film;
With
A region where the side surface of the conductive portion and the barrier metal film are not in contact exists at a distance of 1/100 or more of the height of the conductive portion. A plurality of conductive parts using a conductive material;
A barrier metal film disposed on each side surface of the plurality of conductive portions;
An insulating film disposed between the plurality of conductive portions via the barrier metal film;
With
2. A semiconductor device according to claim 1, wherein a side surface of the conductive portion has a region which is not in contact with the side surface of the barrier metal film with an inclination of 5 degrees or more.   The semiconductor device according to claim 1, wherein the region is located on an upper side surface of the conductive portion.   The semiconductor device according to claim 4, wherein an upper surface of the conductive portion is a region not in contact with the barrier metal film.   The semiconductor device according to claim 1, wherein the conductive material is copper (Cu).   7. The semiconductor device according to claim 1, wherein a material having a relative dielectric constant of 3.5 or less is used as the material of the insulating film. A first insulating film forming step of forming an insulating film on the substrate;
An opening forming step of forming an opening in the insulating film;
A barrier metal film forming step of forming a barrier metal film on the surface of the opening;
A deposition step of depositing a conductive material in the opening in which the barrier metal film is formed on the surface;
A polishing step of polishing the substrate surface on which the conductive material is deposited;
An etching step of etching the substrate surface polished by the polishing step using an etching solution;
A second insulating film forming step of forming an insulating film on the substrate surface etched by the etching step;
A method for manufacturing a semiconductor device, comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein in the etching step, a mixed liquid of an oxidizing agent and an organic acid is used as the etching liquid.

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