CN121690230A - Communication methods and devices based on LDPC codes - Google Patents

Abstract

A communication method and a communication device based on LDPC codes, wherein equipment can be used for encoding or decoding based on an LDPC matrix, the LDPC matrix is determined based on an LDPC base matrix, a lifting value Zc and a translation value of the base matrix, wherein the translation value of the base matrix is determined based on a second row sequence, a second column sequence and Zc, elements of the second row sequence are in one-to-one correspondence with rows of the base matrix, elements of the second column sequence are in one-to-one correspondence with columns of the base matrix, the second row sequence is determined based on a first row sequence, the second column sequence is determined based on a first column sequence, the number of elements of the first row sequence is smaller than the number of elements of the second row sequence, and the number of elements of the first column sequence is smaller than the number of elements of the second column sequence. The method can flexibly construct the translation value of the base matrix and support a wider set of lifting values.

Description

Communication method and communication device based on LDPC code

Technical Field

The present application relates to the field of encoding, and more particularly, to a communication method and a communication apparatus based on an LDPC code.

Background

In the field of channel coding, low Density Parity Check (LDPC) codes are one of the most well-established and widely-used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes, and due to the unique structure of the check matrix, the encoding can be realized by using a simple feedback shift register, so that the encoding complexity of the LDPC codes is reduced.

The translation values given for the QC-LDPC code in the current protocol (see the multiple sets of translation values shown in table 2 in the specific embodiment) depend on random search, and cannot theoretically guarantee the ring property of the LDPC code, and in addition, the translation values in the QC-LDPC code shown in table 2 are only applicable to the exponentially increasing lifting value sets (see the multiple sets of lifting value sets shown in table 1 in the specific embodiment) and are not applicable to other types of lifting value sets.

Disclosure of Invention

The embodiment of the application provides a communication method and a communication device based on LDPC codes, which can flexibly construct translation values of a base matrix and support a wider lifting value set.

In a first aspect, a communication method based on an LDPC code is provided, where the method may be performed by a sender device, where the "sender device" in the present application may refer to the sender device itself (e.g. a network device, a terminal device), a component in the sender device (e.g. a processor, a chip, or a chip system, etc.), or may be a logic module or software capable of implementing all or part of the functions of the sender device, where the method is not specifically described.

The method comprises the steps of obtaining an information bit sequence, determining an LDPC matrix, wherein the LDPC matrix is determined based on an LDPC base matrix, a lifting value Zc and a translation value of the base matrix, the translation value of the base matrix is determined based on a second row sequence, a second column sequence and a lifting value Zc, the number of elements of the second row sequence is equal to the number of rows of the base matrix, the elements of the second row sequence are in one-to-one correspondence with the rows of the base matrix, the number of elements of the second column sequence is equal to the number of columns of the base matrix, the elements of the second column sequence are in one-to-one correspondence with the columns of the base matrix, the second row sequence is determined based on a first row sequence, the number of elements of the first row sequence is smaller than the number of elements of the second row sequence, the number of elements of the first column sequence is smaller than the number of elements of the second column sequence, and encoding the information bit sequence according to the LDPC matrix to obtain a codeword sequence.

The technical scheme provides a method for acquiring a second row/column sequence based on a first row/column sequence and determining a base matrix translation value based on the second row/column sequence and a lifting value. In the method, the translation value is not dependent on random search, but can be flexibly constructed through the determined parameters, so that the circle property of the LDPC code can be theoretically ensured.

In a second aspect, a communication method is provided, which may be performed by a receiving end device, where the "receiving end device" in the present application may refer to the receiving end device itself (e.g. a network device, a terminal device), a component in the receiving end device (e.g. a processor, a chip, or a chip system, etc.), or a logic module or software that can implement all or part of the functions of the receiving end device, without being specifically described.

The method comprises the steps of obtaining a symbol sequence, determining an LDPC matrix, wherein the LDPC matrix is determined based on an LDPC base matrix, a lifting value Zc and a translation value of the base matrix, the translation value of the base matrix is determined based on a second row sequence, a second column sequence and a lifting value Zc, the number of elements of the second row sequence is equal to the number of rows of the base matrix, the elements of the second row sequence are in one-to-one correspondence with the rows of the base matrix, the number of elements of the second column sequence is equal to the number of columns of the base matrix, the elements of the second column sequence are in one-to-one correspondence with the columns of the base matrix, the second row sequence is determined based on a first row sequence, the number of elements of the first row sequence is smaller than the number of elements of the second row sequence, the number of elements of the first column sequence is smaller than the number of elements of the second column sequence, and decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

The advantageous effects of the second aspect are described with reference to the first aspect, and are not described here again.

In certain implementations of the first or second aspect, the translation value of the 1 element located in the row i and the column j in the base matrix is summed based on t first values, where t is a positive integer, where the first values are determined based on R (i), C (j), zc, p and s corresponding to the first values, R (i) is an element corresponding to the row i in the second row sequence, C (j) is an element corresponding to the column j in the second column sequence, s is an integer between 1 and t, and p is a prime number corresponding to Zc.

In the above technical solution, in order to theoretically guarantee the ring properties (such as ring performance and ring existence) of the LDPC code, the shift value of the base matrix may be determined based on the above parameters.

In certain implementations of the first or second aspect, p is a prime number base of Zc, or p is a maximum prime number that can divide the maximum lifting value in all lifting value sets, or p is a prime number that can divide any lifting value in all lifting value sets, or p is a maximum or minimum value in prime number bases corresponding to all lifting value sets.

In certain implementations of the first or second aspect, the translation value SV _i,j of the 1 element in row i, column j in the base matrix satisfies the following equation:

Where s is a positive integer, u _s+v_s＝s+1,u_s and v _s are both positive integers, Z _{id_s} is determined based on Zc, p and s, or Z _{id_s}＝1,k_s is a positive integer multiple of p ^s-1. For example, t=2 or 3.

In the above technical solution, the characteristics related to the ring can be theoretically ensured. Different terms of the calculation formula can ensure different circle properties. Wherein s=1 in the above equation of SV _i,j is to ensure that 4 turns do not exist, s=2 is to ensure that the number of 6 turns is small, and that 6 turns do not exist if Zc is sufficiently large, s=3 is to ensure that the number of 8 turns is small, and that 8 turns do not exist if Zc is sufficiently large, and so on, and s is greater than or equal to 3 to further ensure the turn property.

In certain implementations of the first or second aspect, the translation value SV _i,j of the 1 element in row i, column j in the base matrix satisfies the following equation:

Where N _s is the value stored in the table s at the position corresponding to row R1 and column C1, row R1 is the row associated with R (i) in table s, column C1 is the column associated with C (j) in table s, s is a positive integer, Z _{id_s} is determined based on Zc, p and s, or Z _{id_s}＝1,k_s is a positive integer multiple of p ^s-1.

In the above technical solution, the parameter N _s for determining the translation value may be obtained by looking up a table, and the obtained translation value may theoretically ensure the characteristics related to the circle. Wherein, t in the calculation formula takes different values, so that different circle properties can be ensured. Wherein s=1 in the above equation of SV _i,j is to ensure that 4 turns do not exist, s=2 is to ensure that the number of 6 turns is small, and that 6 turns do not exist if Zc is sufficiently large, s=3 is to ensure that the number of 8 turns is small, and that 8 turns do not exist if Zc is sufficiently large, and so on, and s is greater than or equal to 3 to further ensure the turn property.

In certain implementations of the first or second aspect, the value N _s stored in the table s satisfies the following formula:

Wherein u _s+v_s＝s+1,u_s and v _s are both positive integers.

In the above technical solution, a specific calculation method of the stored value N _s in the predefined form s is given, and the calculation method can theoretically guarantee the characteristics related to the circle.

In certain implementations of the first or second aspect, all rows of the table s are in one-to-one correspondence with elements in the second row sequence, and all columns of the table s are in one-to-one correspondence with elements in the second column sequence.

In certain implementations of the first or second aspect, Z _{id_s} is determined based on Zc, p, and s, and Z _{id_s} satisfies the following formula:

z_{id_s}＝mod(mod(Zc,p^s+1),p^s)

the above calculation can theoretically guarantee the characteristics related to the circle.

In certain implementations of the first or second aspect, the base matrix is determined based on a split sequence θ, where θ (i) is equal to a first character, indicates that row i of the base matrix is not associated with any row of the base matrix, otherwise indicates that row i of the base matrix is associated with row θ (i) of the base matrix, and θ (i) is less than i, the first row sequence consists of a plurality of elements that are in one-to-one correspondence with the plurality of rows of the base matrix, the plurality of rows θ (i) is equal to all rows i of the first character, the element in the second row sequence that corresponds to row i1 is equal to the element in the first row sequence that corresponds to row i1, the element in the second row sequence that corresponds to row i2 is equal to the element in the second row sequence that corresponds to row θ (i 2), wherein θ (i 1) is equal to the first character, θ (i 2) is not equal to the first character, or the first row sequence is composed of a plurality of elements in one-to-one correspondence with the core rows of the base matrix, the element corresponding to row i1 in the second row sequence is equal to the element corresponding to row i1 in the first row sequence, the element corresponding to row i3 in the second row sequence is equal to the element corresponding to row i3 'in the first row sequence, the element corresponding to row i2 in the second row sequence is equal to the element corresponding to row θ (i 2) in the second row sequence, wherein row i1 is any row in the core of the base matrix, row i3 is any row of all rows except the core rows where θ (i) is equal to the first character, i3' is smaller than i3, and θ (i 1) is equal to the first character, θ (i 2) is not equal to the first character.

In the technical scheme, the first sequence does not contain the element corresponding to the line i of which θ (i) is not equal to the first character, so that the translation values of the child node and the father node are guaranteed to have correlation, and the QC-level meta-elimination expansion can be realized.

In certain implementations of the first or second aspect, the first row sequence is determined based on a split sequence, wherein a plurality of elements in the first row sequence are each included in the split sequence, a first element in the first row sequence is a minimum value in the split sequence, and an element corresponding to a first row in the first row sequence is smaller than an element corresponding to a second row, and a row number of the first row is smaller than a row number of the second row.

In the above technical scheme, only the splitting sequence can be stored, the first row sequence can be determined based on the splitting sequence, so that the splitting process can keep the QC structure, and the hardware implementation is simpler.

In certain implementations of the first aspect or the second aspect, the first column sequence includes a plurality of elements, the plurality of elements are in one-to-one correspondence with a core column of the base matrix, elements corresponding to a column j1 in the second column sequence are equal to elements corresponding to a column j1 in the first column sequence, and the column j1 is any column in the core column.

In certain implementations of the first or second aspect, the base matrix is a cyclic shift space-coupled low-density parity-check SC-LDPC base matrix, the sub-codes of the base matrix have a coupling length of L, a coupling width of w, a number of rows of each base matrix block in the sub-codes is m and a number of columns is n, the first row sequence is composed of (m× (w+c)) elements, the elements in the first row sequence are in one-to-one correspondence with the first (m× (w+c)) rows of the base matrix, c is an integer, the elements in the first column sequence are composed of (n× (w+c)) elements, the elements in the first column sequence are in one-to-one correspondence with the first (n×w)) elements of the base matrix, the second row sequence is composed of (m×l)) elements, the elements in the second row sequence are obtained based on cyclic multiplexing of the first row sequence, and the elements in the second column sequence are obtained based on cyclic multiplexing of the first column sequence.

In the above technical solution, a specific set of rules for generating the translation values is provided, and the translation values of the base matrix under the condition of any more subcodes can be obtained according to the rules.

Illustratively, c is equal to-1, -2, 0,1, or 1.

In a third aspect, a communications device is provided for performing the method provided by any one of the aspects or implementations thereof. In particular, the apparatus may comprise means and/or modules, such as a processing unit and/or a transceiver unit, for performing the method provided in any of the above aspects or implementations thereof.

In one implementation, the apparatus is a sender device or a receiver device. When the apparatus is a transmitting end device or a receiving end device, the transceiver unit may be a transceiver, or an input/output interface, or a communication interface, and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input/output interface is an input/output circuit.

In another implementation, the apparatus is a chip, a system-on-chip, or a circuit for use in a transmitting device or a receiving device. When the apparatus is a chip, a system-on-chip or a circuit used in a transmitting end device or a receiving end device, the transceiver unit may be an input/output interface, an interface circuit, an output circuit, an input circuit, a pin, or a related circuit on the chip, the system-on-chip or the circuit, and the processing unit may be at least one processor, a processing circuit, or a logic circuit.

In a fourth aspect, there is provided a communications device comprising a memory for storing a program, and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided by any one of the aspects or implementations thereof.

In one implementation, the apparatus is a sender device or a receiver device.

In another implementation, the apparatus is a chip, a system-on-chip, or a circuit for use in a transmitting device or a receiving device.

In a fifth aspect, there is provided a communications apparatus comprising at least one processor and a communications interface, the at least one processor being configured to obtain a computer program or instructions stored in a memory via the communications interface to perform the method provided by any one of the aspects or embodiments thereof. The communication interface may be implemented in hardware or software.

In one implementation, the apparatus further includes the memory.

In a sixth aspect, a processor is provided for performing the method provided in the above aspects.

The operations such as transmitting and acquiring/receiving, etc. related to the processor may be understood as operations such as outputting and receiving, inputting, etc. by the processor, and may be understood as operations such as transmitting and receiving by the radio frequency circuit and the antenna, if not specifically stated, or if not contradicted by actual function or inherent logic in the related description, which is not limited by the present application.

In a seventh aspect, a computer readable storage medium is provided, the computer readable storage medium storing program code for execution by a device, the program code comprising instructions for performing the method provided by any one of the aspects or implementations thereof.

In an eighth aspect, there is provided a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method provided by any one of the aspects or implementations thereof.

In a ninth aspect, a chip is provided, the chip including a processor and a communication interface, the processor reading instructions stored on a memory through the communication interface, and performing the method provided in any one of the above aspects or implementation manner. The communication interface may be implemented in hardware or software.

Optionally, as an implementation manner, the chip further includes a memory, where a computer program or an instruction is stored in the memory, and the processor is configured to execute the computer program or the instruction stored in the memory, where the processor is configured to execute the method provided in any one of the above aspects or implementation manner.

When the method provided by the application is executed by the chips, the application is not limited to the number of the chips for realizing the method of the application, and the method can be executed by one chip or can be executed by 2 or more chips. When the number of chips for implementing the method of the application is 2 or more, the chip manufacturer is not limited, and the chips can be the same manufacturer or different manufacturers.

In a tenth aspect, there is provided a computer program which, when run on a computer, causes the method provided by any one of the aspects or implementations thereof described above to be performed.

In an eleventh aspect, a communication system is provided comprising at least one of the sender device or the receiver device described above.

Drawings

Fig. 1 is a schematic diagram of a network architecture to which embodiments of the present application may be applied.

Fig. 2 is a schematic diagram of a check matrix H of LDPC.

Fig. 3 is a Tanner graph of an LDPC check matrix H.

Fig. 4 is a schematic diagram of the structure of a check matrix.

Fig. 5 is a schematic diagram of an information transmission flow.

Fig. 6 is a schematic flow chart of a communication method 600 based on an LDPC code provided by the present application.

Fig. 7 is a schematic diagram of the correspondence of the table s with the second row (column) sequence.

Fig. 8 is a schematic diagram of a translation value of a QC-SC-LDPC base matrix determined based on the method proposed by the present application.

Fig. 9 is a schematic block diagram of a communication apparatus 1000 provided in an embodiment of the present application.

Fig. 10 is a schematic block diagram of a communication device 1100 according to an embodiment of the present application.

Detailed Description

In order to facilitate understanding of the embodiments of the present application, the following description is made before describing the embodiments of the present application.

"Used to indicate" or "indicating" may include both used to indicate directly and used to indicate indirectly, or "used to indicate" or "indicated" may be indicated explicitly and/or implicitly. The first, second, etc. various numbers are merely for convenience of description and are not intended to limit the scope of embodiments of the application, e.g., distinguishing between different messages, different information, etc. The "pre-defining" may be implemented by pre-storing corresponding codes, tables, or other means for indicating relevant information in the device, and the present application is not limited to the specific implementation manner. Reference to "protocol" may refer to a standard protocol in the field of communications, and may include, for example, long term evolution (long term evolution, LTE) protocols, new Radio (NR) protocols, and related protocols for use in future communication systems, as the application is not limited in this regard. Words "exemplary," "such as," "illustratively," "as (another) example," and the like are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise. "at least one" means one or more, and "a plurality" means two or more. "at most one" means one or 0. "and/or" describes an association of associated objects, meaning that there may be three relationships, e.g., A and/or B, and that there may be A alone, while A and B are present, and B alone, where A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one of a, b and c may represent a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Wherein a, b and c can be single or multiple respectively. The relevant description relating to network element a sending a message, information or data to network element B and network element B receiving a message, information or data from network element a is intended to illustrate to which network element the message, information or data is intended for, and not to limit whether it is sent directly between them or indirectly via other network elements. The descriptions of "when..once.," in the case of..once., "if" and "if" etc. all refer to that the device will make the corresponding treatment in some objective condition, it is not intended to limit the time, nor does it require that the device have to have a deterministic action in its implementation, nor does it imply that there are other limitations. "corresponds to" and equivalents means that the two have a correspondence, and may include indirect correspondence. For example, corresponding to an objective condition, the device may directly or indirectly make the corresponding process, and does not require that the corresponding process must follow the objective condition.

In addition, the network architecture and the service scenario described in the embodiments of the present application are for more clearly describing the technical solution of the embodiments of the present application, and do not constitute a limitation on the technical solution provided by the embodiments of the present application, and as a person of ordinary skill in the art can know, with evolution of the network architecture and appearance of a new service scenario, the technical solution provided by the embodiments of the present application is also applicable to similar technical problems.

A communication system to which the embodiments of the present application can be applied is described below.

Embodiments of the present application may be applied to various communication systems including, but not limited to, fifth generation (5th generation,5G) systems, LTE systems, long term evolution advanced (long term evolution-advanced, LTE-a) systems, LTE frequency division duplex (frequency division duplex, FDD) systems, LTE time division duplex (time division duplex, TDD) systems, and the like. But also to future communication systems, such as sixth generation mobile communication systems. Further, it may also be applied to device-to-device (D2D) communications, vehicle-to-everything (V2X) communications, machine-to-machine (machine to machine, M2M) communications, machine type communications (MACHINE TYPE communications, MTC), internet of things (internet of things, ioT) communications systems, narrowband internet of things systems (NB-IoT) or other communications systems. In addition, the method can be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (worldwide interoperability for microwave access, WIMAX), and third generation partnership project (3rd generation partnership project,3GPP), etc., without limitation.

A communication system suitable for use with embodiments of the present application may include one or more transmitting end devices and one or more receiving end devices. Alternatively, one of the transmitting-end device and the receiving-end device may be a terminal device, and the other may be a network device. Alternatively, the transmitting end device and the receiving end device may be both terminal devices. Alternatively, the transmitting-end device and the receiving-end device may both be network devices.

Fig. 1 is a schematic diagram of a network architecture to which an embodiment of the application is applied. As shown in fig. 1, the embodiment of the present application can be applied to both uplink data transmission and downlink data transmission. Only uplink data transmission or downlink data transmission between one network device and two terminal devices (e.g., terminal device 1 and terminal device 2) is taken as an example in fig. 1. In uplink data transmission, the transmitting end equipment is terminal equipment, and the receiving end equipment is network equipment, whereas in downlink data transmission, the transmitting end equipment is network equipment, and the receiving end equipment is terminal equipment. Furthermore, applicability of embodiments of the present application in other communication scenarios is not limited, and may also be applied in, for example, side-link communications.

The terminal device of the present application may also be referred to as a User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a Mobile Terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a drone, a wireless communication device, a user agent, a user equipment, or the like. The terminal device in the embodiment of the application can be a device for providing voice and/or data connectivity for a user, and can be used for connecting people, things and machines, such as a handheld device with a wireless connection function, a vehicle-mounted device and the like. The terminal device in the embodiment of the present application may be a mobile phone (mobile phone), a tablet (pad), a notebook, a palm, a Mobile Internet Device (MID), a wearable device, a Virtual Reality (VR) device, an augmented reality (augmented reality, AR) device, a wireless terminal in industrial control (industrial control), a wireless terminal in unmanned (SELF DRIVING), a wireless terminal in teleoperation (remote medical surgery), a wireless terminal in smart grid (SMART GRID), a wireless terminal in transportation security (transportation safety), a wireless terminal in smart city (SMART CITY), a wireless terminal in smart home (smart home), or the like.

The network device of the present application may be a device having a radio transceiving function, which may be a device providing a radio communication function service, typically located at a network side, including but not limited to a next generation base station (gnob, gNB) in a 5G system, a base station in a sixth generation mobile communication system, a base station in a future mobile communication system, or an access Node in a wireless fidelity (WIRELESS FIDELITY, wiFi) system, an evolved Node B (eNB) in a long term evolution (long term evolution, LTE) system, a radio network controller (radio network controller, RNC), a Node B (NB), a base station controller (base station controller, BSC), a home base station (e.g., home evolved NodeB or home B, HNB), a baseband unit (BBU), a transmission reception point (transmission reception point, TRP), a transmission point (TRANSMITTING POINT, TP), a base transceiver station (base transceiver station, BTS), a satellite, a drone, etc. In a network architecture, the network device may include a centralized unit (centralized unit, CU) node, or include a Distributed Unit (DU) node, or be a RAN device including a CU node and a DU node, or be a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, a relay station, an in-vehicle device, a wearable device, etc. in a cloud wireless access network (cloud radio access network, CRAN) scenario. Further, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip for placement within the aforementioned device or apparatus. The base station may also be a mobile switching center, a device that performs a base station function in D2D, V2X, M M communication, a network side device in a 6G network, a device that performs a base station function in a future communication system, or the like. The base stations may support networks of the same or different access technologies, without limitation.

The means for implementing the functions of the terminal device or the network device in the present application may refer to the terminal device or the network device itself, or may refer to a device capable of supporting the terminal device or the network device to implement the functions, such as a system on a chip (SoC) or a Modem (Modem), unless otherwise specified. The apparatus may be installed in a terminal device or a network device. In the embodiment of the application, the chip system can be composed of chips, and can also comprise chips and other discrete devices.

It should also be noted that some of the embodiments herein describe specific solution details by taking a 5G system as an example. It will be appreciated that when the scheme is used in other communication systems, for example, an LTE system, or future communication systems, each message, channel, or information in the scheme may be replaced with a message, channel, or information, etc. in other communication systems that can implement the corresponding function, which the present application is not limited to.

In addition, the embodiment of the application can be applied to various application scenes, such as a high-throughput scene, a high-reliability scene, a low-time-delay scene, a high-reliability low-time-delay scene or a low-power consumption scene. The high-throughput scene may be, for example, an enhanced mobile broadband (enhanced mobile broadband, eMBB) scene, the high-reliability low-latency scene may be, for example, a URLLC (ultra reliable low latency communication) scene, the low-power-consumption scene may be, for example, an M2M scene, an MTC scene, an IoT scene, or the like.

In order to facilitate understanding of embodiments of the present application, several concepts or terms related to embodiments of the present application are briefly described. The concepts or terms described below are described with reference to concepts or terms specified in the protocol, but it is not meant that embodiments of the present application can be applied only to existing systems, and concepts or terms to which embodiments of the present application relate can be applied to future systems. And wherein specific names of concepts or terms (e.g., concepts or terms related to the functional description) may be adjusted as future systems evolve.

1. LDPC code

The LDPC code is a linear block code, in which an information sequence to be encoded is divided into groups in units of q bits, and then the q information bits are subjected to linear operation by an encoder to obtain m check bits, and then the q information bits are combined with the m check bits to obtain a codeword with a length of n=q+m. The mapping from q bits of information bits to codewords of length n bits is generally represented by a corresponding check matrix H. And correspondingly generating a code word sequence according to the check matrix H to finish the coding process, and correspondingly decoding the received signal by the receiving end equipment after the code word sequence is transmitted through a channel to judge the original information bits.

The check matrix H of the LDPC is a sparse matrix. The number of zero elements in the check matrix H is far more than the number of non-zero elements, or, the row weight (or column weight) of the check matrix is far less than the number of elements in each row (or column) of the LDPC matrix. The LDPC code with length equal to q and code length equal to n can be uniquely determined by the check matrix H.

Tanner (Tanner) represented the check matrix H in 1981 by way of a graph, which is now referred to as a Tanner graph, which corresponds to the check matrix one-to-one. The Tanner graph is composed of two classes of vertices, one class of vertices representing codeword bits, called variable nodes, and the other class of vertices representing check constraint relationships, each check node representing a check constraint relationship, as described below in conjunction with fig. 2 and 3.

Fig. 2 is a schematic diagram of a check matrix H of LDPC.

In fig. 2, { V _i } represents a Variable Node (VN) set, { C _i } represents a Check Node (CN) set. Each row of the check matrix H represents a check equation, each check equation corresponding to a check node, each column represents a codeword bit, and each codeword bit corresponds to a variable node. In fig. 2, the number of variable nodes is 8, and the number of check nodes is 4. If a codeword bit is included in the corresponding check equation, a connection is used to connect the variable node and check node concerned to obtain the Tanner graph.

Fig. 3 is a Tanner graph of an LDPC check matrix H.

As shown in fig. 3, the Tanner graph represents the check matrix of the LDPC. For example, for a check matrix H with m rows and n columns, the Tanner graph includes two types of nodes, namely n variable nodes and m check nodes. The n variable nodes respectively correspond to n columns of the check matrix H, and the m check nodes respectively correspond to m rows of the check matrix H. The circle (cycle) in the Tanner graph is made up of vertices connected to each other, with one vertex in the group of vertices being the start and end point at the same time, and passing through each node only once. More specifically, the circles in the Tanner graph refer to a closed loop formed by connecting variable nodes, check nodes and edges end to end. The length of a circle is defined as the number of edges it contains, and the girth of the graph may also be referred to as the perimeter of the graph, defined as the smallest circle length in the graph, as shown by the darkened line in fig. 3, with a girth of 4 in fig. 3. The variable nodes in the Tanner graph correspond to each column of the check matrix H, i.e., to each codeword bit of the LDPC. Check nodes in the Tanner graph correspond to each row of the check matrix H, i.e. to check bits of the LDPC. The connection condition between the two types of nodes corresponds to the value of the element in the H matrix. If there is connection between the ith check node and the jth variable node, the value of the element (i, j) representing the H matrix is 1, and if there is no connection, the corresponding element is 0. The connection between a variable node and a check node may also be referred to as a join. The check node and the variable node are connected, and can be described as having connection or connecting edges between the check node and the variable node. The connective relationship between the check node and the variable node may include both the presence or absence of connective edges.

2. QC-LDPC code

QC-LDPC codes are a class of structured LDPC codes. Due to the unique structure of the check matrix, the code can be realized by using a simple feedback shift register during coding, and the coding complexity of the LDPC code is reduced. The actually used QC-LDPC code is represented by a Base Graph (BG), wherein elements in the BG are 0 or 1, and 1 and 0 in the BG are expanded, and a check matrix H can be obtained after expansion is completed and used for encoding or decoding. In the embodiment of the application, BG can be written in a matrix form, and can be called as a base matrix H _BG in the application. An element of 0 in the base matrix H _BG indicates that there is no continuous edge in the base graph, and a value of 1 indicates that there is continuous edge in the base graph (or indicates that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multi-base pattern selection, and the current standard stores two base patterns, BG1 and BG2, respectively. When the information length is less than or equal to 292, or the information length is less than or equal to 3824 and the code rate is less than or equal to 2/3, or the code rate is less than or equal to 0.25, BG2 is used, otherwise BG1 is used. The expansion process of the base matrix is described below.

Based on the base matrix and the lifting values Zc (lifting size), the base matrix may be extended to a complete check matrix for encoding or decoding. Z _c in the present application may also be referred to as a spreading factor, a lifting factor, a spreading value, a spreading factor, a lifting size, etc. The expansion process is to promote all elements in the base matrix to be a zc×zc square matrix, wherein 0 is promoted to be a zc×zc 0 matrix, 1 is promoted to be an identity matrix, and cyclic shift is performed on the identity matrix based on a translation value (shifting value, SV) corresponding to 1, and the cyclic shift can be leftward or rightward, which is not limited in the application. It will be appreciated that each 1 in the base matrix corresponds to a respective one of the translation values. Taking a 4*4 identity matrix as an example, if the shift values are 0,1,3, the cyclic shift matrix after right cyclic shift is as follows:

(1) When the shift value is 0 (i.e. kept unchanged), the corresponding matrix after cyclic shift is

(2) When the translation value is 1, the corresponding matrix after cyclic shift is

(3) When the translation value is 3, the corresponding matrix after cyclic shift is

It will also be appreciated that the complete check matrix H may be represented by an index matrix H _b, each element in H _b corresponding to a Zc sub-matrix, each element identifying the number of times the corresponding sub-matrix is cyclically shifted by the Zc identity matrix, whereby the storage space required for the complete check matrix H is greatly reduced. The elements in the index array H _b may also be referred to as QC blocks.

For example, the exponential matrix H _b of QC-LDPC code is as follows:

It can be seen that the index matrix H _b has a size of 4 rows and 24 columns, and that each element i in the index matrix H _b represents a square matrix of Zc order The cyclic shift matrix is represented, i represents a cyclic shift value of the cyclic shift matrix, and i is an integer. In addition, in the exponent matrix H _b, "-1" represents an all-zero matrix, and "0" represents an identity matrix.

For example, the number of the cells to be processed,The following is shown:

Alternatively, the zero elements in the exponent matrix H _b may have other expressions other than "-1", for example, using "-" or null values to represent an all-zero matrix.

It can be understood that, the matrix corresponding to the position of-1 being changed to 0 is the base matrix by changing the position of greater than and equal to 0 in the index matrix H _b to 1. And expanding 1 in the base matrix into a Zc-Zc cyclic shift matrix based on elements in the corresponding position of the index matrix, expanding 0 into a Zc-Zc 0 matrix, and obtaining a check matrix after expansion is completed.

Then, the information bit sequence c may be encoded based on the check matrix H to obtain a codeword sequence, where the codeword sequence includes (n+2×zc-K) check bits w, N is a length of the codeword sequence, k=kb×zc, kb is a number of columns of the information column corresponding to the base map, zc is a lifting value, and Zc is specifically referred to as description in term interpretation 3. Specifically, the check bit w is determined based on the information bit sequence c and the check matrix H, wherein the encoding process for the check bit w＝[w₀,w₁,w₂,…,w_N+2*Zc-K-1]^T,c＝[c₀,c₁,c₂,…,c_K-1]^T, is to solve the equationThe process of obtaining w.

3. Lifting Value Zc (Lifting Size) and Shifting Value (Shifting Value)

The storage content of the 5G LDPC code about the shift Value comprises (1) a Lifting Value (Shifting Size) list and (2) a shift Value (Shifting Value) list corresponding to the rows of the Lifting Size list one by one.

Illustratively, the list of polarizing Size is shown in Table 1.

TABLE 1

Promotion value index	Lifting value sets
		0	{2,4,8,16,32,64,128,256}
1	{3,6,12,24,48,96,192,384}
		2	{5,10,20,40,80,160,320}
3	{7,14,28,56,112,224}
		4	{9,18,36,72,144,288}
5	{11,22,44,88,176,352}
		6	{13,26,52,104,208}
7	{15,30,60,120,240}

The j-th line of the list of sharpening Size includesWherein a _j∈{2,3,5,7,9,11,13,15},max(k_j) is {7,7,6,5,5,5,4,4}, and the line label of the Lifting Size corresponds to the column label of the Lifting Value one by one, i.e. the Lifting Size in each line of the Lifting Size list corresponds to a group of the Lifting Value.

For example, the Shifting Value list is shown in table 2.

TABLE 2

For a fixed lifting value index, one non-0 position of the base matrix corresponds to 1 translation value. For example, the element in row 0 and column 0 in H _BG corresponds to a shift value of 211 when the lifting value index=0, the element in row 1 and column 6 in H _BG corresponds to a shift value of 66 when the lifting value index=3, and the element in row 2 and column 9 in H _BG corresponds to a shift value of 206 when the lifting value index=7.

It will be appreciated that, currently, when LDPC encoding is performed, it is necessary to determine the lifting value first, and then determine the corresponding translation value based on the selected lifting value to construct the check matrix. For example, if the determined lifting value is 40, and the lifting value index corresponding to 40 in table 1 is 2, then the check matrix may be constructed based on the translation value in the column corresponding to the lifting value index=2 in table 2.

4. Structure of base matrix

Fig. 4 is a schematic diagram of the structure of a check matrix.

As shown in fig. 4 (a), the check matrix may include a high rate region (high rate region), an all-zero region, an incremental redundancy region (INCREMENTAL REDUNDANCY REGION), and a laplace-like region (raptor-like region). The high code rate region may include a portion a and a portion B shown in fig. 4 (B), where the portion a corresponds to information bits (or called information bits, systematic bits, etc.), and the portion B is a square matrix and corresponds to core check bits (or called core check bits), where the core check may be a check corresponding to the highest code rate, or may also be a check having degrees all greater than or equal to 2, or may also be a check node corresponding to a row set having the greatest row weight (row weight is significantly higher than other rows). The all zero region may correspond to part C of fig. 4 (b) and be an all zero matrix. The incremental redundancy region (INCREMENTAL REDUNDANCY REGION) may correspond to part D in fig. 4 (b). The laponite-like region may correspond to the E part of (b) of fig. 4, may be an identity matrix, and corresponds to the low-rate extended check bits. The part B and the part E are both verification parts, the part B is defined as a core verification area, the characteristic can be a coding part of a non-lower triangle (namely, the value above the diagonal is not all 0), or a coding part with the column weight larger than 1, the part E is defined as an expansion verification area, and the characteristic can be a coding part of a lower triangle (namely, the value above the diagonal is all 0), or a diagonal matrix.

The check matrix of the LDPC code shown in FIG. 4 adopts a 'raptor-like' structure, and can be gradually expanded to a low code rate through a core matrix with a high code rate. In actual use, as shown in fig. 4 (a), the front X rows and front Y columns of the check matrix may be truncated, and as the code rate increases from high to low, the areas of the matrix used are also gradually enlarged.

It should be noted that the check matrix may be represented by an LDPC base matrix, and thus the structure of the LDPC base matrix is similar to that of the check matrix, which is not described in detail herein.

5. Information column and check column

The columns of the LDPC matrix are composed of information columns and check columns.

Information columns corresponding to information bits (or information bits, system bits, etc.), are columns corresponding to the a portion.

The check columns correspond to check bits (or check bits, etc.), and are columns corresponding to the B part and the C part, and can comprise a core check column and an expansion check column. The core check column is a column corresponding to the B part, the expansion check column is a column corresponding to the C part or the E part, and the expansion check column can be also called a raptor-like column. Or the core check column is a check column with a column weight greater than 1 in the B part (1 element is arranged above and below the diagonal line of the B part), and the expansion check column is the rest of the check columns except the core check column.

6. Core row, core column, core matrix

Core row: core row of LDPC base matrix core row corresponding to core check bit. In other words, the core row is a row corresponding to a high code rate region, or a row corresponding to a portion a, B, or C.

The core column may include all information columns and all core check columns. In other words, the core column is a column corresponding to a high code rate region, or a column corresponding to a portion a+b.

The core Matrix (Kernel Matrix) is a Matrix region consisting of all core rows and all core columns of the LDPC base Matrix. In other words, the core matrix is a high code rate region of the LDPC base matrix, or a part consisting of a part and a part B.

7. Traditional expansion and split expansion

The traditional expansion is also called normal expansion, and refers to a low code rate expansion mode based on a traditional mode, wherein in the mode, the rows of the storage matrix are read as the rows of the LDPC base matrix.

The split expansion is different from the traditional expansion in that a row of the storage matrix is read as a newly added row of the LDPC base matrix, and a certain row in front of the newly added row in the LDPC base matrix is required to be subjected to element elimination by using the newly added row, and the line subjected to element elimination and the newly added row are orthogonal except for expansion nodes. It can also be understood that the line after the elimination is split into a newly added line and a line after the elimination, or the line after the elimination and the newly added line are orthogonal except for the expansion node, or the line after the elimination really contains all other lines except for the expansion check node in the newly added line. The line that is eliminated may correspond to a parent node, and the newly added line or elimination line may correspond to a child node.

8. Space coupling-low density parity check code (SPATIALLY COUPLED-low DENSITY PARITY CHECK, SC-LDPC) code

The SC-LDPC code is constructed by coupling L disjoint subcodes, where L is the coupling length, and the SC-LDPC code check matrix H has the form:

wherein H _i is a parity check matrix with the size of MxN, w is a coupling width, Is a subcode, L is the coupling length, i.e. contained in HIs a number of (3).

The quasi-cyclic SC-LDPC (QC SC-LDPC) code is an SC-LDPC code with a special structure, and the check matrix H of the quasi-cyclic SC-LDPC code can be obtained by lifting the corresponding base matrix. At a lifting value of Z _c, the form of the base matrix B of the QC SC-LDPC code is as follows:

Wherein B _i is a base matrix block of size m×n, m=m/Z _c,n＝N/Z_c, w is a coupling width, and L is a coupling length.

9. Information transmission flow

Fig. 5 is a schematic diagram of an information transmission flow suitable for use in the present application. As shown in fig. 5, the information is sent by the source, and the information arrives at the sink after processing such as source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery, and the like, so as to complete the transmission of the information from the source to the sink. Wherein the processing shown in the upper layer of fig. 5 (including source coding, channel coding, modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. Embodiments of the present application generally relate to source coding, channel decoding, and source recovery as shown in fig. 5.

Based on the description in the background art, the application provides a communication method based on LDPC codes, which can effectively solve the technical problems. The method according to the present application will be described in detail.

Fig. 6 is a schematic flow chart of a communication method 600 based on an LDPC code provided by the present application. The method comprises the following steps.

It is to be understood that the method 600 may be performed by a transmitting device and a receiving device, and that "transmitting device" or "receiving device" may refer to the transmitting device or the receiving device itself, or may refer to a device capable of supporting the transmitting device or the receiving device to implement the function, which are described in the following description using the transmitting device and the receiving device for convenience of description. The sending end device may be a terminal device or a network device, and the receiving end device may be a terminal device or a network device.

S610, the transmitting end equipment acquires the information bit sequence.

It can be appreciated that if the transmitting end device needs to communicate with the receiving end device, that is, the transmitting end device needs to send a signal to the receiving end device, the transmitting end device needs to first acquire an information bit sequence corresponding to the signal that needs to be sent to the receiving end device.

The sending end device obtains the information bit sequence, which may mean that the sending end device performs source coding on the source symbol to generate the information bit sequence, or the sending end device obtains the information bit sequence, or that the sending end device receives the information bit sequence from other communication devices, the method for obtaining the information bit sequence is not limited in the application.

S620, the transmitting terminal equipment determines the LDPC matrix.

The LDPC matrix is determined based on an LDPC base matrix (hereinafter abbreviated as base matrix), a lifting value Zc and a translation value of the base matrix, wherein the translation value of the base matrix is determined based on a second row sequence R, a second column sequence C and the lifting value Zc, the number of elements of the second row sequence R is equal to the number of rows of the base matrix and the elements of the second row sequence are in one-to-one correspondence with the rows of the base matrix, the number of elements of the second column sequence C is equal to the number of columns of the base matrix and the elements of the second column sequence are in one-to-one correspondence with the columns of the base matrix, the second row sequence is determined based on the first row sequence, the number of elements of the first row sequence is smaller than the number of elements of the second row sequence, and the number of elements of the first column sequence is smaller than the number of elements of the second column sequence.

The base matrix may be the base matrix of a QC-LDPC code, or may be the base matrix of a QC SC-LDPC code, for example.

For example, the first row sequence may correspond to at least one second row sequence, and similarly, the first column sequence may also correspond to at least one second column sequence. If there are a plurality of second row (column) sequences, a second row (column) sequence to be finally used may be determined according to the lifting value Zc, and then a translation value of the base matrix may be determined based on the determined second row (column) sequence.

For example, the correspondence between the elements in the second row (column) sequence and the rows (columns) of the base matrix may be sequential correspondence, i.e. the ith element in the second row (column) sequence corresponds to the ith row (column) of the base matrix, or the correspondence may be reverse order correspondence, or the correspondence may also be a specific order.

For example, the first row (column) sequence may be obtained based on the lift value index corresponding to Zc or Zc, or the first row (column) sequence may be obtained based on a pre-stored sequence calculation, and the method for obtaining the first row (column) sequence is not limited in the present application.

First, possible implementations of determining the translation value of the basis matrix based on the second row sequence R, the second column sequence C and the lifting value Zc are described in detail.

Alternatively, the translation value of the 1 element in the base matrix may be determined based on the following manner that the translation value of the 1 element in the base matrix located in the row i and the column j is obtained by summing t first numerical values, t is a positive integer, wherein the first numerical values are determined based on R (i), C (j), zc, p and s corresponding to the first numerical values, R (i) is an element corresponding to the row i in the second row sequence R, C (j) is an element corresponding to the column j in the second column sequence C, s is an integer between 1 and t, and p is a prime number corresponding to Zc.

For example, s corresponding to any one of the t first values is different, that is, t s corresponding to the t first values is t different integers between 1 and t.

For example, p may be a prime number base of Zc, or may be a maximum value or a minimum value in prime number bases corresponding to all lifting value sets, or may be a maximum prime number capable of dividing the maximum lifting value in all lifting value sets, or may be a prime number capable of dividing any lifting value in all lifting value sets.

P is illustrated below in connection with a specific set of boost values. By way of example, there is an exponentially increasing set of lifting values other than those shown in table 2, the type of lifting values corresponding to 3 sets of lifting values, all lifting values in the first set of lifting values satisfying the first expression 7n, n being a positive integer (e.g., the first set of lifting values includes lifting values 7, 14, 21), all lifting values in the second set of lifting values satisfying the second expression 11n (e.g., the second set of lifting values includes lifting values 11, 22, 33), all lifting values in the third set of lifting values satisfying the third expression 13n (e.g., the third set of lifting values includes lifting values 13, 26, 39). For example, if Zc is a lifting value in the second set of lifting values, p is 11. For example, if p is the maximum value in the prime number base corresponding to the 3 lifting value sets, p is 13. For example, if p is the minimum value in the prime number base corresponding to the 3 lifting value sets, p is 7. And are not illustrated here.

Two ways of determining SV _i,j are given below.

Mode one

Where mod represents a modulo operation, and the parameters in the above formula are explained below.

(1) S is a positive integer, t is an integer greater than or equal to 1, and u _s+v_s＝s+1,u_s and v _s are both positive integers.

For example, t=2 or 3.

By way of example, s=3, there are possible values of u _s＝1,v_s =3, or u _s＝2,v_s =2, or v _s＝3,v_s =1.

Illustratively, u _s＝1,v_s = s, then

For example, u _s＝s,v_s = 1, then

It is understood that mod ((R (i) ×c (j)) ^s),(Z_{id_s}*p))*k_s may be regarded as an example of one of the above t first values.

(2) See the description above for p, and are not repeated here.

(3) Z _{id_s} is determined based on Zc, p and s, or, Z _{id_s} =1.

In one possible implementation, Z _{id_s}＝mod(mod(Zc,p^s+1),p^s), where there are two segments of modulo, where the two segments of modulo are Zc modulo the p-related parameter, and the object of the first segment of modulo is p times the object of the second segment of modulo.

By way of example, the detailed expressions for Z _{id_s} corresponding to s greater than 3 are analogized based on the detailed implementation ,Z_{id_1}＝mod(mod(Zc,p²),p),Z_{id_2}＝mod(mod(Zc,p³),p²),Z_{id_3}＝mod(mod(Zc,p⁴),p³),, and are not described in detail herein.

Optionally, Z _{id_s} corresponding to all s in s=1 to t is determined based on Zc, p and s.

Optionally, Z _{id_s} corresponding to all s in s=1 to t is 1.

Optionally, Z _{id_s} corresponding to a part s in s=1 to t is determined based on Zc, p and s, and Z _{id_s} =1 corresponding to the remaining s.

(4) K _s is a positive integer multiple of p ^s-1.

Specifically, k ₁ is an integer multiple of 1, k ₂ is an integer multiple of p, k ₃ is an integer multiple of p ², and so on, which are not described here again.

By way of example, the positive integer multiple here is 1, i.e. k _s equals p ^s-1.

Based on the description corresponding to fig. 3, it can be seen that in the Tanner graph, the circle is defined by starting from a vertex, passing through the non-repeated vertex along the non-repeated edge, and finally returning to the structure of the starting point. Since the Tanner graph is a two-part graph, the length of the circle can only be an even number greater than 2, such as 4,6,8, etc. The shorter length of the loop is a great hazard to the LDPC code, so in the design of the LDPC code, it is necessary to avoid the short loop as much as possible. The SV _i,j calculation formula given above can theoretically guarantee the loop characteristics. Different terms of the calculation formula can ensure different circle properties. For example, in the above equation for SV _i,j, s=1 is to ensure that 4 turns do not exist, s=2 is to ensure that the number of 6 turns is small, and that 6 turns do not exist if Zc is sufficiently large, s=3 is to ensure that the number of 8 turns is small, and that 8 turns do not exist if Zc is sufficiently large, and so on, and s is greater than or equal to 3 to further ensure the turn property.

Alternatively, a fixed constant may be added or subtracted to the above equation for SV _i,j, which constant does not change with position i and j, and at this time, the overall ring properties do not change.

Mode two

In this manner, mod corresponding to s=1 to t (N _s,(Z_{id_s}*p))*k_s may be understood as the above t first values, and SV _i,j may be obtained by adding the t first values, where N _s corresponding to each first value may be obtained by looking up a table.

It is to be understood that the above formula is only an example, and the meaning of each parameter is described in the first mode, and will not be repeated here. In this way, the flow of table lookup to obtain M _s is described with emphasis.

Wherein N _s is obtained based on R (i), C (j) and a pre-stored table s, wherein each row and each column in the table s stores a value at a position corresponding to the table s, N _s is a value stored at a position corresponding to a row R1 and a column C1 of the table s, wherein the row R1 is a row associated with R (i) in the table s, and the column C1 is a column associated with C (j) in the table s. For example, as shown in the right table in fig. 7, element 3 in the second row sequence corresponding to the 2 nd row of the base matrix is associated with the (3+1) th row (i.e., one example of row r 1) of the table s, and element 7 in the second column sequence corresponding to the 8 th column of the base matrix is associated with the (7+1) th column (i.e., one example of column c 1) of the table s, so that the shift value of the 1 element in the 2 nd row and 8 th column of the base matrix is the value 5 stored in the position corresponding to the 4 th row and 8 th column of the table s.

It will be understood that N _s is obtained based on R (i), C (j) and table s, and then N _s corresponding to s=1 to t is obtained through R (i), C (j) and t tables, respectively, specifically, N ₁ is obtained based on R (i), C (j) and table 1, N ₂ is obtained based on R (i), C (j) and table 2, and so on, and will not be described herein.

While the table look-up acquisition N _s was described above, a possible way of determining the values stored in table s is given below by way of example only.

In one possible implementation, the value N _s stored in the table s satisfies the following formula:

Wherein u _s+v_s＝s+1,u_s and v _s are both positive integers.

In another possible implementation, the value N _s stored in the table s satisfies the following formula:

the correspondence of rows in table s with the second row sequence and columns in table s with the second column sequence is described below.

In one possible implementation, all rows of the table s are in one-to-one correspondence with all elements in the second row sequence, and all columns of the table s are in one-to-one correspondence with all elements in the second column sequence. Illustratively, R (i) is associated with row i in table s and C (j) is associated with row j in table s.

In another possible implementation manner, the elements in the second row sequence and the second column sequence are elements in a finite field, the finite field may also be called a galois field, the number of the elements is a power of prime number field, and the number of the elements in the finite field set is p. For example, p=13, the finite field set may be {0,1,2,3,4,5,6,7,8,9,10,11,12}, the table s is shown in table 3, all rows of the table s are in one-to-one correspondence with elements in the finite field, and all columns of the table s are in one-to-one correspondence with elements in the finite field, specifically, the first column may be regarded as one finite field element for each row, and the first row may be regarded as one finite field element for each column.

TABLE 3 Table 3

For example, the elements in the first row sequence and the first column sequence may also be elements in the finite field set.

Illustratively, R (i) is associated with row mod ((R (i) +a), p) in table s, and similarly, C (j) is associated with row mod ((C (j) +b), p) in table s.

For example, a=b. Further, a=b=0 or a=b=1 or-1. The advantage of a=b=0 is that the expression is simple, and the advantage of a=b=1 or-1 is corresponding to the finite field element, so that the calculation is easy and the hardware implementation is realized.

For example, p=13, the finite field set may be the set {0,1,2,3,4,5,6,7,8,9,10,11,12}, a=b= -1, the second row sequence is {2,4,5,7,8,9}, the second column sequence is {0,2,3,5,6,10}, taking 5 in the second row sequence as an example, 5 is associated with row 4 in table s, 0 in the second column sequence as an example, 0 is associated with column 11 in table s, and N _s is a value stored in a position corresponding to row 4 and column 11 in table s.

It will be appreciated that the formulas in the first and second modes are merely examples, and for example, Z _{id_s} in the above formulas may be replaced by a quotient of Zc divided by Zc, for example, zc=33, and Zc with 11, then Z _{id_s} =3.

In one possible implementation, the second row sequence and the second column sequence are determined based on the third sequence. For example, the second row sequence may be obtained by cutting out a corresponding number of elements in the third sequence based on the number of rows of the base matrix, and similarly, the second column sequence may be obtained by cutting out a corresponding number of elements in the third sequence based on the number of columns of the base matrix.

Next, two scenarios, that is, a QC-LDPC base matrix and a QC SC-LDPC base matrix, are taken as examples of the base matrix, and a possible implementation manner of determining the second row sequence based on the first row sequence and determining the second column sequence based on the first column sequence is described in detail below.

In a first scenario, the base matrix is a QC-LDPC base matrix, and the base matrix is determined based on a split sequence θ, and the second row sequence is determined based on the first row sequence and the split sequence θ.

The splitting sequence is described below. The base matrix is determined based on a split sequence θ, where the split sequence θ includes m elements, where m is equal to the number of rows of the base matrix, where m elements are in one-to-one correspondence with m rows of the base matrix, and it can be understood that an element corresponding to a row i of the base matrix in the m elements is θ (i).

For example, if the row number of the base matrix is numbered from 1, the value of the element θ (i) in the split sequence may be a first character or a positive integer, where the first character is not equal to any positive integer. When theta (i) is a positive integer, the row i representing the base matrix is associated with the row theta (i) of the base matrix, wherein the theta (i) is smaller than i, namely the value of the theta (i) is smaller than the row number of the current row, and when theta (i) is a first character, the row i representing the base matrix is not associated with any row in the base matrix. The first character may be a number, letter, symbol, or the like, which is not a limitation of the present application. For example, in this example, the first character may take 0, where the split sequence θ represents an expansion mode of the LDPC storage matrix, and when θ (i) is not equal to 0, it indicates that the ith row needs to be subjected to elimination with the θ (i) row when the ith row is expanded (which may be referred to as θ (i) being a parent node of i and i being a child node of θ (i)), and θ (i) =0 indicates that the ith row is normally expanded.

For example, if the row number of the base matrix starts from row 0, the first character cannot take 0, and other characters, such as-1, -2, etc., can be taken. The first character is not equal to a natural number (i.e., is not equal to 0 and a positive integer). Similarly, when θ (i) is a natural number, the row i representing the base matrix is associated with the row θ (i) of the base matrix, and θ (i) is smaller than i, that is, the value of θ (i) is smaller than the row number of the current row, and when θ (i) is the first character, the row i representing the base matrix is not associated with any row of the base matrix. The expansion mode is the same as above, and will not be described again here.

For convenience of explanation, the following description will be given with the row number and the column number of the base matrix (memory matrix) numbered from 1, and the first character is taken as 0, that is, the value of the element θ (i) in the split sequence is taken as 0 or a positive integer. The split sequence θ is illustrated. The base matrix includes m=17 rows, the split sequence θ includes 17 elements, θ= {0,0,0,0,0,0,0,3,1,4,0,0,0,0,2,7,6}, and the 17 elements are sequentially in one-to-one correspondence with 1 to 17 rows of the base matrix. Here, θ (i) =0 corresponding to row i= 1,2,3,4,5,6,7,11,12,13,14 of the base matrix, θ (8) = 3<8 corresponding to row 8 of the base matrix, and θ (9) = 1<9 corresponding to row 9 of the base matrix in the split sequence.

Two specific ways of determining the second row sequence based on the first row sequence are given below.

In one mode, the first row sequence is composed of a plurality of elements, the plurality of elements are in one-to-one correspondence with a plurality of rows of the base matrix, and a plurality of rows θ (i) of the base matrix are equal to all rows i of 0. Then, the element corresponding to row i1 in the second row sequence is equal to the element corresponding to row i1 in the first row sequence, the element corresponding to row i2 in the second row sequence is equal to the element corresponding to row θ (i 2) in the second row sequence, where θ (i 1) is equal to 0, θ (i 2) is a positive integer, and θ (i 2) is less than i2.

For example, if the plurality of elements in the first row sequence are different from each other, the elements corresponding to the row i1 in the second row sequence are different.

Examples are given in tables 4 and 5. It will be appreciated that the memory matrix is the same as the number of rows of the base matrix, and the matrices in tables 4 to 6 are memory matrices. As shown in table 4, the split sequence θ is {0,0,0,3,2,1,0}, and 7 elements in the split sequence θ correspond to rows 1 to 7 of the base matrix one by one, respectively. The first row sequence is {0,3,1,2}, 4 elements in the first row sequence are respectively corresponding to the 1 st row, the 2 nd row, the 3 rd row and the 7 th row of the base matrix one by one, and then as shown in table 5, elements corresponding to the i1 row in the second row sequence, namely elements corresponding to the 1 st row, the 2 nd row, the 3 rd row and the 7 th row in the second row sequence are {0,3,1,2}, respectively. In addition, the element corresponding to the line i2 in the second line sequence, that is, the element corresponding to the 4 th line in the second line sequence is equal to the element corresponding to the θ (4) th line in the second line sequence, because θ (4) =3, the element corresponding to the 4 th line in the second line sequence is equal to the element corresponding to the 3 rd line in the second line sequence, that is, equal to 1, and similarly, the element corresponding to the 5 th line in the second line sequence is equal to the element corresponding to the θ (5 th line, that is, 2 nd line) in the second line sequence, that is, equal to 3, and the element corresponding to the 6 th line in the second line sequence is equal to the element corresponding to the θ (6 th line, that is, 1 st line) in the second line sequence, that is, equal to 0, and therefore, the determined second line sequence is {0,3,1,1,3,0,2}.

TABLE 4 Table 4

TABLE 5

In a second mode, the first row sequence is composed of a plurality of elements, the plurality of elements are in one-to-one correspondence with a plurality of rows of the base matrix, and θ (i) corresponding to a core area of the base matrix is equal to a row of 0. Then, the element corresponding to the row i1 in the second row sequence is equal to the element corresponding to the row i1 in the first row sequence, the element corresponding to the row i3 in the second row sequence is equal to the element corresponding to the row i3 'in the first row sequence, the element corresponding to the row i2 in the second row sequence is equal to the element corresponding to the row θ (i 2) in the second row sequence, wherein the row i1 is any one of the plurality of rows, the row i3 is any one of the remaining rows except the plurality of rows among all rows where θ (i) is equal to 0, i3' is less than i3, wherein θ (i 1) is equal to 0, θ (i 2) is a positive integer, and θ (i 2) is less than i2.

By way of example, row i3' is any one of the rows having a common threshold number with row i3 of less than or equal to 1. For example, the elements corresponding to the positions of the row a and the column c and the row b and the column c in the storage matrix are all 1, and the number of the columns c meeting the above condition in the storage matrix can be understood as the number of the common adjacent points of the row a and the row b.

Examples are given in tables 4 and 6. As shown in table 4, the split sequence θ is {0,0,0,3,2,1,0}, and 7 elements in the split sequence θ correspond to rows 1 to 7 of the base matrix one by one, respectively. The first row sequence is {0,3,1}, 3 elements in the first row sequence are in one-to-one correspondence with the 1 st row, 2 nd row and 3 rd row of the base matrix respectively, then as shown in table 6, the elements corresponding to the 1 st row, 2 nd row and 3 rd row of the base matrix in the second row sequence are {0,3,1}, respectively, the elements corresponding to the 7 th row of the base matrix in the second row sequence may be equal to the elements corresponding to the 1 st row, 2 nd row or 3 rd row of the base matrix in the first row sequence, and here, by way of example, the rows with the common threshold number of less than or equal to 1 are selected, it can be seen that only the common threshold number of the 1 st row, 2 nd row and 3 rd row of the memory matrix satisfies the condition of less than or equal to 1, so the elements corresponding to the 7 th row of the base matrix in the second row sequence are equal to the elements corresponding to the 1 st row of the base matrix in the 7 th row sequence, that is equal to 0. In addition, the element corresponding to the 4 th row in the second row sequence is equal to the element corresponding to the θ (4) th row in the second row sequence, and because θ (4) =3, the element corresponding to the 4 th row in the second row sequence is equal to the element corresponding to the 3 rd row in the second row sequence, that is, equal to 1, and similarly, the element corresponding to the 5 th row in the second row sequence is equal to the element corresponding to the θ (5 th row, that is, 2 nd row) in the second row sequence, that is, equal to 3, and the element corresponding to the 6 th row in the second row sequence is equal to the element corresponding to the θ (6 th row, that is, 1 st row) in the second row sequence, that is, equal to 0, so the determined second row sequence is {0,3,1,1,3,0,0}.

TABLE 6

It can be seen that the first sequence does not contain the element corresponding to the line i of which θ (i) is not equal to the first character, so that the benefit is that translation values of the child node and the father node are guaranteed to have correlation, and the elimination expansion of QC level can be realized.

Optionally, the first line sequence may be determined based on a split sequence, where a plurality of elements in the first line sequence are all included in the split sequence, a first element in the first line sequence is a minimum value in the split sequence, an element corresponding to a first line in the first line sequence is smaller than an element corresponding to a second line, and a line number of the first line is smaller than a line number of the second line. It can also be understood that, for the line i where θ (i) =0, the first line sequence selects, in order from small to large, a smallest element that does not currently appear in the first line sequence as the element corresponding to the line i, that is, the selected element corresponding to the line i is not equal to the element corresponding to the line i '(i' < i) in the first line sequence, and for the line i where θ (i) >0, the value of the first line sequence does not need to be considered.

For example, if the splitting sequence is {0,0,0,3,2,1,0}, the first row sequence is {0,1,2,3}, and 4 elements in the first row sequence are respectively in one-to-one correspondence with the 1 st row, the 2 nd row, the 3 rd row and the 7 th row of the base matrix.

For example, the split sequence may be a pre-stored sequence.

The manner in which the second column sequence is determined based on the first column sequence is described below.

Optionally, the first column sequence includes a plurality of elements, the plurality of elements are in one-to-one correspondence with the core columns of the base matrix, the element corresponding to the column j1 in the second column sequence is equal to the element corresponding to the column j1 in the first column sequence, and the column j1 is any column in the core columns.

Illustratively, the elements in the second column sequence corresponding to all but the core columns of the base matrix are natural numbers. For example, elements of the second column sequence corresponding to the remaining columns may be identical, e.g., 0 or 1, or elements of the second column sequence corresponding to the remaining columns may be different, e.g., may be populated in a 01 or 10 cycle manner, which is not limited in this regard.

The base matrix is QC SC-LDPC base matrix, and the form of the base matrix is shown as a matrix B:

The sub-code of the base matrix has a coupling length L, a coupling width w, a number of rows m and a number of columns n of each base matrix block B _i in the sub-code.

In one possible implementation, the first row sequence includes (m×1) elements, and one base matrix block B _i corresponds to m rows, which can be regarded as that each m elements in the first row sequence corresponds to B ₀,…,B_w one by one in sequence. In addition, the rule of obtaining the second line sequence based on the first line sequence is that the second line sequence obtained by cyclic multiplexing based on the first line sequence includes (m× (l+w)) elements since the base matrix includes (m× (l+w)) lines in total.

In one possible implementation, the first column sequence may include (n×1) elements, where one base matrix block B _i corresponds to n columns, and each n elements in the first column sequence may be regarded as corresponding to (w+1) B ₀ one to one in sequence. In addition, the rule of obtaining the second column sequence based on the first column sequence is that the second column sequence obtained by cyclic multiplexing based on the first column sequence includes (n×l) elements since the base matrix includes (n×l) columns in total.

Illustrating cyclic multiplexing of sequences. For example, the base matrix includes 10 rows in total, with the first row sequence being {0,3,1,2}, and the second row sequence being {0,3,1,2,0,3,1,2,0,3}.

It will be appreciated that (w+1) in the above description is a parameter related to the coupling width w. Alternatively, (w+1) may be replaced by (w+c), and the corresponding first row/column sequence and the second row/column sequence are that the first row sequence is composed of (m× (w+c)) elements, the elements in the first row sequence are in one-to-one correspondence with the first (m× (w+c)) rows of the base matrix, c is an integer, the first column sequence is composed of (n× (w+c)) elements, and the elements in the first column sequence are in one-to-one correspondence with the first (n× (w+c)) columns of the base matrix. The second row sequence is composed of (m×l+w)) elements, the elements in the second row sequence are cyclically multiplexed based on the first row sequence, the second column sequence is composed of (n×l) elements, and the elements in the second column sequence are cyclically multiplexed based on the first column sequence.

Illustratively, c is equal to-1, -2, 0, 1, or 1. The advantage of this approach is that it is possible to ensure as good a loop quality as possible, supporting flexible lifting values.

It will be further understood that the elements corresponding to all rows in the base matrix in the second row sequence are circularly multiplexed by the first row sequence, and similarly, the elements corresponding to all columns in the base matrix in the second column sequence are circularly multiplexed by the first column sequence, so as long as the translation value corresponding to each 1 element in the area #1 in the base matrix is calculated, where the area #1 is an area formed by the front (2*m × (w+c) -1) row and the front (n× (w+c)) column of the base matrix, and the translation value of the remaining position in the base matrix can be circularly multiplexed based on the translation value of the area.

For example, n=m=1, w=4, and l=10, as shown in fig. 8, the base matrix is a matrix of 14 rows and 10 columns, and only the positions of 1 element are shown in the base matrix, and the elements of the remaining positions are all 0 elements. For example, if c=1, the first row sequence includes 5 elements, the first column sequence includes 5 elements, cyclic shift is performed based on the first row sequence and the first column sequence to obtain a second row sequence and a second column sequence, the second row sequence includes 14 elements, which are respectively in one-to-one correspondence with 14 rows of the base matrix, and the second column sequence includes 10 elements, which are respectively in one-to-one correspondence with 10 columns of the base matrix. As shown in fig. 8, if the translation value of 1 element in the area #1 of the base matrix is determined, and the area #1 is an area consisting of the first 9 rows and the first 5 columns of the base matrix, as shown in fig. 8, the translation values of the remaining positions in the base matrix may be circularly multiplexed based on the translation values of the area.

In another possible implementation, the length of the first row sequence is (w+c1) ×m, the length of the first column sequence is (w+c2) ×n, where c is an integer, and c1< c2, and then the second row sequence obtained by cyclic multiplexing the first row sequence is similar to the second row sequence obtained by cyclic multiplexing the first column sequence, where the second row sequence includes (n×l) elements. Then, a translation value of the base matrix is determined based on the second row sequence and the second column sequence. It will be understood that the elements corresponding to all rows in the base matrix in the second row sequence are circularly multiplexed by the first row sequence, and similarly, the elements corresponding to all columns in the base matrix in the second column sequence are circularly multiplexed by the first column sequence, so as long as the translation value corresponding to each 1 element in the area #1 in the base matrix is calculated, where the area #1 is an area formed by the front (2*m × (w+c1) -1) row and the front (n× (w+c2)) column of the base matrix, and the translation value of the remaining position in the base matrix can be circularly multiplexed based on the translation value of the area.

Alternatively, in the process of circularly multiplexing the first row (column) sequence to obtain the second row (column) sequence, each round of circularly multiplexing can replace the first row (column) sequence. Taking the first row sequence as sequence #1 as an example, the second row sequence is { { sequence #1}, p ₁ { sequence #1}, p ₂ { sequence #1}, where p _i is a permutation of sequence # 1. For example, the base matrix includes 10 rows in total, the first row sequence is {0,3,1,2}, then the second row sequence may be { { {0,3,1,2}, {3,1,0,2}, {3,0 }.

It can be understood that the corresponding LDPC matrix can be obtained after lifting and translating the elements in the base matrix. In the present application, the LDPC matrix may also be referred to as an LDPC coding matrix. For example, the LDPC matrix may be an LDPC check matrix, or an LDPC generator matrix. The LDPC check matrix or the LDPC generation matrix is a matrix obtained by lifting and shifting elements in all areas of the base matrix, and the LDPC generation matrix and the LDPC check matrix are in one-to-one correspondence.

S630, the transmitting terminal equipment encodes the information bit sequence according to the LDPC matrix and outputs a codeword sequence.

For the coding process, see the above description, and will not be repeated here.

S640, the transmitting device determines a symbol sequence based on the codeword sequence.

It will be appreciated that the symbol sequence may be a rate matched and modulated sequence. For example, the transmitting end device performs rate matching on the codeword sequence, modulates the sequence after rate matching to obtain a symbol sequence, and maps the modulated symbol sequence onto physical resources for transmission.

S650, the transmitting end device transmits the symbol sequence to the receiving end device. Correspondingly, the receiving end device receives the symbol sequence from the transmitting end device.

It will be appreciated that the symbol sequence #1 transmitted by the transmitting device may be different from the symbol sequence #2 received by the receiving device, since the symbol sequence may introduce a channel noise signal during transmission.

And S660, the receiving end equipment decodes the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

The LDCP matrix according to which the receiving end device decodes is the same as the LDPC matrix according to which the transmitting end device encodes, and the specific manner in which the receiving end device determines the LDPC matrix may refer to the description on the transmitting end device side, which will not be described in detail herein.

It will be appreciated that the various steps in the above figures are merely exemplary and are not strictly limiting. In addition, the sequence number of each process does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

It will also be appreciated that some optional features of the various embodiments of the application may, in some circumstances, be independent of other features or may, in some circumstances, be combined with other features, without limitation.

It should also be understood that, in the foregoing embodiments of the method and operations implemented by a device (a transmitting device or a receiving device), the method and operations may also be implemented by component parts of the device (such as a chip or a circuit), which are not limited thereto.

The method embodiment provided by the present application is described in detail above with reference to fig. 1 to 8, and the device embodiment of the present application will be described below with reference to fig. 9 and 10. It will be appreciated that, in order to implement the functions of the above embodiments, the apparatus in fig. 9 and 10 includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and method steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. It will be appreciated that the technical features described in the method embodiments described above are equally applicable to the device embodiments described below.

Fig. 9 and 10 are schematic structural views of possible devices according to embodiments of the present application. These apparatuses may be used to implement the functions of the transmitting end device or the receiving end device in the above method embodiments, so that the beneficial effects of the above method embodiments may also be implemented.

Fig. 9 is a schematic block diagram of a communication apparatus 1000 provided in an embodiment of the present application. As shown in fig. 9, the apparatus 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 may communicate with the outside, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

In one possible design, the apparatus 1000 may implement steps or processes performed by the transmitting device in the above method embodiment, where the processing unit 1020 is configured to perform the operations related to the processing of the transmitting device in the above method embodiment, and the communication unit 1010 is configured to perform the operations related to the transmission of the transmitting device in the above method embodiment.

In yet another possible design, the apparatus 1000 may implement steps or processes performed by a receiving end device in the above method embodiment, where the communication unit 1010 is configured to perform the operations related to the receiving end device in the above method embodiment, and the processing unit 1020 is configured to perform the operations related to the processing of the receiving end device in the above method embodiment.

It is understood that the apparatus 1000 herein is embodied in the form of functional units. The term "unit" herein may refer to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (e.g., a shared, dedicated, or group processor, etc.) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that support the described functionality. In an alternative example, it will be understood by those skilled in the art that the apparatus 1000 may be specifically configured to perform each flow and/or step corresponding to the transmitting end device in the foregoing method embodiment, or the apparatus 1000 may be specifically configured to be configured to perform each flow and/or step corresponding to the receiving end device in the foregoing method embodiment, which is not repeated herein.

The apparatus 1000 of each of the above aspects has a function of implementing the corresponding step performed by the transmitting end device in the above method, or the apparatus 1000 of each of the above aspects has a function of implementing the corresponding step performed by the receiving end device in the above method. The functions may be implemented by hardware, or may be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above, for example, the communication units may be replaced by transceivers (for example, a transmitting unit in the communication units may be replaced by a transmitter, a receiving unit in the communication units may be replaced by a receiver), and other units, such as a processing unit, may be replaced by a processor, to perform the transceiving operations and the related processing operations in the respective method embodiments, respectively.

The communication unit may be a transceiver circuit (e.g., may include a receiving circuit and a transmitting circuit), and the processing unit may be a processing circuit. In the embodiment of the present application, the apparatus in fig. 9 may be the receiving end device or the transmitting end device in the foregoing embodiment, or may be a chip or a system on chip (SoC), for example. The communication unit can be an input/output circuit or a communication interface, and the processing unit is a processor or a microprocessor or an integrated circuit integrated on the chip. And are not limited herein.

Fig. 10 is a schematic block diagram of a communication device 1100 according to an embodiment of the present application. The apparatus 1100 includes a processor 1110 and a transceiver 1120. Wherein the processor 1110 and the transceiver 1120 are in communication with each other via an internal connection path, the processor 1110 is configured to execute instructions to control the transceiver 1120 to transmit signals and/or receive signals.

Optionally, the apparatus 1100 may further include a memory 1130, where the memory 1130 and the processor 1110, the transceiver 1120 communicate with each other through an internal connection path. The memory 1130 is used to store instructions, and the processor 1110 may execute the instructions stored in the memory 1130. In a possible implementation manner, the apparatus 1100 is configured to implement each flow and step corresponding to the sending end device in the foregoing method embodiment. In another possible implementation manner, the apparatus 1100 is configured to implement the respective flows and steps corresponding to the receiving end device in the foregoing method embodiment.

Optionally, the memory 1130 may be integrated in the processor 1110.

In one possible scenario, the apparatus 1100 includes at least one processor integrated with memory, and other memory in addition to the memory integrated with the processor.

It is to be understood that the apparatus 1100 may be specifically a transmitting end device or a receiving end device in the foregoing embodiments, and may also be a chip or a chip system. Correspondingly, the transceiver 1120 may be a transceiver circuit of the chip, which is not limited herein. Specifically, the apparatus 1100 may be configured to perform each step and/or flow corresponding to the sending device or the receiving device in the above method embodiments.

The memory 1130 may optionally include read-only memory and random access memory, and provide instructions and data to the processor. The memory may comprise a non-volatile random access memory. For example, the memory may also store information of the device type. The processor 1110 may be configured to execute instructions stored in a memory, and when the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to perform the steps and/or processes of the method embodiments described above that correspond to a transmitting device or a receiving device.

In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in the processor for execution. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.

It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capability. In implementation, the steps of the above method embodiments may be implemented by integrated logic circuits of hardware in a processor or instructions in software form. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The processor in the embodiments of the present application may implement or execute the methods, steps and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be embodied directly in the execution of a hardware decoding processor, or in the execution of a combination of hardware and software modules in a decoding processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method.

It will be appreciated that the memory in embodiments of the application may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an erasable programmable ROM (erasable PROM), an electrically erasable programmable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as external cache memory. By way of example, and not limitation, many forms of RAM are available, such as static random access memory (STATIC RAM, SRAM), dynamic random access memory (DYNAMIC RAM, DRAM), synchronous Dynamic Random Access Memory (SDRAM), double data rate synchronous dynamic random access memory (doubledata RATE SDRAM, DDR SDRAM), enhanced synchronous dynamic random access memory (ENHANCED SDRAM, ESDRAM), synchronous link dynamic random access memory (SYNCHLINK DRAM, SLDRAM), and direct memory bus random access memory (direct rambus RAM, DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Alternatively, the memory (e.g., 1130) in embodiments of the present application may be integrated in the processor (e.g., 1110).

Furthermore, the present application also provides a computer readable storage medium, where computer instructions are stored, where the computer instructions, when executed on a computer, cause operations and/or flows performed by a transmitting device or a receiving device in the embodiments of the method of the present application to be performed.

The present application also provides a computer program product comprising computer program code or instructions which, when run on a computer, cause operations and/or flows performed by a transmitting device or a receiving device in method embodiments of the present application to be performed.

In addition, the application also provides a chip, which comprises a processor. The memory for storing the computer program is provided separately from the chip and the processor is configured to execute the computer program stored in the memory such that the operations and/or processes performed by the transmitting device or the receiving device in any one of the method embodiments are performed.

Further, the chip may also include a communication interface. The communication interface may be an input/output interface, an interface circuit, or the like. Further, the chip may further include a memory.

In addition, the application also provides a communication system which comprises the transmitting end equipment and the receiving end equipment in the embodiment of the application.

It should also be noted that the memory described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein. In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. The storage medium includes various media capable of storing program codes such as a U disk, a mobile hard disk, a ROM, a RAM, a magnetic disk or an optical disk.

It is appreciated that reference throughout this specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, various embodiments are not necessarily referring to the same embodiments throughout the specification. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It is also to be understood that in the present application, when "if" and "if" all refer to a corresponding process that a network element will perform under some objective condition, and are not limited in time, nor do they require that a judgment be made in the implementation of the network element, nor are other limitations meant to be implied.

It will also be appreciated that in embodiments of the present application, "B corresponding to A" means that B is associated with A, from which B may be determined. It will be further understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.

Claims (18)

1. A communication method based on low density parity check, LDPC, codes, the method comprising:

Acquiring an information bit sequence:

Determining an LDPC matrix, wherein the LDPC matrix is determined based on an LDPC base matrix, a lifting value Zc and a translation value of the base matrix, the translation value of the base matrix is determined based on a second row sequence, a second column sequence and the lifting value Zc, the number of elements of the second row sequence is equal to the number of rows of the base matrix and the elements of the second row sequence are in one-to-one correspondence with the rows of the base matrix, the number of elements of the second column sequence is equal to the number of columns of the base matrix and the elements of the second column sequence are in one-to-one correspondence with the columns of the base matrix, the second row sequence is determined based on a first row sequence, the number of elements of the first row sequence is smaller than the number of elements of the second row sequence, and the number of elements of the first column sequence is smaller than the number of elements of the second column sequence;

and encoding the information bit sequence according to the LDPC matrix to obtain a code word sequence.

2. A communication method based on low density parity check LDPC code is characterized in that,

Acquiring a symbol sequence;

determining an LDPC matrix based on an LDPC base matrix, a lifting value Z _c and a translation value of the base matrix, wherein the translation value of the base matrix is determined based on a second row sequence, a second column sequence and the lifting value Z _c, the number of elements of the second row sequence is equal to the number of rows of the base matrix and the elements of the second row sequence are in one-to-one correspondence with the rows of the base matrix, the number of elements of the second column sequence is equal to the number of columns of the base matrix and the elements of the second column sequence are in one-to-one correspondence with the columns of the base matrix,

The second row sequence is determined based on a first row sequence, the second column sequence is determined based on a first column sequence, the number of elements of the first row sequence is smaller than the number of elements of the second row sequence, and the number of elements of the first column sequence is smaller than the number of elements of the second column sequence;

And decoding the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

3. The method according to claim 1 or 2, wherein the translation value of 1 element in row i and column j in the base matrix is based on a summation of t first values, wherein t is a positive integer,

The first numerical value is determined based on R (i), C (j), zc, p and s corresponding to the first numerical value, wherein R (i) is an element corresponding to the row i in the second row sequence, C (j) is an element corresponding to the column j in the second column sequence, s is an integer between 1 and t, and p is a prime number corresponding to the Z _c.

4. The method of claim 3, wherein the step of,

And p is the prime number base of the Zc, or the p is the maximum prime number capable of dividing the maximum lifting value in all lifting value sets, or the p is the prime number capable of dividing any lifting value in all lifting value sets, or the p is the maximum value or the minimum value in the prime number base corresponding to all lifting value sets.

5. The method according to claim 3 or 4, wherein the translation value SV _i,j of the 1 element in row i and column j in the base matrix satisfies the following formula:

Wherein, the

S is a positive integer, u _s+v_s =s+1, both u _s and v _s are positive integers,

Said Z _{id_s} being determined based on said Zc, said p and said s, or, said Z _{id_s} =1,

The k _s is a positive integer multiple of p ^s-1.

6. The method according to claim 3 or 4, wherein the translation value SV _i,j of the 1 element in row i and column j in the base matrix satisfies the following formula:

Wherein, the

The N _s is a numerical value stored in a position corresponding to a row R1 and a column C1 of a table s, the row R1 is a row associated with the R (i) in the table s, the column C1 is a column associated with the C (j) in the table s, the s is a positive integer,

Said Z _{id_s} being determined based on said Zc, said p and said s, or, said Z _{id_s} =1,

The k _s is a positive integer multiple of p ^s-1.

7. The method according to claim 6, characterized in that the value N _s stored in the table s satisfies the following formula:

Wherein, u _s+v_s = s+1, both u _s and v _s are positive integers.

8. The method according to claim 6 or 7, wherein,

All rows of the table s are in one-to-one correspondence with elements in the second row sequence, and all columns of the table s are in one-to-one correspondence with elements in the second column sequence.

9. The method of any one of claims 5 to 8, wherein the Z _{id_s} is determined based on the Zc, the p, and the s, and the Z _{id_s} satisfies the following formula Z _{id_s}＝mod(mod(Zc,p^s+1),p^s).

10. The method according to any one of claims 1 to 9, wherein the base matrix is determined based on a split sequence θ, the element of the split sequence θ corresponding to row i of the base matrix being θ (i), wherein θ (i) is equal to a first character indicating that row i of the base matrix is not associated with any row of the base matrix, otherwise, row i of the base matrix is indicated to be associated with row θ (i) of the base matrix, and that θ (i) is less than i,

The first row sequence is composed of a plurality of elements, the plurality of elements are in one-to-one correspondence with a plurality of rows of the base matrix, the plurality of rows are such that θ (i) is equal to all rows i of the first character, the elements corresponding to row i1 in the second row sequence are equal to the elements corresponding to row i1 in the first row sequence, the elements corresponding to row i2 in the second row sequence are equal to the elements corresponding to row θ (i 2) in the second row sequence, wherein θ (i 1) is equal to the first character, θ (i 2) is not equal to the first character,

Or alternatively, the first and second heat exchangers may be,

The first row sequence is composed of a plurality of elements, the elements are in one-to-one correspondence with core rows of the base matrix, the elements corresponding to the row i1 in the second row sequence are equal to the elements corresponding to the row i1 in the first row sequence, the elements corresponding to the row i3 in the second row sequence are equal to the elements corresponding to the row i3 DEG in the first row sequence, the elements corresponding to the row i2 in the second row sequence are equal to the elements corresponding to the row theta (i 2) in the second row sequence, wherein the row i1 is any row in the core of the base matrix, the row i3 is any row which is remained except the core row in all rows of the theta (i) equal to the first character, the i3 DEG is smaller than the i3, the theta (i 1) is equal to the first character, and the theta (i 2) is not equal to the first character.

11. The method of claim 10, wherein the step of determining the position of the first electrode is performed,

The first line sequence is determined based on the split sequence, wherein the plurality of elements in the first line sequence are all included in the split sequence, a first element in the first line sequence is a minimum value in the split sequence, an element corresponding to a first line in the first line sequence is smaller than an element corresponding to a second line, and a line number of the first line is smaller than a line number of the second line.

12. The method of any one of claims 1 to 11, wherein the first column sequence comprises a plurality of elements in one-to-one correspondence with a core column of the base matrix, wherein elements in the second column sequence corresponding to columns j1 are equal to elements in the first column sequence corresponding to columns j1, wherein columns j1 are any one of the core columns.

13. The method according to any one of claims 1 to 9, wherein,

The base matrix is a cyclic shift space coupling low-density parity check QCSC-LDPC base matrix, the coupling length of subcodes of the base matrix is L, the coupling width is w, the number of rows of each base matrix block in the subcodes is m and the number of columns is n,

The first row sequence is composed of (m x (w+c)) elements, the elements in the first row sequence are in one-to-one correspondence with the first (m x (w+c)) row of the base matrix, c is an integer,

The first column sequence is composed of (n x (w+c)) elements, the elements in the first column sequence are in one-to-one correspondence with the previous (n x (w+c)) columns of the base matrix,

The second row sequence is composed of (m+w)) elements, the elements in the second row sequence are circularly multiplexed based on the first row sequence,

The second column sequence is composed of (n×l) elements, and the elements in the second column sequence are cyclically multiplexed based on the first column sequence.

14. The method of claim 13, wherein c is equal to-1, -2, 0, 1, or 1.

15. A communication device comprising at least one processor and interface circuitry for receiving signals from other communication devices than the communication device and transmitting signals from the processor to the processor or sending signals from the processor to other communication devices than the communication device, the processor implementing the method of any of claims 1 to 14 by logic circuitry or executing code instructions.

16. The communication device of claim 15, wherein the communication device is a chip or a system-on-chip.

17. A computer-readable storage medium, characterized in that the storage medium has stored therein a computer program or instructions, which, when executed, cause the method of any of claims 1 to 14 to be implemented.

18. A computer program product comprising a computer program which, when run, causes the method of any one of claims 1 to 14 to be carried out.