CN116760416B - A dual-configuration mode high-precision oversampling analog-to-digital converter control module - Google Patents

Abstract

The invention relates to a control module of a double-configuration mode high-precision oversampling analog-to-digital converter, belonging to the field of analog integrated circuit design. Conventional high-precision oversampling ADCs all use a single mode to control the ADC functions, such as using a pin only mode or using a register configuration mode only, which can lead to inflexible register configuration. In order to solve the problem, the invention provides a circuit structure, and the selection of the function of the IO port and the selection of the input and output of the IO port are realized through control signals, so that the high-precision oversampling analog-to-digital converter in a double configuration mode is realized, and the configuration of the ADC is more flexible.

Description

A dual-configuration mode high-precision oversampling analog-to-digital converter control module

Technical field

The invention belongs to the field of analog integrated circuit design, and specifically relates to a dual configuration mode high-precision oversampling analog-to-digital converter control module.

Background technique

Analog-to-digital converter (ADC) is an indispensable key unit in the field of analog integrated circuit design and analog-to-digital mixed processing. Among them, high-precision oversampling ADC is a widely used branch.

Traditional high-precision oversampling ADCs all use a single mode to control the function of the ADC. For example, only pin mode can be used, as shown in Figure 1. Pin mode is to use the pins of the chip to directly configure the functions of the chip. This is simple and reliable for simple applications. There is no need for complex configuration design, and the PCB boards used around the chip are relatively simplified. However, this will bring certain disadvantages, that is, there is no possibility to adjust and modify the configuration after the PCB design is determined, resulting in an inflexible chip usage environment.

Later, for high-precision oversampling ADCs, internal registers appeared to control and configure the chip, such as TI's ADS1258 chip. Users can use the complex register combination inside the chip to flexibly configure high-precision oversampling ADCs. The advantage of this is that when there is a control chip such as FPGA or MCU outside the ADC to control the ADC, the function of the ADC chip can be modified on-site by changing the configuration code of the FPGA or MCU, significantly improving the chip usage conditions. However, this brings corresponding disadvantages, that is, the configuration code is generally stored in the memory chip. The memory chip is susceptible to external interference. If non-volatile memory is not used to store the code, the configuration will be lost when the entire system is powered off. information.

From the perspective of system design complexity, the peripheral circuits used in pin mode are simple and reliable. Do not use memory to store configuration codes, but it is inconvenient to modify after the design is finalized. The peripheral design of using internal registers to control and configure the ADC chip is more complicated, and will use control chips and memory chips such as FPGA or MCU. The design is difficult, but it is more flexible to change the functions of the ADC, such as on-site replacement of sampling channels and more. ADC peripheral functions.

Contents of the invention

In order to optimize the mode control method of high-precision over-sampling ADC and solve the shortcomings of pin mode and use of internal registers for control, the present invention proposes a new internal design structure of high-precision over-sampling ADC to realize the function of IO port through control signals The selection and the selection of IO port input and output.

The working principle is shown in Figure 2:

The control module includes circuit signal strobe Mux1 and circuit signal strobe Mux2, input buffer INBUF, output buffer OUTBUF, an inverter, and a digital module;

PINMOD generates control signals PINMOD Control, PINM1 and PINM2 through the digital module. The IO Pin is the ADC chip pin. PINMOD Control is directly connected to the control end of the input buffer INBUF and is connected to the control end of the output buffer OUTBUF after passing through an inverter. ;The input terminal of the input buffer INBUF is connected to the IO Pin, and the output terminal is connected to the input terminal of the circuit signal strobe Mux1; the input terminal of the output buffer OUTBUF is connected to the output of the circuit signal strobe Mux2, and the output terminal is connected to the IO Pin ;The output of circuit signal strobe Mux1 is connected to function 1 and function 2 inside the ADC chip, and is selected through PINM1; the input of circuit signal strobe Mux2 is connected to function 1 and function 2 inside the ADC chip, and is selected through PINM2;

The circuit signal strobe Mux1 and the circuit signal strobe Mux2 are written by digital codes, and function 1 or function 2 is selected through the PINMOD control signals PINM1 and PINM2; the input buffer INBUF and the output buffer OUTBUF have the same structure, and control the signal. to act as a buffer.

This module is used to control the chip port to achieve mode switching. Makes the chip configuration more flexible.

Description of the drawings

Figure 1 shows the traditional single mode control;

Figure 2 is the schematic diagram of IO PIN controlled by PINMODE signal;

Figure 3 is a schematic diagram of using PINMODE to control the chip configuration mode.

Implementation

The embodiments will be described in detail below with reference to the accompanying drawings.

Figure 2 is the schematic diagram of the IO Pin controlled by the PINMODE signal.

PINMOD Control can control whether the IO Pin is an input pin or an output pin. When PINMOD Control is high level, the input buffer INBUF is turned on, the output buffer OUTBUF is turned off, the IO Pin becomes an input pin, and the signal is input from the outside; when PINMOD Control is high, When the level is low, the input buffer INBUF is closed, the output buffer OUTBUF is opened, IOPin becomes the output pin, and the signal is output internally;

PINM1 controls whether the signal input from the IO Pin controls function 1 or function 2. When PINM1 is high level, it is connected to function 1, and when it is low level, it is connected to function 2. PINM2 controls whether the signal output from IO Pin comes from function 1 or function 2. When PINM2 is high level, the signal of IO PIN comes from function 1, and when it is low level, the signal of IO PIN comes from function 2.

When the PINMODE pin is connected to the power supply, the control signals PINM1 and PINM2 generated by the digital module are high level, making the pin connection function 1. PINMOD Control is generated according to whether the pin is input or output. When the pin is When the pin is input, the PINMOD Control generated is high level. When the pin is an output pin, the PINMODControl generated is low level. At this time, the chip is in pin configuration mode;

When the PINMODE pin is grounded, the control signals PINM1 and PINM2 generated by the digital module are low level, causing the pin to connect to function 2. PINMOD Control is generated according to whether the pin is an input or an output. When the pin is an input When the pin is an output pin, the generated PINMOD Control is high level. When the pin is an output pin, the generated PINMODControl is low level. At this time, the ADC chip is in the register configuration mode.

Figure 3 is a schematic diagram of using PINMODE to control the chip configuration mode. The left and right sides of the figure are the typical IO of the chip. The configuration status of the IO Pin of different chips can be controlled by using independent PINMOD. Generally speaking, a high-precision oversampling ADC will contain an analog modulator and a digital filter. At the same time, a series of control logic will be added to the periphery of the digital filter to form the digital control module of the ADC. Each pin that needs to be multiplexed will use the structure shown in Figure 2 to achieve different pin functions in different modes.

The SCLK on the left port is the SPI clock, and DIN/MOD share an IO Pin. When the chip is in register configuration mode, the PINMODE pin is connected to ground. Under the control of the control signal generated by PINMOD, the DIN/MOD pin is first set as the input terminal, and then the corresponding PINM1 sets the function to DIN. At this time, the SPI data Accessible via DIN port. When the chip is in pin configuration mode, the PINMODE pin is connected to the power supply. In a similar manner to the above, the port will be defined as MOD and can be used to connect 0 or 1 to configure the ADC chip.

The M1 and M0 ports on the right output the SDM modulation data of the ADC when the chip is in pin configuration mode. When the chip is in register mode, it is used as DR1 and DR0 to configure the chip conversion speed.

DOUT is the data serial output port of the chip. The final processing data of the chip is transmitted from here to the external FPGA or MCU chip to collect the ADC conversion results.

When the chip enters the pin configuration mode, since there is no synchronous clock inside the chip, SYNC will provide a synchronous signal input. This synchronous signal input can make the result of each sampling of the ADC chip in a user-controllable mode. When the chip is in register configuration mode, SYNC does not need to provide a synchronization signal because SCLK will become the synchronization clock in this mode. In register configuration mode, the function of this pin will change from providing a synchronization signal input to a control signal that can control the on or off of the chip's internal high-pass filter.

MCLK is the main clock output of the ADC chip in pin configuration mode. Users can use the MCLK of the chip to drive other chips when the chip is in use, so that other chips can be synchronized by the ADC chip. PHS can select the size of the internal digital filter when the chip is in register configuration mode.

By controlling PINMODE to connect to power or ground, and combining control modules with different functions, the pins correspond to different pin functions under different PINMODEs, realizing flexible conversion between pin configuration mode and register configuration mode, and solving the problem of having only one single mode. Defects.

Claims (6)

1. A dual configuration mode high-precision oversampling analog-to-digital converter control module, characterized in that the control module includes a circuit signal gate Mux1 and a circuit signal gate Mux2, an input buffer INBUF, and an output buffer OUTBUF, An inverter, a digital module; PINMOD generates control signals PINMOD Control, PINM1 and PINM2 through the digital module. The IO Pin is the ADC chip pin. PINMOD Control is directly connected to the control end of the input buffer INBUF and is connected to the control end of the output buffer OUTBUF after passing through an inverter. ;The input terminal of the input buffer INBUF is connected to the IO Pin, and the output terminal is connected to the input terminal of the circuit signal strobe Mux1; the input terminal of the output buffer OUTBUF is connected to the output of the circuit signal strobe Mux2, and the output terminal is connected to the IO Pin ;The output of the circuit signal strobe Mux1 is connected to function 1 and function 2 inside the ADC chip, and is selected through the control signal PINM1; the input of the circuit signal strobe Mux2 is connected to function 1 and function 2 inside the ADC chip, and is selected through the control signal PINM2 make a choice; The circuit signal strobe Mux1 and the circuit signal strobe Mux2 are written by digital codes, and function 1 or function 2 is selected through the PINMOD control signals PINM1 and PINM2; the input buffer INBUF and the output buffer OUTBUF have the same structure, and control the signal. to act as a buffer. 2. The control module according to claim 1, characterized in that when the PINMOD is connected to the power supply, the ADC chip is in the pin configuration mode, and when the PINMOD is connected to the ground, the ADC chip is in the register configuration mode, specifically: When the PINMOD pin is connected to the power supply, the control signals PINM1 and PINM2 generated by the digital module are high level, causing the pin to connect to function 1. The control signal PINMOD Control is generated according to whether the pin is input or output. When the pin When the pin is an input pin, the generated PINMOD Control is high level. When the pin is an output pin, the generated PINMOD Control is low level. At this time, the chip is in pin configuration mode; When the PINMOD pin is grounded, the control signals PINM1 and PINM2 generated by the digital module are low level, causing the pin to connect to function 2. PINMOD Control is generated according to whether the pin is an input or an output. When the pin is an input When the pin is an output pin, the generated PINMOD Control is high level. When the pin is an output pin, the generated PINMOD Control is low level. At this time, the ADC chip is in the register configuration mode. 3. The control module according to claim 2, wherein the function 1 is M1/M0 in the pin configuration mode, and the function 2 is DR1/DR0 in the register configuration mode. 4. The control module according to claim 2, wherein the function 1 is MOD in the pin configuration mode, and the function 2 is DIN in the register configuration mode. 5. The control module according to claim 2, wherein the function 1 is to provide synchronization signal input in the pin configuration mode, and the function 2 is to control the opening or closing of the chip's internal high-pass filter in the register configuration mode. Signal. 6. The control module according to claim 2, wherein the function 1 is MCLK in pin configuration mode, and the function 2 is PHS in register configuration mode.