CN116156897B

CN116156897B - Three-dimensional memory, preparation method, and storage system

Info

Publication number: CN116156897B
Application number: CN202211174501.2A
Authority: CN
Inventors: 刘小欣; 霍宗亮
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-09-26
Filing date: 2022-09-26
Publication date: 2025-09-05
Anticipated expiration: 2042-09-26
Also published as: CN116156897A; CN120769502A

Abstract

The disclosure provides a three-dimensional memory, a preparation method and a memory system, and relates to the technical field of semiconductor chips. The array device comprises a first substrate, a storage stack structure and a grid line isolation structure. The memory stack structure is disposed on the first substrate and includes gate insulating layers and gate layers alternately stacked. The gate line isolation structure includes a plurality of conductive portions each penetrating the storage stack structure and the first substrate, and a first insulating layer disposed between the conductive portions and the gate layer and between adjacent conductive portions. The first peripheral device is disposed on a side of the first substrate remote from the storage stack. The conductive portion extends to the first peripheral device and is electrically connected with the first peripheral device.

Description

Three-dimensional memory, preparation method and memory system

Technical Field

The disclosure relates to the technical field of semiconductor chips, and in particular relates to a three-dimensional memory, a preparation method and a memory system.

Background

As the feature size of the memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which results in a storage density of 2D or planar NAND flash memory approaching the upper limit.

To overcome the limitation imposed by the 2D or planar NAND flash memory, memories having a three-dimensional structure (3D NAND) have been developed to increase the memory density by three-dimensionally disposing memory cells on a substrate. The memory area of the current three-dimensional structure memory is small.

Disclosure of Invention

The embodiment of the disclosure provides a three-dimensional memory, a preparation method and a memory system, and aims to solve the problem of small memory area of the memory with a current three-dimensional structure.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

In one aspect, a three-dimensional memory is provided that includes an array device and a first peripheral device. The array device comprises a first substrate, a storage stack structure and a grid line isolation structure. The memory stack structure is disposed on the first substrate and includes gate insulating layers and gate layers alternately stacked. The gate line isolation structure includes a plurality of conductive portions, each of which penetrates through the storage stack structure and the first substrate, and a first insulating layer disposed between the conductive portion and the gate layer and between adjacent conductive portions. The first peripheral device is disposed on a side of the first substrate remote from the storage stack. The conductive portion extends to the first peripheral device and is electrically connected with the first peripheral device.

The conductive portion is provided in the gate line isolation structure, and the conductive portion can be used to connect the first peripheral device and the array device, so that the area (area in the XY plane) of the entire array device can be increased. Or, under the condition that the area of the array device is unchanged, the conductive part passes through the grid line isolation structure, so that the storage space is increased.

In some embodiments, the first peripheral device includes a second substrate, a peripheral interconnect conductor layer, and a second insulating layer. The peripheral interconnect is disposed on the second substrate. The second insulating layer is arranged on one side of the peripheral interconnection conductor layer away from the second substrate. The conductive part penetrates through the second insulating layer and is contacted with the peripheral interconnection conductor layer.

In some embodiments, the conductive portion includes a first portion and a second portion. The first portion is a portion of the conductive portion located in the array device, and the second portion is a portion of the conductive portion extending into the second insulating layer. The first portion and the second portion are smoothly connected.

In some embodiments, the orthographic projection of the conductive portion on the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer on the second substrate.

In some embodiments, the conductive portion is of the same material as the peripheral interconnect conductor layer.

In some embodiments, the array device further includes a third insulating layer. The third insulating layer is disposed between the first substrate and the first peripheral device. The conductive part penetrates through the third insulating layer.

In some embodiments, the first insulating layer is further disposed between the conductive portion and the first substrate.

In some embodiments, the array device further includes a channel structure, a bit line contact, and a gate line contact. The channel structure extends through the memory stack structure. The bit line contact is positioned on one side of the channel structure away from the first substrate and is electrically connected with the channel structure. The grid line contact is positioned on one side of the grid layer away from the first substrate and is electrically connected with the grid layer. Wherein the conductive portion is flush with at least one of the bit line contact and the gate line contact, each of which is away from an end of the first substrate.

In some embodiments, the plurality of conductive portions includes at least one of a first conductive portion and a second conductive portion. The first conductive part is electrically connected with the bit line contact, and the second conductive part is electrically connected with the gate line contact.

In some embodiments, the three-dimensional memory further includes a second peripheral device. The first peripheral device comprises a first transistor or a first transistor and a second transistor, the second peripheral device comprises a second transistor, and threshold voltages of the first transistor and the second transistor are different. The second peripheral device is disposed on a side of the array device remote from the first peripheral device. The plurality of conductive portions includes a third conductive portion electrically connected to the second peripheral device.

On the other hand, the preparation method of the three-dimensional memory comprises the steps of forming a storage stacked structure penetrated by a grid line gap on an initial substrate, wherein the storage stacked structure comprises alternately stacked grid insulating layers and grid layers, and the grid line gap extends into the initial substrate. A first insulating layer provided with a plurality of first grooves arranged at intervals is formed in the gate line gap, and at least the gate layer is shielded by the first insulating layer. A sacrificial portion is formed in the first groove. And thinning the initial substrate to expose the gate line gaps, thereby forming a first substrate. The first peripheral device is stacked on a side of the first substrate remote from the storage stack structure. The plurality of sacrificial portions are replaced with a plurality of conductive portions that extend to and are electrically connected with the first peripheral device.

In some embodiments, the first peripheral device includes a second substrate, a peripheral interconnect conductor layer, and a second insulating layer. The peripheral interconnect conductor layer is disposed on the second substrate. The second insulating layer is arranged on one side of the peripheral interconnection conductor layer away from the second substrate.

The step of replacing the plurality of sacrificial portions with the plurality of conductive portions includes removing the plurality of sacrificial portions. Etching is performed at the position of the first groove to form a second groove, and the second groove penetrates through the second insulating layer and exposes the peripheral interconnection conductor layer. A conductive portion is formed in the second groove.

In some embodiments, the notches of the second slots proximate to the peripheral interconnect conductor layer are all obscured by the peripheral interconnect conductor layer.

In some embodiments, the memory stack structure is also penetrated by the channel structure.

The method for manufacturing the three-dimensional memory further comprises the step of forming a bit line contact hole on one side of the channel structure away from the first substrate while etching the first groove to form a second groove.

The method for manufacturing the three-dimensional memory further comprises the step of forming a bit line contact in the bit line contact hole, and the bit line contact is electrically connected with the channel structure.

In some embodiments, the plurality of conductive portions includes a first conductive portion that is electrically connected to the bit line contact.

In some embodiments, the step of etching at the location of the first trench and the step of forming the second trench are performed simultaneously, and the method for manufacturing the three-dimensional memory further comprises forming a gate line contact hole at a side of the gate layer away from the first substrate.

The method for manufacturing the three-dimensional memory further comprises the step of forming a grid line contact in the grid line contact hole, and the grid line contact is electrically connected with the grid layer.

In some embodiments, the plurality of conductive portions includes a second conductive portion, the second conductive portion being electrically connected to the gate line contact.

In some embodiments, the method of fabricating a three-dimensional memory further includes stacking a second peripheral device on a side of the array device remote from the first peripheral device. The first peripheral device comprises a first transistor or a first transistor and a second transistor, the second peripheral device comprises a second transistor, and threshold voltages of the first transistor and the second transistor are different. The plurality of conductive portions further includes a third conductive portion electrically connected to the second peripheral device.

In some embodiments, after the step of thinning the initial substrate to expose the gate line slit and forming the first substrate, the method of fabricating the three-dimensional memory further includes forming a third insulating layer on a side of the substrate remote from the storage stack structure before the step of stacking the first peripheral devices on a side of the first substrate remote from the storage stack structure.

In some embodiments, the first insulating layer covers sidewalls of the gate line slit.

In some embodiments, the first slot extends through the first insulating layer.

In yet another aspect, a memory system is provided that includes a three-dimensional memory as described above, and a controller electrically connected to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, comprising a storage system as described above.

It can be appreciated that, the method for manufacturing a three-dimensional memory, the storage system and the electronic device provided in the foregoing embodiments of the present disclosure may refer to the beneficial effects of the three-dimensional memory, and are not described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

Fig. 1 is a block diagram of a three-dimensional memory provided by an embodiment of the present disclosure.

Fig. 2 is an equivalent circuit diagram of one memory cell block in the three-dimensional memory shown in fig. 1.

Fig. 3 is a block diagram of a three-dimensional memory provided in an embodiment of the present disclosure.

Fig. 4 is a top view of the three-dimensional memory of fig. 3.

Fig. 5 is a cross-sectional view taken along A1-A2 of fig. 4.

Fig. 6 is a block diagram of another three-dimensional memory provided in accordance with an embodiment of the present disclosure.

Fig. 7 is a block diagram of the second peripheral device added to fig. 5.

Fig. 8 is a flow chart of a method of fabricating a three-dimensional memory according to some embodiments of the present disclosure.

Fig. 9 to 21 are process step diagrams of a method for manufacturing a three-dimensional memory.

FIG. 22 is a block diagram of a storage system according to some embodiments.

FIG. 23 is a block diagram of a storage system according to further embodiments.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

In the description of the present disclosure, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and each includes a combination of A, B and C of a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes three combinations of A only, B only, and a combination of A and B.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

In the present disclosure, "above," "over," and "over" should be interpreted in the broadest sense such that "over" means not only "directly over" but also includes the meaning of "over" with an intermediate feature or layer therebetween, and "over" or "over" means not only "over" or "over" but also includes the meaning of "over" or "over" without an intermediate feature or layer therebetween (i.e., directly over).

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As used herein, the term "substrate" refers to a material to which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed by memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., lateral surface) of the substrate or source layer.

Some embodiments of the present disclosure provide a three-dimensional memory. Fig. 1 is a block diagram of a three-dimensional memory provided by an embodiment of the present disclosure. Fig. 2 is an equivalent circuit diagram of one memory cell block in the three-dimensional memory shown in fig. 1.

Referring to fig. 1, a three-dimensional memory 10 may include an array device 200. The three-dimensional memory 10 may further include a peripheral circuit M electrically connected to the array device 200.

Specifically, the array device 200 includes one or more memory cell blocks BLK, such as memory cell blocks BLK 1-BLKm (m is an integer greater than or equal to 2). Each of the plurality of memory cell blocks BLK in fig. 1 may be implemented as shown in fig. 2.

Referring to fig. 2, the memory cell block BLK includes at least one (e.g., one; e.g., a plurality of) memory cell strings NS, and may further include a source layer SL. A memory cell string NS (e.g., each memory cell string NS) in the memory cell block BLK is electrically connected to the source layer SL. It should be noted that the number of memory cell strings in a memory cell block shown in fig. 2 is merely illustrative, and the embodiments of the present disclosure do not limit the number of memory cell strings in a memory cell block.

The source layer SL may include a semiconductor material such as single crystal silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer may also include undoped regions.

A memory cell string NS (e.g., each memory cell string NS) includes a plurality of transistors. The plurality of transistors may include at least one (e.g., one; e.g., a plurality of) memory cells MC, such as memory cells MC 1-MC 4. The plurality of memory cells MC may be connected in series with each other. The memory cell MC may be configured to store data. In the array device 200, the individual memory cells MC may be distributed in an array to form a memory cell array. It should be noted that the number of memory cells MC in a memory cell string shown in fig. 2 is merely illustrative, and the number of memory cells in a memory cell string is not limited in the embodiments of the present disclosure.

In some embodiments, the plurality of transistors in the memory cell string NS may further include at least one (e.g., one; e.g., a plurality of) string selection transistors SST and at least one (e.g., one; e.g., a plurality of) selection transistors GST located on both sides of each of the memory cells MC in series with each other. Among them, the string selection transistor SST and the ground selection transistor GST may be connected in series with each memory cell MC. Also, one pole (e.g., drain) of a string of selection transistors SST may be electrically connected to the bit line BL, and one pole (e.g., source) of a ground selection transistor GST may be electrically connected to the source layer SL.

The memory cell string NS may extend in a direction perpendicular to the source layer SL, or the memory cell string NS may extend in a thickness direction of the three-dimensional memory 10. Based on this, a plurality of transistors in the memory cell string NS may be distributed in a direction perpendicular to the source layer SL. Further, the channels of the respective transistors in a memory cell string NS may form a channel structure, and the channel structure 235 may include the channels of the respective memory cells MC in the memory cell string NS, and may further include channels of one or more string selection transistors SST and one or more ground selection transistors GST. The channel structure 235 may extend in a direction perpendicular to the source layer SL.

With continued reference to fig. 2, the memory cell block BLK may further include a plurality of gate lines G surrounding the channel structure. A channel structure and a gate line G surrounding the channel structure may form a transistor, wherein the gate line G may serve as a gate of the transistor, and may control an on state of the transistor.

Specifically, at least one (e.g., one; e.g., another) of the plurality of gate lines G may be configured as a word line WL, e.g., word lines WL 1-WL 4. A word line WL (e.g., each word line WL) may serve as a gate of each memory cell MC located on the same logical page in the memory cell block BLK. At least one (e.g., one; e.g., another) of the plurality of gate lines G may be configured as a string selection line SSL, which may serve as a gate of one or more string selection transistors SST. At least one (e.g., one; e.g., another) of the plurality of gate lines G may be configured as a ground selection line GSL, which may serve as a gate of one or more ground selection transistors GST.

In a memory cell block BLK, string selection lines SSL1 to SSL3 are separated from each other, ground selection lines GSL are electrically connected to each other, and word lines WL at the same level may be electrically connected to each other. Further, the bit lines BL1 to BL3 are separated from each other. The embodiment of the present disclosure does not particularly limit the connection relationship of the signal lines described above. For example, in some embodiments, the ground selection lines GSL may be separated from each other like the string selection lines SSL1 to SSL 3.

With continued reference to fig. 1, peripheral circuitry M is electrically connected to array device 200, and in particular, peripheral circuitry M may be electrically connected to one or more channel structures. The peripheral circuit M is configured to receive signals, including, for example, an address signal ADDR, a command signal CMD, a control signal CTRL, and a data signal DA, from outside the three-dimensional memory 10, and to input signals to the array device 200 and/or receive signals from the array device 200 in response to the signals, so that the three-dimensional memory 10 can perform memory operations, such as a read operation, a program operation, and an erase operation.

In some embodiments, the peripheral circuit M may include various sub-circuits such as a page buffer 100c, a row decoder 100a, and control logic (which may also be referred to as logic circuits) 100 b. The peripheral circuit M may also include other sub-circuits such as input/output circuits (e.g., I/O buffers), voltage generation circuits for voltages required for internal operation of the three-dimensional memory 10, and error correction circuits for correcting errors in data read from the array device 200, for example.

Specifically, in some embodiments, control logic 100b is electrically coupled to row decoder 100a, and may also be electrically coupled to voltage generation circuitry and input/output circuitry. Control logic 100b may control the operation of three-dimensional memory 10. Illustratively, the control logic 100b may generate various internal control signals for use in the three-dimensional memory 10 in response to the control signal CTRL. For example, when the three-dimensional memory 10 performs a program operation or an erase operation, the control logic 100b may adjust the magnitudes of voltages supplied to the word lines WL and the bit lines BL.

In some embodiments, the row decoder 100a selects at least one word line WL, at least one string selection line SSL, and at least one ground selection line GSL in response to the address signal ADDR. Illustratively, the row decoder 100a may be configured to transmit a voltage for performing a memory operation to the selected word line WL.

In some embodiments, page buffer 100c may be electrically connected to bit line BL. The page buffer 100c may be configured to sense a voltage on the selected bit line BL to read data stored in the memory cell. The page buffer 100c may also be configured to temporarily store write data to be written (or programmed) into the memory cells.

Referring to fig. 3, the three-dimensional memory 10 may include an array device 200 and a first peripheral device 100. Wherein the array device 200 may be referred to the description above. The first peripheral device 100 may include at least one (e.g., one, as well as a plurality) of the various sub-circuits in the peripheral circuit M described above. Illustratively, the first peripheral device 100 may include all of the sub-circuits in the peripheral circuit M. Also by way of example, the first peripheral device 100 may include a row decoder 100a and not include a page buffer 100c. Also exemplary, the first peripheral device 100 may include at least one of a page buffer 100c, a control logic 100b, and an input/output circuit, without including the row decoder 100a.

The first peripheral device 100 may be stacked with the array device in a thickness direction (i.e., Z-axis direction) of the three-dimensional memory 10. The positive Z-axis direction is a direction from the ground selection transistor GST to the string selection transistor SST in the memory cell string NS. The first peripheral device 100 may be stacked under the three-dimensional memory 10 in the negative Z-axis direction, and in particular, the first peripheral device 100 is located at a side of the memory cell string NS remote from the string selection transistor SST.

As described above, the array device 200 needs to be electrically connected to the first peripheral device 100. In some embodiments, the array device 200 may be electrically connected to the first peripheral device 100 through a plurality of conductive portions, which may be located at the periphery of the memory cell array in the array device 200, but this may result in an increase in the area (area in the XY plane) of the entire array device 200. Alternatively, in the case where the area of the array device 200 is unchanged, a portion of the area of the memory cell array is sacrificed to dispose the conductive portions, thereby losing some memory space.

In other embodiments, the conductive portions 2322 may be inserted into the memory cell array, so as to ensure the area occupied by the memory cell array on the premise that the area of the array device 200 is unchanged. Fig. 4 is a top view of the three-dimensional memory of fig. 3, and fig. 5 is a cross-sectional view of fig. 4 taken along line A1-A2.

Referring to fig. 4 and 5, in the three-dimensional memory, the array device 200 includes a first substrate 220, a memory stack structure 231, and a channel structure 235.

The first substrate 220 refers to a material layer to which a subsequent layer may be added. The first substrate 220 itself may be patterned. Subsequent layers added on the first substrate 220 may be patterned or may remain unpatterned. In addition, the first substrate 220 may include at least one of a variety of semiconductor materials such as amorphous silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, etc., and may include at least one of a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Illustratively, the first substrate 220 may be partially or fully doped to function as the source layer SL. Alternatively, the first substrate 220 may be made of a non-conductive material such as glass, plastic, or sapphire wafer, and the source layer SL may be disposed under the first substrate 220 (Z-axis negative direction), for example, the source layer SL may be located between the first substrate 220 and the first peripheral device 100, for example.

The storage stack structure 231 is disposed on the first substrate 220, and the storage stack structure 231 includes gate insulating layers 2311 and gate layers 2312 alternately stacked. Specifically, the memory stack structure 231 includes a plurality of gate layers 2312 stacked with a gate insulating layer 2311 disposed between each adjacent two of the gate layers 2312. In addition, a gate insulating layer 2311 may be disposed over a top gate layer 2312. A gate insulating layer 2311 may also be disposed under the bottom gate layer 2312.

The material of the gate insulating layer 2311 is an insulating material, for example, one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, but other suitable materials are also possible.

The gate layer 2312 may include a plurality of gate lines at the same level (the same distance from the first substrate 220 in the Z-axis direction). The gate layer 2312 may include a conductive material including, but not limited to, any combination of one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, and silicide. In some embodiments, each gate layer 2312 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 2312 includes a doped polysilicon layer.

The channel structure 235 extends through the memory stack structure 231, specifically, along the Z-axis direction, and the channel structure 235 extends in a plurality of gate layers 2312 (or gate lines) that are stacked. In some embodiments, the channel structure 235 also extends into the first substrate 220, enabling electrical connection of the channel structure 235 with the source layer SL. For example, the bottom of the channel structure 235 may be flush with the lower surface of the first substrate 220 (the surface remote from the storage stack structure 231). As another example, the bottom of the channel structure 235 does not penetrate the lower surface of the first substrate 220, and it can be said that a portion of the first substrate 220 is located under the channel structure 235. A plurality of gate layers 2312 (or a plurality of gate lines G) may surround the channel structure 235, and a plurality of transistors in the memory cell string may be formed.

It should be noted that the number and distribution of the channel structures 235 shown in fig. 4 and 5 are only illustrative, and the embodiments of the present disclosure do not limit the number and distribution of the channel structures 235.

In some embodiments, channel structure 235 includes a semiconductor channel that extends through storage stack structure 231, and may further include a tunneling layer disposed between the gate line and the semiconductor channel, and a charge storage layer disposed between the tunneling layer and the gate line, and may further include a barrier layer disposed between the charge storage layer and the gate line.

The semiconductor channel material may include a semiconductor material, such as one or more of amorphous, polycrystalline, or single crystal silicon, among others. The semiconductor channel may be electrically connected with the source layer SL.

The material of the tunneling layer may include an insulating material, such as one or a combination of silicon oxide, silicon nitride, or silicon oxynitride. Electrons and holes in the semiconductor channel may tunnel through the tunneling layer into the charge storage layer.

The charge storage layer may be configured to store charge, and one or more memory cells in the string of memory cells may be operated by storing charge in or removing charge from the charge storage layer. The material of the charge storage layer may comprise one or a combination of silicon nitride, silicon oxynitride, silicon.

The barrier layer may be configured to prevent charges stored in the charge storage layer from leaking to the gate line. The material of the barrier layer may include an insulating material, for example, the material of the barrier layer is one or a combination of more of silicon oxide, silicon nitride, or silicon oxynitride.

With continued reference to fig. 4 and 5, the array device 200 further includes a gate line isolation structure extending through the storage stack structure 231 in the Z-axis direction. Illustratively, a gate line isolation structure may be configured to define the memory cell block BLK. For example, the portion between two gate line isolation structures may be a memory cell block BLK, and the two gate line isolation structures may be two adjacent gate line isolation structures or may be disposed at a distance from each other. Also illustratively, a gate line isolation structure may be configured to define the gate line G in the gate layer 2312. For example, a gate line G may be located between two adjacent gate line isolation structures.

The storage stack structure 231 may be provided with a gate line slit in which a gate line isolation structure is disposed. In some examples, the gate line slit also extends through the first substrate 220, and the gate line isolation structure extends into the first substrate 220 along the gate line slit.

The gate line isolation structure includes a plurality of conductive portions 2322 and a first insulating layer 2321. The plurality of conductive portions 2322 are disposed at intervals along the length direction (z-axis direction) of the gate line isolation structure.

A conductive portion 2322 (e.g., each conductive portion 2322) may be located in the gate line slit and penetrate the storage stack 231 and the first substrate 220 in the Z-axis direction. The conductive portion 2322 extends to the first peripheral device 100 and is electrically connected to the first peripheral device 100, and the conductive portion 2322 passes out of the array device 200 to be electrically connected to the first peripheral device 100. For example, if a connection portion (may also be referred to as a conductor portion) for electrically connecting with the array device 200 in the first peripheral device 100 is located at the upper surface of the first peripheral device 100, the conductive portion 2322 exposed from the array device 200 may be in contact with the connection portion to achieve electrical connection, or may be electrically connected with the connection portion through a conductive material. Also by way of example, if the connection in the first peripheral device 100 for electrical connection with the array device 200 is located inside the first peripheral device 100 (below the upper surface of the first peripheral device 100), the conductive portion 2322 in the array device 200 may extend into the inside of the first peripheral device 100 and be electrically connected (e.g., in contact with) the connection, for example, the conductive portion 2322 in the array device 200 may pass through the upper surface of the first peripheral device 100 and continue onto the connection in the first peripheral device 100 to be in contact with the connection.

Illustratively, the cross section (cross section perpendicular to the Z-axis direction) of the conductive portion 2322 may be a regular shape or an irregular shape such as a circle, a rectangle, or the like.

The conductive portion 2322 is made of a conductive material, for example, one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials.

The conductive portion 2322 is provided in the gate line isolation structure, the conductive portion 2322 may be used to connect the first peripheral device 100 and the array device 200, so that an area (an area in the XY plane) of the entire array device 200 may be increased. Alternatively, in the case where the area of the array device 200 is not changed, the conductive portion 2322 passes through the gate line isolation structure, increasing the memory space.

The first insulating layer 2321 is disposed between the conductive portions 2322 and the gate layer 2312, and between adjacent conductive portions 2322, so that the conductive portions 2322 and the gate layer 2312 are insulated from each other, and the adjacent conductive portions 2322 are insulated from each other.

Illustratively, first insulating layer 2321 is also disposed between conductive portion 2322 and first substrate 220. For example, the sidewalls of the gate line slit are covered with the first insulating layer 2321, which means that the portion of the gate line slit penetrating the storage stack structure 231 and the portion of the gate line slit penetrating the first substrate 220 may be formed in one patterning process, for example, both of which are etched using the same mask, which may be advantageous in simplifying the process.

In some examples, the first insulating layer 2321 fills in the gate line slit, and a plurality of through trenches (may also be referred to as through holes) are opened on the first insulating layer 2321. The through-slot penetrates the first insulating layer 2321 in the Z-axis direction, and at this time, the storage stack structure 231 and the first substrate 220 are penetrated. The conductive portion 2322 is disposed in the through groove, and the conductive portion 2322 is exposed to the through groove. The material of the first insulating layer 2321 is an insulating material, for example, one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

With continued reference to fig. 4 and 5, the first peripheral device 100 is disposed on a side of the first substrate 220 remote from the storage stack 231. In some embodiments, to form the peripheral circuits described above, the first peripheral device 100 includes a second substrate. The material of the second substrate may be selected from the materials listed above for the first substrate 220. The material of the first substrate 220 may be the same as or different from the material of the second substrate. Illustratively, the material of the second substrate may include at least one of a variety of semiconductor materials including silicon, germanium, gallium arsenide, indium phosphide, and the like. Based on this, a source region and a drain region of a transistor may be partially doped on the second substrate with a portion between the source region and the drain region in the second substrate as an active region, and an insulating layer and a gate of the transistor are formed over the active region, thereby constituting a transistor in the peripheral device. The first peripheral device 100 further includes a peripheral interconnect layer disposed on the second substrate. The peripheral interconnect layer may be disposed between the first substrate 220 and the second substrate.

The peripheral interconnect layer is used to make electrical connection of the sub-circuits in the first peripheral device 100 to other devices (e.g., the array device 200, and also the second peripheral device 300, infra). For example, the peripheral interconnect layer may electrically connect the transistors of the first peripheral device 100 with other components.

The peripheral interconnect layer includes a peripheral interconnect conductor layer 140 disposed on the second substrate. The peripheral interconnect conductor layer 140 is configured to electrically connect sub-circuits (e.g., transistors) in the first peripheral component with the conductive portions 2322 in the array device 200. Illustratively, the peripheral interconnect conductor layer 140 may be in contact with the conductive portions 2322 in the array device 200. When the peripheral interconnect layer includes a plurality of conductor layers, the peripheral interconnect conductor layer 140 may be the uppermost conductor layer or any conductor layer other than the uppermost layer. The material of the peripheral interconnect conductor layer 140 is a conductive material, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicide, but may be other suitable materials.

The peripheral interconnect layer also includes a second insulating layer 130. The second insulating layer 130 is disposed on a side of the peripheral interconnect conductor layer 140 remote from the second substrate such that the second insulating layer 130 covers the peripheral interconnect conductor layer 140. The material of the second insulating layer 130 is an insulating material, for example, one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, and may be other suitable materials.

The conductive portions 2322 of the array device 200 extend through the second insulating layer 130 and electrically connect, e.g., contact, with the peripheral interconnect conductor layer 140. This allows peripheral circuitry in the first peripheral device 100 to be electrically connected to memory cells in the array device 200. Illustratively, the conductive portion 2322 includes a first portion that is a portion of the conductive portion 2322 located in the array device 200 (i.e., a portion that extends through the memory stack structure 231 and the first substrate 220), and a second portion that is a portion of the conductive portion 2322 that extends into the second insulating layer 130. The first portion and the second portion are joined smoothly, i.e. there is no significant step at the interface where the two are joined.

For example, the through trenches in the array device 200 mentioned above that extend through the memory stack 231 and the first substrate 220 (e.g., through the first insulating layer 2321), also extend through the second insulating layer 130. Specifically, the storage stack structure 231 and the first substrate 220 are etched to form a first trench, and then the first trench is etched until the second insulating layer 130 is etched through, so as to form a through trench (which may also be referred to as a second trench). Based on this process, the walls of the through-slots have no significant steps. Thereafter, the conductive portion 2322 including the first portion and the second portion is obtained after one filling in the through groove. I.e. the first and second parts are not spliced, which is advantageous for simplifying the process.

Illustratively, the orthographic projection of the conductive portion 2322 onto the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer 140 onto the second substrate. For example, the lower surface (surface close to the second substrate) of the conductive portion 2322 may be orthographic projected onto the second substrate within orthographic projection of the peripheral interconnect conductor layer 140 onto the second substrate, and a gap may be provided therebetween. For another example, the front projection of the upper surface (surface away from the second substrate) of the conductive portion 2322 onto the second substrate is located within the front projection of the peripheral interconnect conductor layer 140 onto the second substrate, and a gap may be provided between the front projections. Thus, when a new through trench is formed in the second insulating layer 130, the etching is stopped until the peripheral interconnect conductor layer 140 is etched, i.e., the peripheral interconnect conductor layer 140 may also function as a stop.

Illustratively, the material of conductive portion 2322 is the same as the material of peripheral interconnect conductor layer 140. This helps to enhance the coupling force between the conductive portion 2322 and the peripheral interconnect conductor layer 140, so that the electrical connection performance between the two is ensured.

In some embodiments, the array device 200 further includes a third insulating layer 210. The third insulating layer 210 is disposed between the first substrate 220 and the first peripheral device 100. For example, the third insulating layer 210 may cover a lower surface of the first substrate 220 (a surface of the first substrate 220 close to the second substrate) in contact with the lower surface of the first substrate 220.

Based on this, the conductive portion 2322 also penetrates the third insulating layer 210. For example, a through slot that extends through the storage stack 231 and the first substrate 220 (e.g., in the first insulating layer 2321) also extends through the third insulating layer 210 and the second insulating layer 130. Specifically, the storage stack structure 231 and the first substrate 220 are etched to form a first trench, and then the first trench is etched until the third insulating layer 210 and the second insulating layer 130 are etched through, so as to form a through trench (which may also be referred to as a second trench).

The material of the third insulating layer 210 is an insulating material, for example, the insulating material may be referred to in connection with the description of the material of the first insulating layer 2321. The material of the third insulating layer 210 may be the same as or different from that of the first insulating layer 2321.

Since the two layers of the array device 200 and the first peripheral device 100 adjacent to each other are the third insulating layer 210 and the second insulating layer 130, the materials of the two layers are similar, so that the bonding of the array device 200 and the first peripheral device 100 can be more stable.

In some examples, a bonding interface 400 may be provided between the array device 200 and the first peripheral device 100. For example, a bonding interface 400 may be provided between the third insulating layer 210 and the second insulating layer 130, and the third insulating layer 210 and the second insulating layer 130 may be bonded to each other through the bonding interface 400. The array device 200 and the first peripheral device 100 are coupled at a bonding interface 400.

In some embodiments, with continued reference to fig. 5, the array device 200 may further include a bit line contact 234. The bit line contact 234 is located on a side of the channel structure 235 remote from the first substrate and is electrically connected to the channel structure 235. For example, a lower end of bit line contact 234 may be electrically connected, e.g., in contact, with channel structure 235. An upper end of bit line contact 234 may be coupled to bit line BL. The material of bit line contact 234 may be a conductive material and may be selected from the materials described above for conductive portion 2322. Illustratively, the material of bit line contact 234 may be the same as the material of conductive portion 2322, based on which both may be accomplished in one process step. For example, the process of forming the through trench in which the bit line contact 234 is located in the bit line contact hole and the conductive portion 2322 by etching the third insulating layer and/or the second insulating layer may be completed in one process step, and then, the bit line contact 234 and the conductive portion 2322 may be formed by filling conductive material in the bit line contact hole and the through trench at the same time.

Illustratively, since the bit line contact hole and the through via may be recessed based on the same surface, the respective upper openings of the bit line contact hole and the through via are at the same level, and thus the conductive portion 2322 located in the through via is flush with the end (i.e., upper end) of the bit line contact 234 located in the bit line contact hole, which is away from the first substrate, respectively.

Illustratively, a plurality of conductive portions 2322 may include a conductive portion 2322 electrically connected to the bit line contact 234, such conductive portion 2322 being referred to hereinafter as a first conductive portion. One or more first conductive portions may be included in the three-dimensional memory. Based on this, the first peripheral device 100 may include a page buffer.

In some embodiments, with continued reference to fig. 5, the array device 200 may further include a gate line contact 236. The gate line contact 236 is located on a side of the gate layer 2312 remote from the first substrate and is electrically connected, e.g., in contact, with the gate layer 2312 (also referred to as a gate line). The material of the gate line contact 236 may be a conductive material, and may be selected from the materials of the conductive portion 2322 described above. Illustratively, the gate line contact 236 may be the same material as the conductive portion 2322, based on which both may be accomplished in one process step. For example, the process of forming the through groove where the conductive portion 2322 is formed by etching the third insulating layer and/or the second insulating layer and the gate line contact hole where the gate line contact 236 is located may be completed in one process step, and then, the gate line contact hole and the through groove may be filled with a conductive material at the same time, so as to form the gate line contact 236 and the conductive portion 2322.

Illustratively, since the gate line contact hole and the through groove may be recessed based on the same surface, the upper openings of the gate line contact hole and the through groove are on the same level, and thus the conductive portion 2322 located in the through groove is flush with the end (i.e., upper end) of the gate line contact 236 located in the gate line contact hole, which is away from the first substrate, respectively.

Illustratively, a plurality of conductive portions 2322 may include a conductive portion 2322 electrically connected to the gate line contact 236, such conductive portion 2322 being hereinafter referred to as a second conductive portion. One or more second conductive portions may be included in the three-dimensional memory. Based on this, the first peripheral device 100 may include a row decoder.

In some embodiments, the plurality of conductive portions 2322 in a gate line isolation structure 232 may include at least one of a first conductive portion and a second conductive portion. For example, the three-dimensional memory includes the first conductive portion and does not include the second conductive portion. For another example, the three-dimensional memory includes the second conductive portion and does not include the first conductive portion. For example, the three-dimensional memory includes a first conductive portion and a second conductive portion, and based on this, the first conductive portion and the second conductive portion may be distributed in different gate line isolation structures 232, or may be distributed in the same gate line isolation structure 232.

Fig. 6 is a block diagram of another three-dimensional memory provided by an embodiment of the present disclosure. Fig. 7 is a block diagram of the second peripheral device 300 added to fig. 5.

Referring to fig. 6 and 7, the peripheral device further includes a second peripheral device 300. The second peripheral device 300 is disposed on a side of the array device 200 remote from the first peripheral device 100. Illustratively, the first peripheral device 100 and the second peripheral device 300 together form the peripheral circuit shown in fig. 1 described above. For example, the first peripheral device 100 may include a row decoder, and the second peripheral device 300 may include a page buffer and control logic therein.

The plurality of conductive portions 2322 in a gate line isolation structure 232 may include a third conductive portion that is electrically connected to the second peripheral device 300. At this time, the third conductive portion may electrically connect the sub-circuit in the first peripheral device 100 with the sub-circuit in the second peripheral device 300. For example, the third conductive portion electrically connects the row decoder with the control logic.

The first peripheral device 100 (or a sub-circuit in the first peripheral device 100) may include a plurality of transistors Q1, and the transistors Q1 are disposed on the first substrate 220. These transistors Q1 include a first transistor, or a first transistor and a second transistor. Meaning that all of these transistors Q1 are first transistors, or some are first transistors and others are second transistors.

The second peripheral device 300 (or a sub-circuit in the second peripheral device 300) may include a plurality of transistors Q2. The transistor Q2 is disposed on the substrate of the second peripheral device 300. Illustratively, these transistors Q2 may include a second transistor. Meaning that all of these transistors Q2 are second transistors, or some are second transistors, and others are transistors having a threshold voltage different from the threshold voltage of the second transistor and the threshold voltage of the first transistor.

The threshold voltages of the first transistor and the second transistor are different. The threshold voltage hereinafter means an absolute value of the threshold voltage.

In some examples, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor. For example, the first transistor may comprise a high voltage transistor, such as a high voltage metal oxide semiconductor field effect transistor (High Voltage Metal Oxide Semiconductor Field-Effect Transistor, HVMOS). The second transistor may comprise a low voltage transistor, for example, a low voltage metal oxide semiconductor field effect transistor (Low Voltage Metal Oxide Semiconductor Field-Effect Transistor, LVMOS). In one possible implementation, the threshold voltage of the third transistor is less than the threshold voltage of the second transistor. The third transistor may comprise a low voltage transistor, for example, a low voltage metal oxide semiconductor field effect transistor (Low Low Voltage Metal Oxide Semiconductor Field-Effect Transistor, LLVMOS).

In other examples, the threshold voltage of the first transistor is less than the threshold voltage of the second transistor. The second transistor may comprise a low voltage transistor, for example, a low voltage metal oxide semiconductor field effect transistor (Low Voltage Metal Oxide Semiconductor Field-Effect Transistor, LVMOS). The first transistor may comprise a low-low voltage transistor, such as a low-low voltage metal oxide semiconductor field effect transistor (Low Low Voltage Metal Oxide Semiconductor Field-Effect Transistor, LLVMOS). In one possible implementation, the threshold voltage of the third transistor is greater than the threshold voltage of the second transistor. For example, the third transistor may include a high voltage transistor, such as a high voltage metal oxide semiconductor field effect transistor (High Voltage Metal Oxide Semiconductor Field-Effect Transistor, HVMOS).

Illustratively, the array device 200 may further include an array interconnect layer 240. The third conductive portion may be electrically connected with the second peripheral device 300 through the array interconnection layer 240. Similar to the peripheral interconnect layer, the array interconnect layer 240 may include a plurality of array interconnect conductor layers, through at least one of which an upper end of the third conductive portion is connected to the second peripheral device 300.

In some examples, a bonding interface 500 may be provided between the array device 200 and the second peripheral device 300. For example, a bonding interface 500 may be provided between the array interconnect layer 240 and the second peripheral device 300 (e.g., peripheral interconnect layer), and the array interconnect layer 240 and the second peripheral device 300 (e.g., peripheral interconnect layer) may be bonded and coupled to each other through the bonding interface 500.

It should be noted that in some embodiments, the array device 200 further includes a device layer 230. The device layer is located between the array periphery layer 240 and the first substrate 220. Therein, in some examples, the device layer 230 may include a storage stack structure 231, a gate line isolation structure 232, a channel structure 235, and the like.

The embodiment also provides a preparation method of the three-dimensional memory. Referring to fig. 8, a method S100 for preparing a three-dimensional memory includes steps S110 to S180.

In step S110, a storage stack structure 231 penetrated by the gate line slit 238 is formed on the initial substrate 221.

Wherein the memory stack structure 231 includes gate insulating layers 2311 and gate layers 2312 alternately stacked. The gate line slit 238 extends into the initial substrate 221. Illustratively, the gate line slit 238 may not extend through the initial substrate 221, which may help provide a stable foundation during fabrication of subsequent structures in the gate line slit 238.

Step S110 may include steps S111-S114. In step S111, referring to fig. 9 and 10, a dielectric stack structure 260 and a channel structure 235 penetrating the dielectric stack structure 260 are formed at one side of the initial substrate 221.

The dielectric stack structure 260 includes gate insulating layers 2311 and gate sacrificial layers 237 alternately stacked. That is, two adjacent gate sacrificial layers 237 are located at both sides of one gate insulating layer 2311 in the Z-axis direction, and two adjacent gate insulating layers 2311 are located at both sides of one gate sacrificial layer 237.

The gate sacrificial layer 237 may include a material having a high etching selectivity with the gate insulating layer 2311. In some examples, each gate insulating layer 2311 includes a silicon oxide layer, and each gate sacrificial layer 237 includes a silicon nitride layer. That is, a plurality of silicon nitride layers and a plurality of silicon oxide layers may be alternately deposited over the initial substrate 221. The gate insulating layer 2311 and the gate sacrificial layer 237 may be formed using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or any combination thereof. Wherein silicon oxide and silicon nitride are pairs of materials having a high etch selectivity, specifically, an etch selectivity between silicon oxide and silicon nitride of greater than 10.

Of course, the gate sacrificial layer 237 and the gate insulating layer 2311 may be other material pairs with high etching selectivity, which are only illustrated herein and not limited thereto.

Thereafter, a channel structure is formed through the dielectric stack structure 260. Illustratively, the channel structure may extend into the initial substrate 221.

For example, a channel hole may be formed through the dielectric stack structure 260, and then the channel structure 235 may be formed in the channel hole. For example, a pattern of channel holes in the photoresist and/or hard mask layer may be defined using photolithographic techniques and channel holes through the dielectric stack structure 260 are formed within the core region by wet and/or dry etching. For example, the Etching process may be a deep Ion reactive Etching (DEEP REACTIVE Ion Etching, DRIE).

In addition, a fourth insulating layer 250 covering the channel structure 235 may be formed, and a material of the fourth insulating layer 250 may be selected from a material of the gate insulating layer 2311. For example, the material of the fourth insulating layer 250 may be the same as that of the gate insulating layer 2311.

In step S112, a gate line slit 238 is formed through the dielectric stack structure 260 and extends into the initial substrate 221.

Illustratively, the gate line slit 238 may be formed by etching downward from the surface of the fourth insulating layer 250. For example, a pattern of trench holes in the photoresist and/or hard mask layer may be defined using photolithographic techniques and gate line slits 238 may be formed through the dielectric stack 260800 within the core region by wet and/or dry etching. For example, the Etching process may be a deep Ion reactive Etching (DEEP REACTIVE Ion Etching, DRIE).

In step S113, referring to fig. 11, the gate sacrificial layer 237 is removed, and a gate layer 2312 is formed at a position where the gate sacrificial layer 237 is located, that is, a gate layer 2312 is formed between two adjacent gate insulating layers 2311. Wherein, the gate line gap 238 is filled with a conductive material between the adjacent gate insulating layers 2311 to form the gate layer 2312.

The gate layer 2312 may be formed between two adjacent gate insulating layers 2311 by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

Conductive materials forming gate layer 2312 include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. In some examples, the material of gate layer 2312 is tungsten.

The gate sacrificial layer 237 is removed to form a gate layer 2312, so that the memory stack structure 231 in which the gate layer 2312 and the gate insulating layer 2311 are alternately stacked is obtained. Wherein the gate layer 2312 occupies the original space of the gate sacrificial layer 237.

Step S114, etching back the conductive material in the gate line slit 238. The conductive material in the gate line slit 238 may be etched back by wet etching and/or dry etching.

In step S120, referring to fig. 12 and 13, a first insulating layer 2321 having a plurality of first grooves H1 formed therein at intervals is formed in the gate line slit 238.

Step S120 includes step S121 and step S122.

In step S121, a first insulating layer 2321 is formed in the gate line slit 238.

Forming the first insulating layer 2321 in the gate line slit 238 may form the first insulating layer 2321 by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. Wherein, the first insulating layer 2321 at least shields the gate layer 2312 the first insulating layer 2321 may function as a gate layer 2312 at the sidewall of the isolation gate line slit 238.

In some examples, the gate line slit 238 extends into the initial substrate 221, and then the first insulating layer 2321 is also formed in the initial substrate 221. For example, the sidewalls of the gate line slit 238 may be entirely covered by the first insulating layer 2321.

In step S122, a plurality of first grooves H1 are formed on the first insulating layer 2321 at intervals.

The first trench H1 in the photoresist and/or hard mask layer may be patterned using a photolithography technique, and the first trench H1 of the first insulating layer 2321 may be formed (e.g., penetrated) by wet etching and/or dry etching. For example, the Etching process may be a deep Ion reactive Etching (DEEP REACTIVE Ion Etching, DRIE).

Step S130 referring to fig. 14, a sacrificial portion 2323 is formed in the first groove H1.

The first groove H1 is filled with a sacrificial material to form a sacrificial portion 2323. The sacrificial material may be selected to have a high etch selectivity to the first insulating layer 2321, for example, the first insulating layer 2321 includes silicon nitride and the sacrificial material includes polysilicon. In some examples, the material of first insulating layer 2321 includes silicon nitride, and the etch ratio between the sacrificial material and the silicon nitride is greater than 30, e.g., the sacrificial material includes carbon, and the etch ratio between carbon and the silicon nitride is greater than 30. Of course, the sacrificial material and the first insulating layer 2321 may be other materials having a high etching selectivity, which is just described above by way of example and not limitation.

In step S140, referring to fig. 15, the initial substrate 221 is thinned to expose the gate line slit 238, thereby forming the first substrate 220.

For example, a Chemical Mechanical Planarization (CMP) and etching process may be used to remove a portion of the initial substrate 221. For example, a large portion is first coarsely ground and then a portion is removed by chemical mechanical fine grinding. In addition, the initial substrate 221 may be thinned in combination with wet etching and/or dry etching to expose the gate line slit 238. In this embodiment, the thinned initial substrate 221 is referred to as a first substrate 220. In step S150, with continued reference to fig. 10, a third insulating layer 210 is formed on a side of the first substrate 220 remote from the storage stack 231.

The third insulating layer 210 may be formed by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

Step S160 referring to fig. 16, the first peripheral device 100 is stacked on a side of the first substrate 220 remote from the storage stack structure 231.

In some examples, the first peripheral device 100 is stacked on a side of the third insulating layer 210 remote from the storage stack structure 231. Illustratively, the first peripheral device 100 includes a second substrate 110, a peripheral interconnect conductor layer 140, and a second insulating layer 130. The peripheral interconnect conductor layer 140 is disposed on the second substrate 110, and the second insulating layer 130 is disposed on a side of the peripheral interconnect conductor layer 140 away from the second substrate 110.

Step S170, replacing the plurality of sacrificial portions 2323 with the plurality of conductive portions 2322, forms the structure shown in fig. 19 and 20.

The conductive portion 2322 extends to the first peripheral device 100 and is electrically connected to the first peripheral device 100. Wherein the top-view shape of the conductive portion is not limited to the shape shown in fig. 13, for example, the shape of the conductive portion may also be a regular shape such as a rectangle or an irregular shape. The positional arrangement of the conductive portions 2322 and the channel structures 235 is not limited to the arrangement shown in fig. 13, for example, in fig. 13 (left-right direction), the number of conductive portions in the gate line slit is smaller than the number of channel structures 235. Step S170 may include:

S171 referring to fig. 17, the plurality of sacrificial portions 2323 are removed. Since the sacrificial portion 2323 is formed of a sacrificial material, the sacrificial material may be removed by wet etching and/or dry etching.

S172 referring to fig. 18, etching is performed at the position of the first trench H1 to form a second trench H2 (i.e., the above through trench), the second trench H2 penetrating the second insulating layer 130 and exposing the peripheral interconnect conductor layer 140.

In some examples, etching is performed at the location of the first trench H1, first etching through the third insulating layer 210, and then etching the second insulating layer 130 to expose the peripheral interconnect conductor layer 140, forming a second trench H2.

The photoresist and/or hard mask layer used in etching the first trench H1 may be continued to be used as a mask, and the third insulating layer 210 and the second insulating layer 130 may be continued to be sequentially etched to the peripheral interconnect conductor layer 140 by wet etching and/or dry etching to form the second trench H2. For example, the Etching process may be a deep Ion reactive Etching (DEEP REACTIVE Ion Etching, DRIE).

S173 referring to fig. 19 and 20, the conductive material is filled in the second groove H2 to form a conductive portion 2322.

In some examples, the bit line contact hole H3 is formed at a side of the channel structure 235 remote from the first substrate 220 at the same time as the step of etching at the location of the first trench H1 to form the second trench H2. The bit line contact hole H3 and the second trench H2 may be formed using the same process.

Simultaneously with the step of forming the conductive portion 2322 in the second trench H2, a bit line contact is formed in the bit line contact hole H3 (filled with a conductive material). Wherein the bitline contacts are electrically connected to the channel structure 235. The bit line contact and the conductive portion 2322 may be fabricated using the same process.

Illustratively, the plurality of conductive portions 2322 includes a first conductive portion that is electrically connected to the bit line contact 234. This allows the first peripheral device 100 to be electrically connected to the bit line contact through the first conductive portion. In some examples, the etching is performed at the location of the first trench H1, and the gate line contact hole H4 is formed at the side of the gate layer 2312 remote from the first substrate 220 at the same time as the step of forming the second trench H2. The gate line contact hole H4 and the second trench H2 may be formed using the same process.

The gate line contact 236 is formed in the gate line contact hole H4 at the same time as the step of forming the conductive portion 2322 in the second trench H2 (filled with a conductive material). Wherein the gate line contact 236 is electrically connected to the gate layer 2312.

Illustratively, the plurality of conductive portions 2322 includes a second conductive portion. The second conductive portion is electrically connected to the gate line contact 236. This may electrically connect the first peripheral device 100 with the gate line contact 236 through the second conductive portion.

It should be noted that the array interconnection layer may also be formed after this step.

Referring to fig. 21, step S180 is to stack a second peripheral device 300 on a side of the array device 200 remote from the first peripheral device 100. The first peripheral device 100 includes a first transistor, or a first transistor and a second transistor. The second peripheral device 300 includes a second transistor, and the threshold voltages of the first transistor and the second transistor are different, as described above with reference to the related description.

The plurality of conductive portions 2322 further includes a third conductive portion that is electrically connected to the second peripheral device 300. Specifically, the third conductive portion is electrically connected to the second peripheral device 300 through the array interconnection layer. In this way, the first peripheral device 100 and the second peripheral device 300 may be electrically connected through the third conductive portion, and the first peripheral device 100 and the second peripheral device 300 may transmit signals.

FIG. 22 is a block diagram of a storage system according to some embodiments. FIG. 23 is a block diagram of a storage system according to further embodiments.

Referring to fig. 22 and 23, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and the three-dimensional memory 10 of some embodiments as described above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., universal flash storage (Universal Flash Storage, UFS) package or Embedded multimedia card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, notebook computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual Reality (VR) devices, augmented Reality (Augmented Reality, AR) devices, or any other suitable electronic device having a memory therein.

In some embodiments, see 22, the memory system 1000 includes a controller 20 and a three-dimensional memory 10, and the memory system 1000 may be integrated into a memory card.

The memory Card includes any one of a PC Card (PCMCIA, personal computer memory Card international association), a Compact Flash (CF) Card, a smart media (SMART MEDIA SM) Card, a memory stick, a Multimedia Card (MMC), a secure digital (Secure Digital Memory Card SD) Card, and UFS.

In other embodiments, referring to fig. 23, a storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a Solid state disk (Solid STATE DRIVES, SSD for short).

In the storage system 1000, in some embodiments, the controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, universal serial bus (Universal Serial Bus, abbreviated USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smartphones, tablets, notebooks, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller, 20 is further configured to process error correction codes with respect to data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable function, such as formatting the three-dimensional memory 10, for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of a variety of interface protocols.

It should be noted that the interface protocol includes at least one of USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, and Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any of a cell phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

The electronic device may include the storage system 1000 described above, and may further include at least one of a central processing unit CPU (Central Processing Unit ), a cache (cache), and the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A three-dimensional memory, comprising: an array device and a first peripheral device;

The array device comprises:

first base;

a memory stack structure, disposed on the first substrate, comprising alternately stacked gate insulating layers and gate layers; and

a gate line isolation structure comprising a plurality of conductive portions and a first insulating layer, wherein each of the plurality of conductive portions penetrates the memory stack structure and the first substrate, and the first insulating layer is disposed between each conductive portion and the gate layer, and between adjacent conductive portions;

The first peripheral device is arranged on a side of the first substrate away from the storage stack structure;

Each of the conductive portions extends to the first peripheral device and is electrically connected to the first peripheral device.

2. The three-dimensional memory according to claim 1, wherein:

The first peripheral device includes:

Second base;

a peripheral interconnect conductor layer, disposed on the second substrate; and

a second insulating layer, disposed on a side of the peripheral interconnect conductor layer away from the second substrate;

Each of the conductive parts passes through the second insulating layer and contacts the peripheral interconnect conductor layer.

3. The three-dimensional memory according to claim 2, wherein:

Each conductive portion includes a first portion and a second portion, the first portion being a portion of each conductive portion located in the array device, and the second portion being a portion of each conductive portion extending into the second insulating layer;

The first portion and the second portion are smoothly connected.

4. The three-dimensional memory according to claim 2, wherein:

The orthographic projection of each conductive portion on the second substrate is located within the orthographic projection of the peripheral interconnect conductor layer on the second substrate.

5. The three-dimensional memory according to claim 2, wherein:

The material of each conductive portion is the same as that of the peripheral interconnect conductor layer.

6. The three-dimensional memory according to claim 1, wherein:

The array device further includes: a third insulating layer disposed between the first substrate and the first peripheral device;

Each of the conductive parts passes through the third insulating layer.

7. The three-dimensional memory according to claim 1, wherein:

The first insulating layer is further disposed between each conductive portion and the first substrate.

8. The three-dimensional memory according to claim 1, wherein:

The array device further comprises:

a channel structure, wherein the channel structure penetrates the memory stack structure;

a bit line contact, located on a side of the channel structure away from the first substrate and electrically connected to the channel structure; and

a gate line contact, located on a side of the gate layer away from the first substrate and electrically connected to the gate layer;

Each of the conductive portions is flush with an end of at least one of the bit line contact and the gate line contact, each of which is away from the first substrate.

9. The three-dimensional memory according to claim 8, characterized in that

The plurality of conductive portions include at least one of a first conductive portion and a second conductive portion; wherein the first conductive portion is electrically connected to the bit line contact, and the second conductive portion is electrically connected to the gate line contact.

10. The three-dimensional memory according to any one of claims 1 to 9, further comprising:

A second peripheral device is provided on a side of the array device away from the first peripheral device; wherein the first peripheral device includes a first transistor, or a first transistor and a second transistor; the second peripheral device includes a second transistor; and the first transistor and the second transistor have different threshold voltages;

The plurality of conductive portions include a third conductive portion electrically connected to a second peripheral device.

11. A method for preparing a three-dimensional memory, comprising:

A memory stack structure penetrated by gate line gaps is formed on an initial substrate; the memory stack structure comprises alternately stacked gate insulation layers and gate layers; the gate line gaps extend into the initial substrate;

forming a first insulating layer with a plurality of first grooves spaced apart from each other in the gate line gap, wherein the first insulating layer at least shields the gate layer;

forming a sacrificial portion in the first groove;

Thinning the initial substrate to expose the gate line gaps to form a first substrate;

stacking a first peripheral device on a side of the first substrate away from the memory stack structure;

The plurality of sacrificial portions are replaced with a plurality of conductive portions, wherein the conductive portions extend to the first peripheral device and are electrically connected to the first peripheral device.

12. The method for preparing a three-dimensional memory according to claim 11, wherein:

The first peripheral device includes: a second substrate, a peripheral interconnect conductor layer and a second insulating layer; the peripheral interconnect conductor layer is arranged on the second substrate, and the second insulating layer is arranged on a side of the peripheral interconnect conductor layer away from the second substrate;

The step of replacing the plurality of sacrificial portions with a plurality of conductive portions comprises:

removing the plurality of sacrificial portions;

Etching at the location of the first groove to form a second groove, wherein the second groove penetrates the second insulating layer and exposes the peripheral interconnect conductor layer;

A plurality of conductive portions are formed in the second groove.

13. The method for preparing a three-dimensional memory according to claim 12, wherein:

The notches of the second grooves close to the peripheral interconnection conductor layer are completely blocked by the peripheral interconnection conductor layer.

14. The method for preparing a three-dimensional memory according to claim 12, wherein:

The storage stack structure is further penetrated by a channel structure;

While etching is performed at the location of the first groove to form the second groove, the method for preparing the three-dimensional memory further includes:

forming a bit line contact hole on a side of the channel structure away from the first substrate;

While forming a plurality of conductive portions in the second grooves, the method for manufacturing the three-dimensional memory further includes forming a bit line contact in the bit line contact hole, wherein the bit line contact is electrically connected to the channel structure.

15. The method for preparing a three-dimensional memory according to claim 14, wherein:

The plurality of conductive portions include a first conductive portion electrically connected to the bit line contact.

16. The method for preparing a three-dimensional memory according to claim 12, wherein:

forming a gate line contact hole on a side of the gate layer away from the first substrate;

While forming a plurality of conductive portions in the second groove, the method for preparing the three-dimensional memory further includes:

A gate line contact is formed in the gate line contact hole, and the gate line contact is electrically connected to the gate layer.

17. The method for preparing a three-dimensional memory according to claim 16, wherein:

The plurality of conductive portions include a second conductive portion; the second conductive portion is electrically connected to the gate line contact.

18. The method for preparing a three-dimensional memory according to claim 11, wherein:

The method for preparing the three-dimensional memory further includes:

A second peripheral device is stacked on a side of the array device away from the first peripheral device; wherein the first peripheral device includes a first transistor, or a first transistor and a second transistor; the second peripheral device includes a second transistor; and the first transistor and the second transistor have different threshold voltages;

The plurality of conductive portions further include a third conductive portion electrically connected to a second peripheral device.

19. The method for preparing a three-dimensional memory according to any one of claims 11 to 18, wherein:

After the step of thinning the initial substrate to expose the gate line gaps to form a first substrate, and before the step of stacking a first peripheral device on a side of the first substrate away from the memory stack structure, the method for preparing the three-dimensional memory further includes:

A third insulating layer is formed on a side of the substrate away from the memory stack structure.

20. The method for preparing a three-dimensional memory according to any one of claims 11 to 18, wherein:

The first insulating layer covers the sidewalls of the gate line gap.

21. The method for preparing a three-dimensional memory according to any one of claims 11 to 18, wherein:

The first groove penetrates the first insulating layer.

22. A storage system, comprising:

The three-dimensional memory according to any one of claims 1 to 10; and

The controller is electrically connected to the three-dimensional memory to control the three-dimensional memory to perform memory operations.