CN114678376B

CN114678376B - Semiconductor structure and its fabrication method, three-dimensional memory

Info

Publication number: CN114678376B
Application number: CN202210302865.8A
Authority: CN
Inventors: 刘文静; 袁伟; 刘磊
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2022-03-25
Filing date: 2022-03-25
Publication date: 2026-03-06
Anticipated expiration: 2042-03-25
Also published as: CN114678376A

Abstract

The disclosure provides a semiconductor structure, a preparation method thereof, a three-dimensional memory, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem that the conductivity of the semiconductor structure is poor. A method of fabricating a semiconductor structure includes forming a dielectric stack structure including gate insulating layers and gate sacrificial layers alternately stacked on one side of a substrate. A channel hole is formed through the dielectric stack structure. And filling a sacrificial material in the channel hole. And removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure comprising alternately stacked gate insulating layers and gate layers. And removing the sacrificial material to expose the channel hole. A dielectric layer is formed within the channel hole. And forming a channel structure in the channel hole. The semiconductor structure is applied to a three-dimensional memory to realize the reading and writing of data.

Description

Semiconductor structure, preparation method thereof and three-dimensional memory

Technical Field

The disclosure relates to the technical field of semiconductor chips, and in particular relates to a semiconductor structure, a preparation method thereof, a three-dimensional memory, a storage system and electronic equipment.

Background

As the feature size of the memory cells approaches the lower process limit, planar processes and fabrication techniques become challenging and costly, which results in a storage density of 2D or planar NAND flash memory approaching the upper limit.

To overcome the limitation imposed by the 2D or planar NAND flash memory, memories having a three-dimensional structure (3D NAND) have been developed to increase the memory density by three-dimensionally disposing memory cells over a substrate.

In the related art, the conductivity of semiconductor structures in some three-dimensional memories is poor.

Disclosure of Invention

The embodiment of the disclosure provides a semiconductor structure, a preparation method thereof and a three-dimensional memory, and aims to solve the problem that the conductivity of the semiconductor structure in the three-dimensional memory is poor.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

in one aspect, a method of fabricating a semiconductor structure is provided. The manufacturing method includes forming a dielectric stack structure including gate insulating layers and gate sacrificial layers alternately stacked on one side of a substrate. A channel hole is formed through the dielectric stack structure. And filling a sacrificial material in the channel hole. And removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure comprising alternately stacked gate insulating layers and gate layers. And removing the sacrificial material to expose the channel hole. A dielectric layer is formed within the channel hole. And forming a channel structure in the channel hole.

The preparation method of the semiconductor structure provided by the embodiment of the disclosure comprises the steps of firstly filling the sacrificial material in the channel hole to obtain the gate layer, then removing the sacrificial material and preparing the dielectric layer in the channel hole. Because the dielectric layer is not manufactured before the grid electrode layer is manufactured, the dielectric layer is protected without additionally adding a sacrificial layer oxide in the process of manufacturing the grid electrode layer, meanwhile, the filling rate of the grid electrode layer between adjacent grid electrode insulating layers can be increased, the conductivity of the grid electrode layer is improved, and the conductivity of a semiconductor structure in the three-dimensional memory is further improved.

In some embodiments, before the sacrificial material is filled in the channel hole, the method further comprises removing part of the gate sacrificial layer by using the channel hole to form a groove. The step of filling the sacrificial material in the channel hole comprises the step of filling the sacrificial material in the channel hole and the groove. The removing the sacrificial material to expose the channel hole includes removing the sacrificial material to expose the channel hole and the recess. The forming a dielectric layer in the channel hole comprises forming a dielectric layer at least filling the groove in the channel hole.

In some embodiments, the forming a dielectric layer within the trench hole that fills at least the recess includes forming a dielectric film that covers the recess and an inner wall of the trench hole, removing portions of the dielectric film that cover the inner wall of the trench hole, and leaving portions of the dielectric film within the recess to form dielectric portions of the dielectric layer within the recess.

In some embodiments, the removing the gate sacrificial layer and forming a gate layer includes forming a gate spacer through the dielectric stack, removing the gate sacrificial layer with the gate spacer, forming a gate gap, and forming a gate layer within the gate gap.

In some embodiments, the forming a gate layer within the gate gap includes forming a protective layer within the gate gap and forming a gate conductive layer within the protective layer. Wherein the protective layer is located between the sacrificial material and the gate conductive layer.

In some embodiments, forming a channel structure within the channel hole includes forming a barrier layer overlying an inner wall of the channel hole and the dielectric layer, forming a storage layer overlying the barrier layer, forming a tunneling layer overlying the storage layer, forming a channel layer overlying the tunneling layer, and filling an insulating material within the channel layer.

In some embodiments, the material of the gate sacrificial layer comprises silicon nitride, and an etch ratio between the sacrificial material and the silicon nitride is greater than 30.

In some embodiments, at least one of the dielectric layer, the dielectric film, and the dielectric portion comprises a material having a dielectric constant greater than 3.9.

In yet another aspect, a semiconductor structure is provided. The semiconductor structure includes a substrate, a memory stack structure, a channel structure, and a dielectric layer. A storage stack structure is located at one side of the substrate, the storage stack structure including gate insulating layers and gate layers alternately stacked. A channel structure extends through the memory stack structure. The dielectric layer is positioned between the gate layer and the channel structure, and the outline of the orthographic projection of the dielectric layer on the substrate is connected with the outline of the orthographic projection of the gate layer on the substrate.

In some embodiments, an orthographic projection of the dielectric layer on the substrate at least partially overlaps an orthographic projection of the gate insulating layer on the substrate.

In some embodiments, the dielectric layer includes a plurality of independently disposed dielectric portions embedded between two adjacent layers of the gate insulating layer.

In some embodiments, the gate layer includes a gate conductive layer, and a protective layer disposed around the gate conductive layer. The protective layer is in contact with the dielectric layer and the gate insulating layer, respectively.

In some embodiments, the dielectric layer comprises a material having a dielectric constant greater than 3.9.

In some embodiments, the channel structure includes a channel layer, an insulating material, and a memory function layer. The insulating material is positioned on the inner side of the channel layer, and the storage function layer is positioned on the outer side of the channel layer. The memory function layer comprises a tunneling layer, a memory layer and a blocking layer which are far away from the channel layer, wherein the blocking layer is in contact with the dielectric layer.

In yet another aspect, a three-dimensional memory is provided. The three-dimensional memory includes the semiconductor structure of some embodiments described above, and a peripheral device electrically connected to the semiconductor structure.

In yet another aspect, a storage system is provided that includes a three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

In yet another aspect, an electronic device is provided, comprising a storage system as described above.

It can be appreciated that, the semiconductor structure, the three-dimensional memory, the storage system and the electronic device provided in the above embodiments of the present disclosure may refer to the beneficial effects of the semiconductor structure, and are not described herein.

Drawings

In order to more clearly illustrate the technical solutions of the present disclosure, the drawings that need to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings may be obtained according to these drawings to those of ordinary skill in the art. Furthermore, the drawings in the following description may be regarded as schematic diagrams, not limiting the actual size of the products, the actual flow of the methods, the actual timing of the signals, etc. according to the embodiments of the present disclosure.

FIG. 1 is a perspective block diagram of a three-dimensional memory according to some embodiments;

FIG. 2 is a cross-sectional view of a three-dimensional memory according to some embodiments;

FIG. 3 is a cross-sectional view of a memory cell string along section line AA' in the three-dimensional memory shown in FIG. 1;

FIG. 4 is an equivalent circuit diagram of a memory cell string;

FIG. 5A is a block diagram of a semiconductor structure according to some embodiments;

FIG. 5B is a block diagram of the semiconductor structure of FIG. 5A at a stage of fabrication;

Fig. 6 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

FIGS. 7A-7J are block diagrams of semiconductor structures at various stages of fabrication according to some embodiments;

FIG. 8 is a flow chart of the fabrication of a semiconductor structure according to some embodiments;

FIG. 9 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

FIG. 10 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 11 is a block diagram of a semiconductor structure according to some embodiments;

Fig. 12A is a flow chart of fabrication of a semiconductor structure according to some embodiments;

Fig. 12B is a flow chart of fabrication of a semiconductor structure according to some embodiments;

Fig. 13 is a flow chart of fabrication of a semiconductor structure according to some embodiments;

Fig. 14 is a block diagram of a semiconductor structure in accordance with some embodiments;

Fig. 15 is a block diagram of a semiconductor structure in accordance with some embodiments;

FIG. 16 is a block diagram of a semiconductor structure according to some embodiments;

FIG. 17 is a block diagram of a storage system according to some embodiments;

FIG. 18 is a block diagram of a storage system according to further embodiments.

Detailed Description

The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by one of ordinary skill in the art based on the embodiments provided by the present disclosure are within the scope of the present disclosure.

In the description of the present disclosure, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

The terms "first" and "second" are used below for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present disclosure, unless otherwise indicated, the meaning of "a plurality" is two or more.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

At least one of "A, B and C" has the same meaning as at least one of "A, B or C" and each includes a combination of A, B and C of a alone, B alone, C alone, a combination of a and B, a combination of a and C, a combination of B and C, and a combination of A, B and C.

"A and/or B" includes three combinations of A only, B only, and a combination of A and B.

The use of "adapted" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action "based on" one or more of the stated conditions or values may be based on additional conditions or beyond the stated values in practice.

As used herein, "about," "approximately" or "approximately" includes the stated values as well as average values within an acceptable deviation range of the particular values as determined by one of ordinary skill in the art in view of the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system).

In the present disclosure, "above," "over," and "over" should be interpreted in the broadest sense such that "over" means not only "directly over" but also includes the meaning of "over" with an intermediate feature or layer therebetween, and "over" or "over" means not only "over" or "over" but also includes the meaning of "over" or "over" without an intermediate feature or layer therebetween (i.e., directly over).

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

As used herein, the term "substrate" refers to a material to which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

The term "three-dimensional memory" refers to a semiconductor device formed by memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) arranged in an array on a major surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertically" means nominally perpendicular to a major surface (i.e., lateral surface) of the substrate or source layer.

Fig. 1is a schematic perspective view of a three-dimensional memory according to some embodiments of the present disclosure, fig. 2 is a cross-sectional view of the three-dimensional memory, fig. 3 is a cross-sectional view of one memory cell string of the three-dimensional memory in fig. 1 along a section line AA', and fig. 4 is an equivalent circuit diagram of the memory cell string in fig. 3.

In fig. 1 and 2, the three-dimensional memory 10 extends in an X-Y plane, and the first direction X and the second direction Y are two orthogonal directions in a plane (for example, a plane in which the source layer SL is located) of the semiconductor structure 200, for example, the first direction X is an extending direction of the word line WL, and the second direction Y is an extending direction of the bit line BL. The third direction Z is perpendicular to the plane in which the semiconductor structure 200 lies, i.e., perpendicular to the X-Y plane.

As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined in a third direction Z relative to the substrate or source layer of the semiconductor device when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

In order to more clearly show the structure of the device, in fig. 2, a view of the array region CA and a view of the stair region SS are shown, the view of the array region CA is based on the left-side coordinate system, the view of the stair region SS is based on the right-side coordinate system, that is, the view of the array region CA shows the cross-sectional structure along the Y-direction, and the view of the stair region SS shows the cross-sectional structure along the X-direction.

Referring to fig. 1 and 2, some embodiments of the present disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200. The semiconductor structure 200 may include a source layer SL, and a memory function structure 270. As shown in fig. 2, the three-dimensional memory 10 may further include a peripheral device 100 coupled to the semiconductor structure 200. The peripheral device 100 may be disposed on a side of the memory function structure 270 remote from the source layer SL.

The source layer SL may include a semiconductor material such as single crystal silicon, single crystal germanium, a group III-V compound semiconductor material, a group II-VI compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Illustratively, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

The semiconductor structure 200 may include an array of memory cell transistor strings (referred to herein as "memory cell strings," e.g., NAND memory cell strings) 400. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400.

Specifically, referring to fig. 3 and 4, the memory cell string 400 may include a plurality of transistors T (e.g., T1 to T6 in fig. 4), and one transistor T (e.g., one of T1 to T6) may be provided as one memory cell, and the transistors T are connected together to form a memory cell string having a plurality of memory cells. A transistor T (e.g., each transistor T) may be formed of a semiconductor channel 241 and one gate line G surrounding the semiconductor channel 241. Wherein the gate line G is configured to control the on state of the transistor.

It should be noted that the numbers of transistors in fig. 1 to 4 are only illustrative, and the memory cell string of the three-dimensional memory provided in the embodiments of the present disclosure may further include other numbers of transistors, for example, 4, 16, 32, and 64.

Further, in the third direction Z, the lowermost gate line of the plurality of gate lines G (e.g., the gate line closest to the source layer SL of the plurality of gate lines G) is configured as a source select gate SGS configured to control the on state of the transistor T6, and thus the on state of the source channel in the memory cell string 400. The uppermost one of the plurality of gate lines G (e.g., the gate line farthest from the source layer SL among the plurality of gate lines G) is configured as a drain select gate SGD configured to control the on state of the transistor T1 and thus the on state of the drain channel in the memory cell string 400. The gate lines positioned in the middle of the plurality of gate lines G may be configured as a plurality of word lines WL including, for example, word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

With continued reference to fig. 1 and 2, in some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled with the memory cell string 400. The array interconnect layer 290 may include a drain terminal (i.e., bit line BL) of the memory cell string 400, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, including, for example, a bit line contact BL-CNT coupled to the bit line BL, a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may further include one or more first interconnect conductor layers 291. The first interconnection conductor layer 291 may include a plurality of connection lines, such as bit lines BL, and word line connection lines WL-CL coupled with the word lines WL. The material of the first interconnection conductor layer 291 and the contact may be a conductive material, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, but other suitable materials are also possible.

Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and/or mixed signal control and sensing circuitry for supporting the operation (or operation) of the array device including, but not limited to, page buffers, decoders (e.g., row and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (Programmable Logic Device, PLDs) or Memory circuitry (e.g., static Random-Access Memory (SRAM)).

Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include a transistor 120.

The material of the substrate 110 may be monocrystalline silicon, or may be other suitable materials, such as silicon germanium, or a silicon-on-insulator film.

The peripheral interconnect layer 130 is coupled to the transistor 120 to enable transmission of electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131 and may further include one or more second interconnect conductor layers 132. The different second interconnect conductor layers 132 may be coupled by contacts. The material of the second interconnection conductor layer 132 and the contact may be a conductive material, such as one or more of tungsten, cobalt, copper, aluminum, and metal silicide, and may be other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, for example, one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, and may be other suitable materials.

The peripheral interconnect layer 130 may be coupled with the array interconnect layer 290 such that the semiconductor structure 200 and the peripheral device 100 may be coupled. In particular, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, peripheral circuits in the peripheral device 100 may be coupled to the memory cell strings in the semiconductor structure 100 to enable transmission of electrical signals between the peripheral circuits and the memory cell strings. In some possible implementations, an adhesive interface 500 may be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 may be adhered and coupled to each other through the adhesive interface 500.

In some related art, in the process of manufacturing a semiconductor structure, a portion of the gate sacrificial layer 03 is removed by using the channel hole to form a sacrificial layer oxide 01, and then a dielectric layer 02 and a channel structure 06 are formed in the channel hole, as shown in fig. 5A. That is, the sacrificial layer oxide 01 is provided between the dielectric layer 02 and the gate sacrificial layer 03, the dielectric layer 02 is located between the gate insulating layer 05 and the channel structure 06, and the dielectric layer 02 covers the surfaces of the plurality of gate insulating layers 05 on the side close to the channel structure 06. The material of the dielectric layer 02 includes a material with a high dielectric constant, for preventing electron leakage in the channel structure 06. The dielectric layer 02 may include aluminum oxide (Al ₂O₃), hafnium oxide (HfO ₂), tantalum pentoxide (Ta ₂O₅), titanium dioxide (TiO ₂), silicon oxynitride (SiO _xN_y), or any combination thereof.

The sacrificial layer oxide 01 is disposed between the dielectric layer 02 and the gate sacrificial layer 03, and is used for preventing the dielectric layer 02 from being damaged in the subsequent process of removing the gate sacrificial layer 03, and the sacrificial layer oxide 01 can be removed together in the process of removing the gate sacrificial layer 03. The gate sacrificial layer 03 and the sacrificial layer oxide 01 are removed by a wet etching process. However, in the case of insufficient etching, the sacrificial layer oxide 01' remains in the gate gap 04, as shown in fig. 5B, resulting in a problem that the filling rate of the gate layer formed later in the gate gap 04 is low, and thus the conductivity of the semiconductor structure in the three-dimensional memory is poor.

Based on this, some embodiments of the present disclosure provide a method of fabricating a semiconductor structure. As shown in FIGS. 6 and 7A, the method for fabricating the semiconductor structure includes steps S10-S16.

Step S10, a dielectric stack structure 800 is formed on one side of the substrate 280. The dielectric stack structure 800 includes gate insulating layers 221 and gate sacrificial layers 222 alternately stacked.

As shown in fig. 7A, a dielectric stack structure 800 is fabricated on a substrate 280. The dielectric stack structure 800 includes a plurality of gate insulating layers 221 and gate sacrificial layers 222 alternately stacked. That is, two adjacent gate sacrificial layers 222 are located at both sides of one gate insulating layer 221 in the third direction Z, and two adjacent gate insulating layers 221 are located at both sides of one gate sacrificial layer 222 in the third direction Z.

The gate sacrificial layer 222 may include a material having a high etching selectivity with the gate insulating layer 221. In some examples, each gate insulating layer 221 includes a silicon oxide layer, and each gate sacrificial layer 222 includes a silicon nitride layer. That is, a plurality of silicon nitride layers and a plurality of silicon oxide layers may be alternately deposited over the substrate 280. The gate insulating layer 221 and the gate sacrificial layer 222 may be formed using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD), atomic layer deposition (Atomic Layer Deposition, ALD), or any combination thereof. Wherein silicon oxide and silicon nitride are pairs of materials having a high etch selectivity, specifically, an etch selectivity between silicon oxide and silicon nitride of greater than 10.

Of course, the gate sacrificial layer 222 and the gate insulating layer 221 may be other material pairs with high etching selectivity, which is only illustrated herein and not limited thereto.

In some examples, the substrate 280 may be a single layer substrate, which may include a semiconductor material, which may be, for example, silicon (Si), germanium (Ge), siGe semiconductor, compound semiconductor, alloy semiconductor, or the like. In other examples, the single layer substrate may also be made of a non-conductive material such as glass, plastic, or sapphire wafer. In addition, in other examples, the substrate 280 may also be a composite substrate, in particular, the composite substrate includes a base layer, a first sacrificial layer, and a stop layer, and the dielectric stack structure 800 may be formed on a side of the stop layer away from the first sacrificial layer. The base layer may comprise amorphous silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials, and may also be made of non-conductive materials such as glass, plastic, or sapphire wafers. The material of the first sacrificial layer may be an insulating material, such as silicon oxide, silicon nitride, or the like. The material of the stop layer may be a semiconductor material, such as one or more of amorphous, polycrystalline, or single crystal silicon.

It should be noted that, in some embodiments, the step of fabricating the source layer SL further includes fabricating the source layer SL with the substrate 280, to obtain the base 210 including the substrate 280 and the source layer SL, or fabricating the source layer SL after removing the substrate, to obtain the base 210 including the source layer SL but without the substrate 280, for example, removing the substrate after the channel structure is fabricated, which is not limited in this disclosure. The substrate 280 is shown in fig. 7A, and the substrate 280 will be omitted in other figures.

Step S11 is to form a channel hole 300 penetrating the dielectric stack structure 800.

As shown in connection with fig. 7B, a pattern of channel holes in the photoresist and/or hard mask layer may be defined using photolithographic techniques and channel holes 300 may be formed through the dielectric stack structure 800 within the core region by wet and/or dry etching. For example, the Etching process may be a deep Ion reactive Etching (DEEP REACTIVE Ion Etching, DRIE).

Step S12, filling the sacrificial material 320 in the channel hole 300.

As shown in connection with fig. 7D, a sacrificial material 320 is filled in the channel hole 300 to maintain the morphology and the internal space of the channel hole 300 that has been currently fabricated, and to prevent the morphology and the internal space of the channel hole 300 from being changed when other structures are subsequently removed and/or formed.

The sacrificial material 320 may be selected to have a high etch selectivity to the gate sacrificial layer 222, for example, the gate sacrificial layer 222 comprises silicon nitride and the sacrificial material 320 comprises polysilicon. In some examples, the material of the gate sacrificial layer 222 includes silicon nitride, and the etch ratio between the sacrificial material 320 and the silicon nitride is greater than 30, e.g., the sacrificial material 320 includes carbon, and the etch ratio between carbon and silicon nitride is greater than 30.

Of course, the sacrificial material 320 and the gate sacrificial layer 222 may be other materials with a high etching selectivity, and the above is merely illustrative and not limitative.

Step S13, removing the gate sacrificial layer 222 and forming the gate layer 260 to obtain a memory stack structure including the gate insulating layers 221 and the gate layer 260 alternately stacked.

The gate sacrificial layer 222 may be removed by removing the gate sacrificial layer 222 using a wet etching process. For example, the gate sacrificial layer 222 is etched at the exposed position of the gate sacrificial layer 222 using an etching solution.

As shown in fig. 7F, after the gate sacrificial layer 222 is removed, a gate gap 340 is formed at a position where the gate sacrificial layer 222 is originally located, that is, a gate gap 340 is formed between two adjacent gate insulating layers 221. Wherein, since the channel hole 300 is filled with the sacrificial material 320, the sacrificial material 320 is connected with the gate insulating layer 221, thereby being capable of supporting the gate insulating layer 221 without collapsing, and maintaining the gate gap 340.

As shown in connection with fig. 7G, the gate electrode 260 may be formed by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof, within the gate gap 340 between two adjacent gate insulating layers 221.

The gate layer 260 includes a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. In some examples, the material of gate layer 260 is tungsten. The gate layer 260 extends along the first direction X.

After forming the gate layer 260 in the gate gap 340, a memory stack structure 220 is obtained in which the gate layer 260 and the gate insulating layer 221 are alternately stacked. Wherein the gate layer 260 occupies the original space of the gate sacrificial layer 222.

Since the dielectric layer 240 is not formed yet when the gate layer 260 is formed, there is no need to add an additional sacrificial layer oxide to protect the dielectric layer 240, and there is no problem that the sacrificial layer oxide is not etched enough to occupy the internal space of the gate gap 340, so that the filling rate of the gate layer 260 in the gate gap 340 can be improved.

Step S14, removing the sacrificial material 320 to expose the channel holes 300.

After the gate layer 260 is formed, two adjacent gate insulating layers 221 may be supported by the gate layer 260 to be spaced apart from each other, so that the sacrificial material 320 may be removed.

The sacrificial material 320 may be removed by wet etching and/or dry etching. After the sacrificial material 320 is removed, the channel hole 300 formed in step 11 is exposed, as shown in fig. 7H.

Step S15 is to form a dielectric layer 240 in the channel hole 300.

As shown in connection with fig. 7I and 7J, the dielectric layer 240 may be formed by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. Dielectric layer 240 is in contact with at least gate layer 260.

Dielectric layer 240 may comprise a high dielectric constant material. In the semiconductor industry, a high dielectric constant generally has the meaning that the dielectric constant k of a material is higher than the dielectric constant k of silicon dioxide, i.e., 3.9. The dielectric constant of the material of the dielectric layer 240 may be 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, etc. Materials for dielectric layer 240 include, but are not limited to, aluminum oxide (Al ₂O₃) hafnium oxide (HfO ₂), tantalum pentoxide (Ta ₂O₅), titanium dioxide (TiO ₂), silicon oxynitride (SiO _xN_y), or any combination thereof.

The dielectric layer 240 is located between the gate layer 260 and the channel structure 230, and can prevent electron leakage of the channel structure 230 and improve reliability of the semiconductor structure 200.

Step S16, forming a channel structure 230 in the channel hole 300.

As shown in fig. 14 to 16, the channel structure 230 may include a channel layer 231, an insulating material 232 located inside the channel layer 231, and a memory function layer 233 located outside the channel layer 231. Specifically, the memory function layer 233 may be formed on the inner wall (the inner wall includes the side wall and the bottom wall) of the trench hole 300, the trench layer 231 may be formed on the inner wall of the memory function layer 233, and the insulating material 232 may be filled in the inner wall of the trench layer 231.

Wherein the channel structure 230 is located inside the dielectric layer 240. After the channel structure 230 is formed, the channel structure 230, and a plurality of gate layers 260 and gate insulating layers 221 disposed around the channel structure 230 together constitute the semiconductor structure 200. Specifically, one channel structure 230, and a plurality of gate layers 260 and gate insulating layers 221 surrounding the channel structure 230 constitute a memory cell string 400.

Wherein the insulating material 232 may serve as a support inside the channel layer 231, improving the structural strength of the storage stack structure 220.

In addition, the method for fabricating the semiconductor structure may further include removing the substrate 280 at the bottom to expose the portion of the memory function layer 233 extending into the substrate 280, removing the portion of the memory function layer 233 extending into the substrate 280 where the barrier layer 2333, the memory layer 2332 and the tunneling layer 2331 extend into the substrate 280 to expose the channel layer 231, and forming the source layer SL such that the source layer SL covers the bottom of the memory stack structure 220 and is in electrical contact with the channel layer 231, as shown in fig. 14 to 16.

In summary, in the method for manufacturing a semiconductor structure according to the above embodiment of the disclosure, the gate layer 260 is manufactured by filling the sacrificial material 320 in the channel hole 300, and then removing the sacrificial material 320 and manufacturing the dielectric layer 240 in the channel hole 300. Because the dielectric layer 240 is not manufactured before the gate layer 260 is manufactured, no additional sacrificial layer oxide is required to be added to protect the dielectric layer in the process of manufacturing the gate layer 260, meanwhile, the problem that the residual sacrificial layer oxide reduces the filling rate of the gate layer 260 can be avoided, the filling rate of the gate layer between adjacent gate insulating layers is improved, the conductivity of the gate layer is further improved, and the conductivity of the semiconductor structure in the three-dimensional memory is improved.

As shown in fig. 8 and 7C, in some embodiments, step 17 is also included prior to step 12.

Step 17, removing part of the gate sacrificial layer 222 by using the channel hole 300 to form a groove 310.

That is, a portion of the gate sacrificial layer 222 adjacent to the channel hole 300 is removed inside the channel hole 300, thereby forming a groove 310 at a position of the removed portion of the gate sacrificial layer 222, as shown in connection with fig. 7C. The bottom of the groove 310 is the remaining gate sacrificial layer 222, and two walls of the groove 310 are two adjacent gate insulating layers 221.

In some examples, a portion of gate sacrificial layer 222 may be removed by wet etching.

Step S12 includes filling the trench hole 300 and the recess 310 with a sacrificial material 320.

As shown in connection with fig. 7D, a sacrificial material 320 is filled in the channel hole 300 and the groove 310 to maintain the morphology and the inner space of the channel hole 300 and the groove 310, which have been currently fabricated, and to prevent the morphology and the inner space of the channel hole 300 and the groove 310 from being changed when other structures are removed and/or formed later.

Step S14 includes removing the sacrificial material 320, exposing the channel holes 300 and the recesses 310.

As shown in fig. 7H, after the sacrificial material 320 is removed, the channel holes 300 and the grooves 310, which were originally filled with the sacrificial material 320, are exposed. The removal manner of the sacrificial material 320 is described in detail above, and will not be described here.

Step S15 includes forming a dielectric layer 240 filling at least the recess 310 within the channel hole 300.

Dielectric layer 240 fills at least recess 310, e.g., dielectric layer 240 is located only within recess 310 as shown in fig. 7J, and e.g., dielectric layer 240 is located both within recess 310 and on the inner walls of channel hole 300 as shown in fig. 7I, and is not limited herein.

In some related art, as shown in fig. 11, the dielectric layer 02 is located between the gate layer 07 and the gate insulating layer 05, taking up more space between two adjacent gate insulating layers 05, resulting in a low filling rate of the gate layer 07. Compared with fig. 11, the semiconductor structure manufactured by the embodiment of the disclosure does not occupy the space between the gate insulating layers 221 and the gate layers 260, so that the filling rate of the gate layers 260 between two adjacent gate insulating layers 221 is improved, the conductivity of the gate layers 260 in the semiconductor structure provided by the embodiment of the disclosure can be improved, and the performance of the semiconductor structure in the three-dimensional memory is further improved.

In addition, by removing a portion of the gate sacrificial layer 222 to form the recess 310, and then forming the dielectric layer 240 in the recess 310, the size of the portion of the dielectric layer 240 located in the recess in the first direction X can be increased, thereby improving the performance of the dielectric layer 240 in preventing electrons in the channel structure 230 from leaking out of the channel structure 230, and improving the reliability of the semiconductor structure 200.

As shown in fig. 9, 7I, and 7J, in some embodiments, step S15 includes step S151 and step S152.

Step S151, forming a dielectric film 600 covering the groove 310 and the inner wall of the channel hole 300.

Dielectric film 600 may be formed using one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

As shown in fig. 7I, the dielectric film 600 includes a first portion 610 facing the recess 310, and a second portion 620 other than the first portion 610. Wherein the surface of the first portion 610 on the side away from the gate layer 260 may form a continuous surface with the surface of the second portion 620 on the side away from the gate layer 260, i.e. the first portion 610 comprises a first sub-portion 611 located in the recess 310, and a second sub-portion 612 located on the side of the first sub-portion 611 away from the gate layer 260, the dimension of the second sub-portion 612 in the first direction X being equal to the dimension of the second portion 620 in the first direction X.

Step S152 of removing a portion of the dielectric film 600 covering the inner wall of the channel hole 300 and leaving a portion 241 of the dielectric film 600 located in the recess 310 to form a dielectric portion 241 of the dielectric layer 240 in the recess 310.

As shown in fig. 7J, the portion of the dielectric film 600 covering the inner wall of the channel hole 300, that is, the second portion 620 and the second sub-portion 612 are described above. The second portion 620 and the second sub-portion 612 may be removed using a wet etching process, thereby leaving the first sub-portion 611 within the recess, forming the dielectric portion 241.

Specifically, the first sub-portion 611 may be formed by a curing process or the like, which is not limited herein.

In the related art, as shown in fig. 10, the dielectric layer 02 captures electrons (trap electrons), and in fig. 10, the area of the dielectric layer 02 capturing electrons is larger, and after a plurality of program/erase (P/E) cycles, electrons reversely tunnel into the dielectric layer 02, which results in a decrease in the speed of P/E. Meanwhile, the electric field generated during the P/E process may cause movement of carriers in the dielectric layer 02 (Lateral Migration), and due to the longer extension length of the dielectric layer 02, as shown in fig. 10, carriers may migrate across the memory cell, causing a problem of abnormal data maintenance (Data Retention Worse).

In this embodiment, a plurality of dielectric portions 241 spaced apart from each other are formed by removing portions of the dielectric film 600 covering the inner walls of the channel holes 300 so that the dielectric portions 241 remaining in one recess 310 are separated from the dielectric portions 241 remaining in the other recess 310. Since the plurality of dielectric portions 241 are provided independently of each other, an area of the dielectric portions 241 capturing electrons is reduced as compared to the dielectric layer 02 in fig. 10. Therefore, after a plurality of program/erase (P/E) cycles, electrons reverse tunneling into the dielectric portion 241 are less, the effect on the speed of P/E is less, and the durability of the semiconductor structure is improved.

In addition, since the plurality of dielectric portions 241 are provided independently of each other, movement of carriers within the dielectric portions 241 is restricted, carriers of one memory cell do not migrate to other memory cells, data anomalies are prevented, and reliability of the semiconductor structure 200 is improved.

It should be noted that, compared to fig. 11, the filling rate of the gate layer 260 between two adjacent gate insulating layers 221 is also improved in this embodiment, so that the conductivity of the gate layer 260 in the semiconductor structure provided in this embodiment of the disclosure can be improved, and further, the performance of the semiconductor structure in the three-dimensional memory can be improved.

In addition, at least one of the dielectric layer 240, the dielectric film 600, and the dielectric portion 241 includes a material having a dielectric constant greater than 3.9, i.e., a high dielectric constant material. The high dielectric constant material is described in detail above and will not be described here.

As shown in FIG. 12A, in some embodiments, step S13 includes steps S131-S133.

Step S131, forming a gate spacer 330 penetrating the dielectric stack 800.

As shown in fig. 7E, the extending direction of the gate isolation trench 330 is the first direction X. The gate spacer 330 divides one gate sacrificial layer 222 into a plurality of gate sacrificial lines arranged along the second direction Y. By forming the gate spacer 330, the exposed area of the gate sacrificial layer 222 is increased, which is advantageous for removing the gate sacrificial layer 222.

The gate spacer 330 may be formed by a dry etching process or a combination of a dry etching process and a wet etching process. The gate spacer 330 may extend through the dielectric stack 800.

In step S132, the gate sacrificial layer 222 is removed by using the gate spacer 330 to form a gate gap 340.

The gate spacer 330 increases the exposed area of the gate sacrificial layer 222, so that the remaining gate sacrificial layer 222 is removed through the gate spacer 330, and the removal speed of the gate sacrificial layer 222 can be increased.

Illustratively, the gate sacrificial layer 222 may be removed by a wet etching process.

After the gate sacrificial layer 222 is completely removed, only a part of the sacrificial material 320 is located between two adjacent gate insulating layers 221, and the plurality of gate insulating layers 221 are supported by the part of the sacrificial material 320 so as to be spaced apart from each other, thereby forming a gate gap, as shown in fig. 7F.

In step S133, a gate layer 260 is formed in the gate gap 340.

As shown in fig. 7G, the gate layer 260 may include a gate conductive layer 261 and a protective layer 262 disposed around the gate conductive layer 261.

In some examples, as shown in FIG. 12B, step S133 may include step S1331 and step S1332.

In step S1331, the protective layer 262 is formed in the gate gap 340.

In step S1332, a gate conductive layer 261 is formed within the protective layer 262.

As shown in connection with fig. 7F and 7G, the protective layer 262 may be formed by depositing a protective material on the inner surfaces of the gate gap 340. The gate conductive layer 261 may be formed by depositing a conductive material on an inner surface of the protective layer 262. Specifically, the inner surface of the gate gap 340 is formed including the surface of the gate insulating layer 221 and the surface of the sacrificial material 320.

The protective material may be a conductive material including, but not limited to, at least one of a metal (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), a metal compound (e.g., titanium nitride (TiNx), tantalum nitride (TaNx), chromium nitride (CrNx), tungsten nitride (WNx), etc.), and a metal alloy (e.g., tiSixNy, taSixNy, crSixNy, WSixNy, etc.). In actual cases, the specific material of the protective layer 262 may be determined based on the material of the gate conductive layer 261 to be subsequently manufactured.

The deposition processes described above include, but are not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof.

The conductive material of the gate conductive layer 261 includes, but is not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. In some examples, the material of the gate conductive layer 261 is tungsten.

As shown in fig. 7G, the protective layer 262 is located between the gate conductive layer 261 and the sacrificial material 320. In addition, the protective layer 262 is also located between the gate conductive layer 261 and the gate insulating layer 221.

Since the adhesion of the protective layer 262 is higher than that of the gate conductive layer 261, the protective layer 262 is disposed around the gate conductive layer 261, not only protecting the gate conductive layer 261, but also enhancing the connection strength between the gate layer 260 and other structures (the gate insulating layer 221 and/or the dielectric layer 240) and improving the structural strength of the semiconductor structure 200.

As shown in FIG. 13, in some embodiments, step S16 includes steps S161-S165.

And step S161, forming a barrier layer which covers the inner wall of the channel hole and the dielectric layer.

Step S162, forming a storage layer covering the barrier layer.

Step S163 is to form a tunneling layer covering the memory layer.

Step S164, forming a channel layer covering the tunneling layer.

And step S165, filling insulating materials in the channel layer.

A blocking layer 2333, a memory layer 2332, a tunneling layer 2331, and a channel layer 231 are sequentially formed along the inner wall of the channel hole. In some examples, a dielectric layer, such as a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, is deposited sequentially along the inner walls of the channel holes using one or more thin film deposition processes including, but not limited to, physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), ALD, or any combination thereof, to form the barrier layer 2333, the electrical storage layer 2332, and the tunneling layer 2331.

In some examples, any of the barrier layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231 may be deposited using a conformal coating process (such as ALD) such that any of the barrier layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231 may be formed to have a uniform thickness (the barrier layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231). In some examples, the thickness of the channel layer 231 may be controlled to be between about 10nm and about 15nm, e.g., 9.8nm, 10nm, 11nm, 12.2nm, 13.5nm, 14nm, 14.6nm, 15nm, or 15.3nm, by controlling the deposition rate and/or time.

After the barrier layer 2333, the storage layer 2332, and the tunneling layer 2331 are completed, a layer of semiconductor material (such as polysilicon) may be deposited on the inner walls of the silicon oxide (tunneling layer 2331) using one or more thin film deposition processes including, but not limited to PVD, CVD, ALD or any combination thereof, thereby forming the channel layer 231.

The material of the blocking layer 2333 may include silicon oxide, silicon nitride, a high dielectric constant material, or a combination thereof. In some examples, the barrier layer 2333 may be a single layer dielectric, such as a silicon oxide layer. In other examples, the barrier layer 2333 may be a composite dielectric layer, such as a silicon nitride layer and an aluminum oxide layer. The material of the memory layer 2332 may include silicon nitride or silicon oxynitride. The material of tunneling layer 2331 may include silicon oxide, silicon oxynitride, or a combination thereof. In some examples, tunneling layer 2331 may be a single layer dielectric, such as a silicon oxide layer. In other examples, tunneling layer 2331 may be a composite dielectric layer, such as a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon oxide layer.

After the channel layer 231 is completed, an insulating material 232 may be filled inside the channel layer 231. The height of the insulating material 232 in the third direction Z may be equal to the height of the channel layer 231 in the third direction Z. May function as a support in the channel layer 231, enhancing the structural strength of the memory stack structure 220.

In some embodiments, the filled insulating material 232 may also include an air gap inside. The number of air gaps may be one or a plurality of. In the case where the air gap is one, the shape of the air gap may be an elongated shape. In the case where there are a plurality of air gaps, the shape of the air gaps may be spherical, and the plurality of spherical air gaps may be uniformly distributed in the insulating material 232.

By providing an air gap within the insulating material 232, structural stresses generated during fabrication or use of the semiconductor structure 200 can be buffered, improving the reliability of the semiconductor structure 200.

Embodiments of the present disclosure provide a semiconductor structure. As shown in connection with fig. 14, semiconductor structure 200 includes a substrate 210, a storage stack structure 220, a channel structure 230, and a dielectric layer 240. The memory stack structure 220 is located at one side of the substrate 210, and the memory stack structure 220 includes gate insulating layers 221 and gate layers 260 alternately stacked. The channel structure 230 extends through the memory stack structure 220. Dielectric layer 240 is located between gate layer 260 and channel structure 230. The outline of the front projection of dielectric layer 240 onto substrate 210 meets the outline of the front projection of gate layer 260 onto substrate 210.

The substrate 210 includes a source layer SL, and a channel structure 230 penetrates the storage stack structure 220. In addition, the base 210 may or may not include a substrate. The embodiments of the present disclosure are not limited in this regard.

The storage stack 220 may include a core region CA and a step region SS having a step profile at the step region SS. The memory stack structure 220 includes a plurality of gate insulating layers 221 and gate layers 260 alternately stacked. That is, two adjacent gate layers 260 are located at both sides of one gate insulating layer 221 in the third direction Z, and two adjacent gate insulating layers 221 are located at both sides of one gate layer 260 in the third direction Z.

In some examples, gate layer 260 includes a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, doped silicon, and/or silicide. The gate insulating layer 221 includes an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The gate layer 260 and the gate insulating layer 221 extend in the first direction X. In the third direction Z, the gate layer 260 positioned at the lowermost of the plurality of gate layers 260 is configured as a source select gate SGS, the gate layer 260 positioned at the uppermost of the plurality of gate layers 260 is configured as a drain select gate SGD, and the gate layer 260 positioned at the intermediate of the plurality of gate layers 260 is configured as a plurality of word lines WL.

The channel structure 230 penetrates the storage stack structure 220 in a stacking direction (i.e., a third direction Z) of the plurality of gate layers 260 and the plurality of gate insulating layers 221. In some examples, the channel structure 230 may extend into the source layer SL, with the portion of the channel structure 230 extending into the source layer SL being surrounded by the source layer SL. The portion of the channel structure 230 outside the source layer SL is surrounded by the plurality of gate layers 260 and the plurality of gate insulating layers 221 in the storage stack structure 220. In which a portion of the channel structure 230 surrounded by the plurality of gate layers 260 and the plurality of gate insulating layers 221 in the memory stack structure 220 forms a memory cell string 400.

Dielectric layer 240 is located between channel structure 230 and memory stack structure 220. One side surface of the dielectric layer 240 in the first direction X is in contact with the channel structure 230. The other side surface of the dielectric layer 240 in the first direction X is in contact with at least the gate layer 260, for example, the dielectric layer 240 is in contact with only the gate layer 260, and for example, the dielectric layer 240 is in contact with both the gate layer 260 and the gate insulating layer 221.

Wherein the outline of the front projection of the dielectric layer 240 on the substrate 210 meets the outline of the front projection of the gate layer 260 on the substrate 210. It is understood that the dielectric layer 240 is not located at one side of the gate layer 260 in the third direction Z, i.e., the dielectric layer 240 is not located between the gate layer 260 and the gate insulating layer 221.

Dielectric layer 240 may comprise a plurality of dielectric materials, wherein at least one of the dielectric materials is different from the material of channel structure 230. In other words, the dielectric layer 240 may include a material that is not present in the channel structure 230.

Illustratively, the dielectric layer 240 includes a high dielectric constant material. Materials for dielectric layer 240 include, but are not limited to, aluminum oxide (Al ₂O₃), hafnium oxide (HfO ₂), tantalum pentoxide (Ta ₂O₅), titanium dioxide (TiO ₂), silicon oxynitride (SiO _xN_y), or any combination thereof.

Dielectric layer 240 may be formed by one or more thin film deposition processes including, but not limited to, chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), thermal oxidation, electroplating, electroless plating, or any combination thereof. In some embodiments, ALD may be used. The dielectric layer 240 formed by the ALD process has the advantage of high uniformity and high accuracy.

The dielectric layer 240 is located between the gate layer 260 and the channel structure 230, and can prevent electron leakage in the channel structure 230, improving reliability of the semiconductor structure 200.

Compared with the related art shown in fig. 5A, the semiconductor structure provided in the embodiment of the disclosure can improve the filling rate of the gate layer 260 in the semiconductor structure, improve the conductivity of the gate layer 260, and further improve the performance of the semiconductor structure 200 in the three-dimensional memory.

As shown in fig. 15, in some embodiments, the front projection of dielectric layer 240 onto substrate 210 at least partially overlaps with the front projection of gate insulation layer 221 onto substrate 210.

In this embodiment, the extension length of the gate insulating layer 221 in the first direction X is greater than the extension length of the gate layer 260 in the first direction X. For example, the gate insulating layer 221 protrudes at an end portion near the channel structure 230, compared to the gate layer 260, so that a recess having the gate layer 260 as a bottom wall and the gate insulating layer 221 as a side wall is formed at a side of the storage stack structure 220 near the channel structure 230.

Wherein the outline of the front projection of the dielectric layer 240 on the substrate 210 at least partially overlaps with the front projection of the gate insulating layer 221 on the substrate 210. It is understood that the dielectric layer 240 is at least partially located on one side of the gate insulating layer 221 in the third direction Z. For example, dielectric layer 240 is at least partially within the recess.

In addition, as shown in fig. 15, at least part of the dielectric layer 240 is filled in the groove, so that the size of the portion of the dielectric layer 240 corresponding to the groove in the first direction X is greater than the size of the portion of the dielectric layer 240 corresponding to the gate insulating layer 221 in the first direction X.

The portion of the dielectric layer 240 corresponding to the recess is located between the channel structure 230 and the gate layer 260, so that the performance of the dielectric layer 240 for preventing electron leakage of the channel structure 230 can be improved, and the reliability of the semiconductor structure 200 can be improved.

As shown in fig. 16, in some embodiments, the dielectric layer 240 includes a plurality of independently disposed dielectric portions 241, and the dielectric portions 241 are embedded between two adjacent gate insulating layers 221.

That is, in the present embodiment, the dielectric layer 240 includes only the dielectric portion 241 located in the recess. The dielectric portions 241 are separated from each other and independently provided.

The dielectric portion 241 is located between adjacent two gate insulating layers 221. The dimension of one dielectric portion 241 in the third direction Z is equal to the spacing distance of the adjacent two gate insulating layers 221 in the third direction Z.

Since the plurality of dielectric portions 241 are provided independently of each other, an area of the dielectric portions 241 capturing electrons is reduced as compared to the dielectric layer 02 in fig. 10. Therefore, after a plurality of program/erase (P/E) cycles, electrons reverse tunneling into the dielectric portion 241 are less, the effect on the speed of P/E is less, and the durability of the semiconductor structure is improved.

In addition, compared with fig. 11, the semiconductor structure manufactured by the embodiment of the disclosure does not occupy the space between the gate insulating layers 221 and the gate layers 260, so that the filling rate of the gate layers 260 between two adjacent gate insulating layers 221 is improved, the conductivity of the gate layers 260 in the semiconductor structure formed by the embodiment of the disclosure can be improved, and the performance of the semiconductor structure in the three-dimensional memory is further improved.

In some embodiments, the gate layer 260 includes a gate conductive layer 261, and a protective layer 262 disposed around the gate conductive layer 261. The protective layer 262 is in contact with the dielectric layer 240 and the gate insulating layer 221, respectively.

The protective layer 262 may be a conductive material including, but not limited to, at least one of a metal (e.g., titanium (Ti), tantalum (Ta), chromium (Cr), tungsten (W), etc.), a metal compound (e.g., titanium nitride (TiN _x), tantalum nitride (TaN _x), chromium nitride (CrN _x), tungsten nitride (WN _x), etc.), and a metal alloy (e.g., tiSi _xN_y、TaSi_xN_y、CrSi_xN_y、WSi_xN_y, etc.). In actual cases, the specific material of the protective layer 262 may be determined based on the material of the gate conductive layer 261.

Since the adhesion of the protective layer 262 is higher than that of the gate conductive layer, the protective layer 262 is disposed around the gate conductive layer, not only protecting the gate conductive layer 261, but also enhancing the connection strength between the gate layer 260 and the gate insulating layer 221 and the dielectric layer 240, and improving the structural strength of the semiconductor structure 200.

In some embodiments, dielectric layer 240 comprises a material having a dielectric constant greater than 3.9. For example, the dielectric layer 240 may have a material with a dielectric constant of 4.0, 4.6, 5.2, 5.5, 6.0, 6.3, 6.7, 7.2, 8.5, 9.1, 9.8, 10.4, etc.

The higher the dielectric constant of the material of the dielectric layer 240, the higher the performance of the dielectric layer 240 to prevent electron leakage in the channel structure 230, and the higher the reliability of the semiconductor structure 200.

In some embodiments, as shown in fig. 14-16, the channel structure 230 includes a channel layer 231, an insulating material 232, and a memory function layer 233. The insulating material 232 is located inside the channel layer 231, and the memory function layer 233 is located outside the channel layer 231. The memory function layer 233 includes a tunneling layer 2331, a memory layer 2332, and a blocking layer 2333 which are sequentially away from the channel layer 231.

The channel layer 231 may include a semiconductor material, and may be amorphous silicon, polycrystalline silicon, or single crystal silicon, for example. The memory function layer 233 is located outside the channel layer 231 and disposed around the channel layer 231. The memory function layer 233 includes a tunneling layer 2331, a memory layer 2332, and a blocking layer 2333. Carriers (electrons or holes) in the channel layer 231 can be tunneled into the storage layer 2332 through the tunneling layer 2331, and the storage layer 2332 is used to store carriers.

The material of the tunneling layer 2331 may include silicon oxide, silicon oxynitride, or any combination thereof. In some examples, tunneling layer 2331 may be a single layer dielectric, such as a silicon oxide layer. In other examples, tunneling layer 2331 may be a composite dielectric layer, such as a first silicon oxide layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a second silicon oxide layer.

The material of the memory layer 2332 may include silicon nitride or silicon oxynitride. The material of the barrier layer 2333 may include silicon oxide, silicon nitride, a high dielectric constant material, or a combination thereof.

The material of the barrier layer 2333 may include silicon oxide, silicon oxynitride, or any combination thereof. In some examples, the barrier layer 2333 may be a single layer dielectric, such as a silicon oxide layer. In other examples, the barrier layer 2333 may be a composite dielectric layer, such as a silicon nitride layer and an aluminum oxide layer.

In some examples, the blocking layer 2333, the storage layer 2332, the tunneling layer 2331, and the channel layer 231 may collectively constitute an ONOP (oxide-nitride-oxide-polysilicon) structure.

The insulating material 232 may include silicon oxide, silicon nitride, silicon oxynitride, etc., which is not limited herein. The insulating material 232 fills the inside of the channel layer 231 and can function as a support. In some examples, an air gap may also be formed within the insulating material 232, which may buffer structural stresses generated by the semiconductor structure during fabrication or use, improving the reliability of the semiconductor structure.

FIG. 17 is a block diagram of a storage system according to some embodiments. FIG. 18 is a block diagram of a storage system according to further embodiments.

Referring to fig. 17 and 18, some embodiments of the present disclosure also provide a storage system 1000. The memory system 1000 includes a controller 20, and the three-dimensional memory 10 of some embodiments as described above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., universal flash storage (Universal Flash Storage, UFS) package or Embedded multimedia card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, notebook computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual Reality (VR) devices, augmented Reality (Augmented Reality, AR) devices, or any other suitable electronic device having a memory therein.

In some embodiments, referring to FIG. 17, the memory system 1000 includes a controller 20 and a three-dimensional memory 10, and the memory system 1000 may be integrated into a memory card.

The memory Card includes any one of a PC Card (PCMCIA, personal computer memory Card international association), a Compact Flash (CF) Card, a smart media (SMART MEDIA SM) Card, a memory stick, a Multimedia Card (MMC), a secure digital (Secure Digital Memory Card SD) Card, and UFS.

In other embodiments, referring to fig. 18, a storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a Solid state disk (Solid STATE DRIVES, SSD for short).

In the storage system 1000, in some embodiments, the controller 20 is configured for operation in a low duty cycle environment, such as an SD card, CF card, universal serial bus (Universal Serial Bus, abbreviated USB) flash drive, or other medium for use in electronic devices such as personal computers, digital cameras, mobile phones, and the like.

In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC for data storage and enterprise storage arrays of mobile devices such as smartphones, tablets, notebooks, and the like.

In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions with respect to data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling. In some embodiments, the controller, 20 is further configured to process error correction codes with respect to data read from the three-dimensional memory 10 or written to the three-dimensional memory 10.

Of course, the controller 20 may also perform any other suitable function, such as formatting the three-dimensional memory 10, for example, the controller 20 may communicate with an external device (e.g., a host) via at least one of a variety of interface protocols.

It should be noted that the interface protocol includes at least one of USB protocol, MMC protocol, peripheral Component Interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced Technology Attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small Computer Small Interface (SCSI) protocol, enhanced Small Disk Interface (ESDI) protocol, integrated Drive Electronics (IDE) protocol, and Firewire protocol.

Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any of a cell phone, a desktop computer, a tablet computer, a notebook computer, a server, a vehicle-mounted device, a wearable device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

The electronic device may include the storage system 1000 described above, and may further include at least one of a central processing unit CPU (Central Processing Unit ), a cache (cache), and the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming a dielectric stack structure on one side of a substrate, the dielectric stack structure including gate insulating layers and gate sacrificial layers alternately stacked;

forming a channel hole penetrating the dielectric stack structure;

filling sacrificial materials in the channel holes;

Removing the gate sacrificial layer and forming a gate layer to obtain a storage stack structure including alternately stacked gate insulating layers and gate layers;

removing the sacrificial material after forming the gate layer, exposing the channel hole;

forming a dielectric layer in the channel hole, and

And forming a channel structure in the channel hole.

2. The method of manufacturing according to claim 1, wherein before filling the trench hole with a sacrificial material, further comprising:

removing part of the grid sacrificial layer by utilizing the channel hole to form a groove;

the filling of the sacrificial material in the channel hole comprises the following steps:

filling sacrificial materials in the channel holes and the grooves;

the removing the sacrificial material, exposing the channel hole, comprises:

removing the sacrificial material to expose the channel hole and the groove;

The forming a dielectric layer within the channel hole includes:

And forming a dielectric layer at least filling the groove in the channel hole.

3. The method of manufacturing according to claim 2, wherein forming a dielectric layer filling at least the recess in the channel hole comprises:

Forming a dielectric film covering the groove and the inner wall of the channel hole;

And removing the part of the dielectric film covering the inner wall of the channel hole, and reserving the part of the dielectric film positioned in the groove so as to form a dielectric part of the dielectric layer in the groove.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the removing the gate sacrificial layer and forming a gate layer includes:

forming a gate spacer through the dielectric stack;

Removing the gate sacrificial layer by using the gate isolation groove to form a gate gap;

a gate layer is formed within the gate gap.

5. The method of manufacturing according to claim 4, wherein forming a gate layer in the gate gap comprises:

Forming a protective layer in the gate gap;

Forming a gate conductive layer within the protective layer;

Wherein the protective layer is located between the sacrificial material and the gate conductive layer.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein forming a channel structure in the channel hole includes:

Forming a barrier layer covering the trench interior walls and the dielectric layer;

forming a storage layer covering the barrier layer;

forming a tunneling layer covering the storage layer;

Forming a channel layer covering the tunneling layer, and

And filling an insulating material in the channel layer.

7. The method according to any one of claims 1 to 3, wherein the material of the gate sacrificial layer comprises silicon nitride, and an etching ratio between the sacrificial material and the silicon nitride is greater than 30.

8. The method according to any one of claims 1 to 3, wherein at least one of the dielectric layer, the dielectric film, and the dielectric portion includes a material having a dielectric constant of more than 3.9.

9. A semiconductor structure, comprising:

A substrate;

A storage stack structure located at one side of the substrate, the storage stack structure including gate insulating layers and gate layers alternately stacked;

a channel structure penetrating the memory stack structure, and

The semiconductor device comprises a substrate, a gate insulating layer, a dielectric layer and a dielectric layer, wherein one part of the dielectric layer is positioned between the gate insulating layer and the channel structure, the other part of the dielectric layer is positioned between the gate insulating layer and the channel structure, the front projection outline of the dielectric layer on the substrate is connected with the front projection outline of the gate layer on the substrate, the dielectric layer is not overlapped with the gate layer in the overlapping direction of the gate layer and the gate insulating layer, and the dielectric layer is overlapped with one part of the gate insulating layer.

10. The semiconductor structure of claim 9, wherein the gate layer comprises a gate conductive layer, and a protective layer disposed around the gate conductive layer;

the protective layer is in contact with the dielectric layer and the gate insulating layer, respectively.

11. The semiconductor structure of claim 9 or 10, wherein the dielectric layer comprises a material having a dielectric constant greater than 3.9.

12. The semiconductor structure of claim 9 or 10, wherein the channel structure comprises:

A channel layer;

An insulating material located inside the channel layer, and

A memory function layer located outside the channel layer, the memory function layer including a tunneling layer, a memory layer, and a blocking layer remote from the channel layer;

Wherein the barrier layer is in contact with the dielectric layer.

13. A three-dimensional memory, comprising:

a semiconductor structure according to any one of claims 9 to 12;

and the peripheral device is electrically connected with the semiconductor structure.

14. A storage system, comprising:

A three-dimensional memory, the three-dimensional memory being as claimed in claim 13;

And a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

15. An electronic device, comprising:

the storage system of claim 14.