CN115206822B - Back-side wafer failure location fixture and method - Google Patents
Back-side wafer failure location fixture and methodInfo
- Publication number
- CN115206822B CN115206822B CN202210718894.2A CN202210718894A CN115206822B CN 115206822 B CN115206822 B CN 115206822B CN 202210718894 A CN202210718894 A CN 202210718894A CN 115206822 B CN115206822 B CN 115206822B
- Authority
- CN
- China
- Prior art keywords
- wafer
- failure
- failure positioning
- frame
- backside
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
- H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
- H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention discloses a back-side wafer failure positioning jig which comprises a wafer protection film, a first opening, a second opening and a positioning device, wherein the wafer protection film is used for being attached to the front side of a wafer, and the first opening is formed for exposing the surface of a failure chip of the wafer. The frame is attached to the surface of the wafer protection film at the periphery of the failure chip and comprises a plurality of input pins and output pins, and each IO pin is connected to the corresponding input pin through a lead. And the wafer fixing device is used for fixedly placing the wafer and downwards arranging the front surface of the wafer. A plurality of wires are provided below the wafer fixture to connect the output pins to an external test system. The invention also discloses a back-side wafer failure positioning method. The invention can realize the back grabbing point connection in time, simply and quickly, can improve the failure analysis and positioning efficiency, and can ensure the integrity and the cleanliness of the wafer.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a back-side wafer failure positioning jig. The invention also relates to a back-side wafer failure positioning method.
Background
As shown in FIG. 1, the conventional back side wafer failure positioning jig adopts a manual probe stage, and comprises:
A needle holder 101, a probe 102 provided at an end of the needle holder 101.
Probes 102 need to be directly tied to the wafer at the split 103, the split 103 has a failed chip, and the probes 102 finally need to be in contact with the IO pins on the failed chip.
Probes 102 are connected to an external test system 105 by wires 104.
The splits 103 are placed on the fixture 106. The fixture 106 has a transparent plate 107 thereon. The back of the split 103 is placed on the transparent plate 107.
A failure positioning device is arranged above the fixing device 106. The failure positioning device is an EMMI device or an OBIRCH device.
The failure positioning device includes a lens 108, the lens 108 injecting laser 109 into the wafer fragment 103 from the back side of the wafer 201. As can be seen from fig. 2, the laser light 109 passes through the transparent plate 107 into the wafer fragments 103. Also included in the fixture 106 is an optical emission microscopy plus positioning system 110 for implementing EMMI or OBIRCH functions.
The manual probe station is a common auxiliary equipment for matching EMMI/OBIRCH failure analysis and positioning, but the probe has a plurality of defects and short plates in the back grabbing process:
1. The needle stand 101 has long debugging time and needs to be modified.
2. It is generally preferred that the test channel not exceed three to four hubs, otherwise a striker is likely to occur.
3. The back needle insertion test often needs the split, just can fine location inefficacy chip, but cracked wafer can't shipment, and in time the wafer does not split, the surface can also cause the contamination in the analysis process, can't pass through OQA, and then can't shipment.
4. The bottom needle insertion needs to repeatedly confirm the contact property of the probe, the debugging difficulty is high, and the requirement on engineers is high.
Disclosure of Invention
The invention aims to solve the technical problem of providing the back type wafer failure positioning jig which can realize back gripping point connection in time, simply and quickly, improve failure analysis positioning efficiency and ensure the integrity and the cleanliness of wafers. Therefore, the invention also provides a back-side wafer failure positioning method.
In order to solve the above technical problems, the back-side wafer failure positioning jig provided by the invention comprises:
The wafer protection film is used for being attached to the front face of a wafer, a first opening exposing the surface of a failed chip of the wafer and covering the surface of the wafer outside the failed chip are formed in the wafer protection film, and the failed chip comprises a plurality of IO pins.
The wafer protection film comprises a frame, wherein the frame is attached to the surface of the wafer protection film at the periphery of the failure chip and comprises a plurality of input pins and a plurality of output pins, the output pins with the same number are connected with the input pins, and each IO pin is connected with the corresponding input pin through a lead.
And the wafer fixing device is used for fixedly placing the wafer and downwards arranging the front surface of the wafer.
A plurality of wires are arranged below the wafer fixing device, a first end of each wire is connected with the corresponding output pin, and a second end of each wire is connected to an external test system.
A further improvement is that the frame is of annular structure and surrounds the periphery of the first opening.
Further improvements are that the frame comprises a PCB board, a built-in wiring board or a lead substrate.
The wafer fixing device is further improved in that a clamping ring is arranged in the wafer fixing device, and the wafer is fixed through the clamping ring.
The further improvement is that a failure positioning device is arranged above the wafer fixing device.
A further improvement is that the failure location device is an EMMI device or an OBIRCH device.
In a further improvement, the failure positioning device comprises a lens, and the lens is used for making laser enter the wafer from the back surface of the wafer.
In order to solve the technical problems, the back-side wafer failure positioning method provided by the invention comprises the following steps:
the wafer protection film is adhered to the front surface of a wafer to form a first opening, the first opening exposes the surface of a failed chip of the wafer, the wafer protection film covers the surface of the wafer outside the failed chip, and the failed chip comprises a plurality of IO pins.
Attaching a frame to the surface of the wafer protection film at the periphery of the failure chip, wherein the frame comprises a plurality of input pins and a plurality of output pins, and the output pins with the same number are connected with the input pins.
And thirdly, connecting each IO pin to the corresponding input pin through a wire bonding.
And fourthly, fixing the front surface of the wafer on a wafer fixing device downwards.
And fifthly, arranging a plurality of wires below the wafer fixing device, wherein the first ends of the wires are connected with the corresponding output pins, and the second ends of the wires are connected with an external test system.
A further improvement is that the frame is of annular structure and surrounds the periphery of the first opening.
Further improvements are that the frame comprises a PCB board, a built-in wiring board or a lead substrate.
The wafer fixing device is further improved in that a clamping ring is arranged in the wafer fixing device, and the wafer is fixed through the clamping ring.
Further improvement is that the method further comprises the steps of:
and step six, arranging a failure positioning device above the wafer fixing device and performing failure positioning.
A further improvement is that the failure location device is an EMMI device or an OBIRCH device.
In a further improvement, the failure positioning device comprises a lens, and the lens is used for making laser enter the wafer from the back surface of the wafer.
Further improvement is that the method further comprises the steps of:
and seventhly, removing the wafer from the wafer fixing device, and sequentially removing the frame and the wafer protective film from the wafer.
The wafer is protected by the wafer protection film to form the first opening at the position of the failed chip, then the frame is arranged, the IO pin of the failed chip is connected to the input pin of the frame through the wire bonding, the whole wafer is fixed on the wafer fixing device, and then the output pin of the frame is connected to the external test system through the lead wire, so that the wafer is not required to be needled to the IO pin of the failed chip, various defects caused by needling, such as long needle seat debugging time, limited number of needle seats of observation through holes, high debugging difficulty of needle punching and the like, can be avoided, and the wafer has the advantages of no needle seat number limitation, high connection stability, no need of broken sheets, ensuring the clean surface of the wafer after analysis, meeting shipment standards and the like, can realize back surface grasp point connection in time, simply and quickly, can improve the failure analysis positioning efficiency, and can also ensure the completeness and the cleanliness of the wafer.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of a conventional backside wafer failure positioning fixture;
FIG. 2 is a schematic diagram of a back side wafer failure positioning jig according to an embodiment of the present invention;
FIG. 3A is a schematic diagram of a wafer top view in a step one of a backside wafer fail location method according to an embodiment of the present invention;
FIG. 3B is a schematic diagram of a cross-sectional view of a wafer after completion of step one of the method for locating a backside wafer failure according to an embodiment of the present invention;
FIG. 4A is a schematic diagram of a wafer cross-section after completion of step three of a backside wafer failure positioning method according to an embodiment of the present invention;
FIG. 4B is an enlarged view of the frame of FIG. 4A in position;
FIG. 4C is a cross-sectional block diagram of FIG. 4A;
FIG. 5 is a schematic diagram of a top view of a wafer after completion of step four of a backside wafer failure location method according to an embodiment of the present invention;
FIG. 6 is a cross-sectional view of a back side wafer failure positioning method according to an embodiment of the present invention after the completion of step four;
FIG. 7A is a cross-sectional view of a wafer removed from the wafer holder in step seven of a backside wafer failure location method according to an embodiment of the present invention;
fig. 7B is a cross-sectional view of the wafer after the completion of step seven of the back-side wafer failure positioning method according to the embodiment of the present invention.
Detailed Description
Fig. 2 is a schematic structural diagram of a back-side wafer failure positioning jig according to an embodiment of the present invention, where the back-side wafer failure positioning jig according to the embodiment of the present invention includes:
the wafer protection film 202 is used for being attached to the front surface of the wafer 201, the wafer protection film 202 is provided with a first opening 203 exposing the surface of a failed chip 201a of the wafer 201 and covers the surface of the wafer 201 outside the failed chip 201a, and the failed chip 201a comprises a plurality of IO pins.
And a frame 204 attached to the surface of the wafer protection film 202 on the periphery of the failed chip 201 a. Referring to fig. 4B, the frame 204 includes a plurality of input pins 204a and a plurality of output pins 204B, the output pins 204B and the input pins 204a with the same number are connected, and each of the IO pins is connected to the corresponding input pin 204a through a lead 205.
In the embodiment of the present invention, the frame 204 has a ring-shaped structure and surrounds the circumference of the first opening 203.
The frame 204 includes a PCB board, a built-in wiring board, or a lead substrate.
Wafer holder 207 for holding wafer 201 and holding the front surface of wafer 201 downward.
A plurality of wires 206 are disposed under the wafer fixture 207, a first end of each wire 206 is connected to a corresponding output pin 204b, and a second end of each wire 206 is connected to an external test system 209.
In the embodiment of the present invention, a clamping ring is disposed in the wafer fixing device 207, and the wafer 201 is fixed by the clamping ring. The snap ring structure is shown in fig. 5.
A failure positioning device is disposed above the wafer fixture 207. The failure positioning device is an EMMI device or an OBIRCH device.
The failure positioning device includes a lens 210, the lens 210 being configured to inject laser light 211 into the wafer 201 from a back side of the wafer 201. As can be seen from fig. 2, the wafer holder 207 also has a transparent plate 208, through which the laser light 211 passes into the wafer 201. Also included in wafer fixture 207 is an optical emission microscopy plus positioning system 211 for implementing EMMI or OBIRCH functions.
According to the embodiment of the invention, the wafer 201 is not required to be split, the wafer protection film 202 is used for protecting the wafer 201, then a first opening 203 is formed at the position of the failed chip 201a, then the frame 204 is arranged, the IO pins of the failed chip 201a are connected to the input pins 204a of the frame 204 through the wire 205, after the whole wafer 201 is fixed on the wafer fixing device 207, the output pins 204b of the frame 204 are connected to the external test system 209 through the wire 206, so that the invention does not need to be needled to the IO pins of the failed chip 201a, and various defects caused by needling, such as long needle seat debugging time, limited number of needle seats for observing through holes, high debugging difficulty for splitting and needling, can be avoided.
The back type wafer failure positioning method provided by the embodiment of the invention comprises the following steps:
step one, as shown in fig. 3A, as shown in the left side of fig. 3A, a wafer 201 is provided, and the wafer 201 has a failed chip 201a thereon. The failed chip 201a has a mark thereon.
As shown in the middle of fig. 3A, a wafer protection film 202 is provided.
As shown on the right side of fig. 3A and in combination with fig. 3B, a wafer protection film 202 is attached to the front side of the wafer 201 and forms a first opening 203, the first opening 203 exposes the surface of the failed chip 201a of the wafer 201, the wafer protection film 202 covers the surface of the wafer 201 outside the failed chip 201a, and the failed chip 201a includes a plurality of IO pins. The position of the first opening 203 is found by the mark, which needs to be cleaned after the first opening 203 is formed.
Step two, as shown in fig. 4A, a frame 204 is attached to the surface of the wafer protection film 202 at the periphery of the failed chip 201 a.
As shown in fig. 4B, the frame 204 includes a plurality of input pins 204a and a plurality of output pins 204B, and the output pins 204B and the input pins 204a of the same number are connected.
In the method of the embodiment of the present invention, the frame 204 has a ring-shaped structure and surrounds the periphery of the first opening 203.
The frame 204 includes a PCB board, a built-in wiring board, or a lead substrate.
Step three, as shown in fig. 4B and also in combination with fig. 4C, each of the IO pins is connected to the corresponding input pin 204a by a wire bonding 205.
Step four, as shown in fig. 5, the wafer 201 is fixed on the wafer fixing device 207 with the front side facing downwards.
In the method of the embodiment of the present invention, a clamping ring is disposed in the wafer fixing device 207, and the wafer 201 is fixed by the clamping ring.
Step five, as shown in fig. 6, a plurality of wires 206 are disposed under the wafer fixing device 207, and a first end of each wire 206 is connected to the corresponding output pin 204b, and a second end of each wire 206 is connected to an external test system 209.
The method also comprises the steps of:
step six, as shown in fig. 2, a failure positioning device is disposed above the wafer fixing device 207 and performs failure positioning.
In the method of the embodiment of the invention, the failure positioning device is an EMMI device or an OBIRCH device.
The failure positioning device includes a lens 210, the lens 210 being configured to inject laser light 211 into the wafer 201 from a back side of the wafer 201. As can be seen from fig. 2, the wafer holder 207 also has a transparent plate 208, through which the laser light 211 passes into the wafer 201. Also included in wafer fixture 207 is an optical emission microscopy plus positioning system 211 for implementing EMMI or OBIRCH functions.
The method also comprises the steps of:
Step seven, as shown in fig. 7A, the wafer 201 is removed from the wafer holder 207.
As shown in fig. 7B, the frame 204 and the wafer protective film 202 are sequentially removed from the wafer 201. Finally, the surface of the wafer 201 remains clean.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (15)
1. A back type wafer failure positioning jig is characterized by comprising:
The wafer protection film is used for being attached to the front surface of a wafer, and is provided with a first opening exposing the surface of a failed chip of the wafer and a second opening covering the surface of the wafer outside the failed chip;
The wafer protection film comprises a wafer protection film, a frame, a plurality of IO pins, a plurality of pins and a plurality of pins, wherein the wafer protection film is adhered to the surface of the periphery of the failure chip;
The wafer fixing device is used for fixedly placing the wafer and downwards arranging the front surface of the wafer;
a plurality of wires are arranged below the wafer fixing device, a first end of each wire is connected with the corresponding output pin, and a second end of each wire is connected to an external test system.
2. The backside wafer failure positioning jig of claim 1, wherein the frame is of a ring-shaped structure and surrounds a periphery of the first opening.
3. The backside wafer failure positioning jig of claim 2, wherein the frame comprises a PCB, a built-in circuit board or a lead substrate.
4. The backside wafer failure positioning jig of claim 1, wherein a clamping ring is provided in the wafer fixing device, and the wafer is fixed by the clamping ring.
5. The wafer backside failure positioning tool of claim 1, wherein the failure positioning device is disposed above the wafer fixture.
6. The backside wafer failure positioning tool of claim 5, wherein the failure positioning device is an EMMI device or an OBIRCH device.
7. The backside wafer failure positioning tool of claim 6, wherein the failure positioning device comprises a lens that directs laser light into the wafer from a backside of the wafer.
8. A back-side wafer failure positioning method is characterized by comprising the following steps:
The method comprises the steps of firstly, attaching a wafer protection film to the front surface of a wafer and forming a first opening, wherein the first opening exposes the surface of a failed chip of the wafer, and the wafer protection film covers the surface of the wafer outside the failed chip;
Attaching a frame to the surface of the wafer protective film at the periphery of the failure chip, wherein the frame comprises a plurality of input pins and a plurality of output pins, and the output pins with the same number are connected with the input pins;
step three, connecting each IO pin to the corresponding input pin through a wire bonding;
Fixing the front surface of the wafer on a wafer fixing device downwards;
And fifthly, arranging a plurality of wires below the wafer fixing device, wherein the first ends of the wires are connected with the corresponding output pins, and the second ends of the wires are connected with an external test system.
9. The method of claim 8, wherein the frame is annular and surrounds the periphery of the first opening.
10. The method of claim 9, wherein the frame comprises a PCB, a built-in circuit board, or a lead substrate.
11. The method of claim 10, wherein the wafer holder has a snap ring, and the wafer is held by the snap ring.
12. The method for locating a backside wafer failure of claim 8, further comprising the steps of:
and step six, arranging a failure positioning device above the wafer fixing device and performing failure positioning.
13. The method of claim 12, wherein the failure location device is an EMMI device or an OBIRCH device.
14. The method of claim 13, wherein the failure positioning device comprises a lens that directs laser light into the wafer from a back side of the wafer.
15. The method for locating a backside wafer failure of claim 12, further comprising the steps of:
and seventhly, removing the wafer from the wafer fixing device, and sequentially removing the frame and the wafer protective film from the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210718894.2A CN115206822B (en) | 2022-06-23 | 2022-06-23 | Back-side wafer failure location fixture and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210718894.2A CN115206822B (en) | 2022-06-23 | 2022-06-23 | Back-side wafer failure location fixture and method |
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| Publication Number | Publication Date |
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| CN115206822A CN115206822A (en) | 2022-10-18 |
| CN115206822B true CN115206822B (en) | 2026-04-03 |
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| CN202210718894.2A Active CN115206822B (en) | 2022-06-23 | 2022-06-23 | Back-side wafer failure location fixture and method |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110299299A (en) * | 2019-07-05 | 2019-10-01 | 北京智芯微电子科技有限公司 | High-density packages chip failure localization method based on manual wire binding machine |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002026091A (en) * | 2000-07-11 | 2002-01-25 | Nec Corp | Method for analyzing failure of semiconductor device |
| US6927079B1 (en) * | 2000-12-06 | 2005-08-09 | Lsi Logic Corporation | Method for probing a semiconductor wafer |
| JP5381118B2 (en) * | 2009-01-21 | 2014-01-08 | 東京エレクトロン株式会社 | Probe device |
| JP2010206188A (en) * | 2009-02-05 | 2010-09-16 | Renesas Electronics Corp | Rear surface treatment method, rear surface analysis method, and rear surface treatment apparatus |
| CN102637615B (en) * | 2012-03-31 | 2014-09-17 | 上海华力微电子有限公司 | Sample preparation method for wafer-level back failure positioning in failure analysis |
| KR101940721B1 (en) * | 2016-10-07 | 2019-04-10 | 한국전자통신연구원 | Multi-channel light module structure and method packaging the structure thereof |
| US9947598B1 (en) * | 2017-06-27 | 2018-04-17 | International Business Machines Corporation | Determining crackstop strength of integrated circuit assembly at the wafer level |
| CN111370347A (en) * | 2020-03-24 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Failure analysis method of power device |
| CN111474465B (en) * | 2020-04-27 | 2022-06-24 | 上海精密计量测试研究所 | Flat-pack semiconductor device fixture and analysis method for EMMI analysis |
| CN111913091B (en) * | 2020-07-31 | 2023-06-13 | 上海华力集成电路制造有限公司 | Sample fixing device |
| CN114076697A (en) * | 2020-08-14 | 2022-02-22 | 长鑫存储技术有限公司 | Preparation method of semiconductor failure analysis sample |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110299299A (en) * | 2019-07-05 | 2019-10-01 | 北京智芯微电子科技有限公司 | High-density packages chip failure localization method based on manual wire binding machine |
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