CN114334998A

CN114334998A - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN114334998A
Application number: CN202111647506.8A
Authority: CN
Inventors: 谢炜; 王迪; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-04-12

Abstract

The present application provides a three-dimensional memory and a manufacturing method thereof. The manufacturing method includes: forming a stacked structure including alternately stacked dielectric layers and sacrificial layers on a substrate, the stacked structure including a stepped structure located in a stepped area, and a sacrificial layer located in the stepped area. at least a portion of the structure is exposed; a first capping layer comprising nitrogen-doped silicon carbide is formed on the exposed at least a portion of the sacrificial layer; a second capping layer comprising silicon-rich silicon oxide is formed on the first capping layer; and the second capping layer is formed A filling layer is formed on the layer to provide a flat surface for the stepped area.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The present application relates to the field of semiconductor technology. In particular, the present application relates to a three-dimensional memory and a method of manufacturing the same.

Background

NAND devices of a planar structure have been approaching the limit of practical expansion, and in order to further increase the memory capacity and reduce the memory cost per bit, 3D NAND memory devices have been proposed. In a 3d nand memory device structure, a stack structure may be formed by alternately stacking dielectric layers and conductive layers vertically or substantially vertically, the stack structure including a core region and a step region, wherein the core region may be used to form an array of channel structures, and the step region may be used to form a step structure.

It is to be appreciated that this background section is intended in part to provide a useful background for understanding the technology, however, it is not necessary for these matters to be within the knowledge or understanding of those skilled in the art prior to the filing date of the present application.

Disclosure of Invention

One aspect of the present application provides a method for manufacturing a three-dimensional memory, including: forming a stacked structure comprising alternately stacked dielectric layers and sacrificial layers on a substrate, wherein the stacked structure comprises a step structure located in a step area, and at least one part of the sacrificial layer located in the step structure is exposed; forming a first capping layer comprising nitrogen-doped silicon carbide on the exposed at least a portion of the sacrificial layer; forming a second capping layer comprising silicon-rich silicon oxide on the first capping layer, and forming a filling layer on the second capping layer.

In one embodiment of the present application, wherein at least a portion of the second cap layer in contact with the first cap layer is converted to a bonding layer, the bonding layer comprises silicon oxide.

In one embodiment of the present application, wherein the silicon-rich silicon oxide comprises elemental silicon, at least a portion of the elemental silicon in the second capping layer is oxidized to the bonding layer.

In one embodiment of the present application, during the forming of the first overburden layer, an exposed surface of the first overburden layer forms a hydrocarbon dangling bond; and during the formation of the second capping layer, the hydrocarbon dangling bonds form water vapor with at least a portion of oxygen atoms in the second capping layer.

In one embodiment of the present application, the wet oxidation of at least a portion of the elemental silicon to the bonding layer comprises: the water vapor wet oxidizes the at least a portion of the elemental silicon to the bonding layer.

In one embodiment of the present application, the second capping layer is formed using an atomic layer deposition process or a high density plasma chemical vapor deposition process.

In one embodiment of the present application, forming the second capping layer includes an annealing process at a temperature ranging from 600 ℃ to 1400 ℃.

In one embodiment of the present application, the method further comprises: forming a gate line gap extending through the stacked structure and into the substrate; and replacing the sacrificial layer with a conductive layer via the gate line gap.

In one embodiment of the present application, the method further comprises: and forming word line contact parts which sequentially penetrate through the filling layer, the second covering layer and the first covering layer and extend into the corresponding conductive layers.

In one embodiment of the present application, the forming the word line contact includes: forming a contact hole penetrating through the filling layer and extending into the first covering layer above the step structure; and continuously processing the contact holes extending into the first covering layer to enable the contact holes to extend to the corresponding conductive layers.

In one embodiment of the present application, the forming the word line contact includes: and filling a conductive material in the contact hole to form the word line contact part.

Another aspect of the present application provides a three-dimensional memory including: a first semiconductor layer; the laminated structure is positioned on the first semiconductor layer and comprises dielectric layers and conducting layers which are alternately stacked, and the laminated structure comprises a step structure positioned in a step area; a first capping layer comprising nitrogen-doped silicon carbide, the first capping layer covering at least a portion of the conductive layer located at the step structure; a second capping layer comprising silicon-rich silicon oxide, the second capping layer being on the first capping layer; and a filling layer on the second cover layer.

In one embodiment of the present application, the three-dimensional memory further comprises: a bonding layer between the first capping layer and the second capping layer.

In one embodiment of the present application, the second capping layer includes silicon-rich silicon oxide having a ratio of silicon atoms to oxygen atoms of 1:1 to 2.

In one embodiment of the present application, the three-dimensional memory further comprises: and the word line contact part sequentially penetrates through the filling layer, the second covering layer and the first covering layer and extends into the corresponding conducting layer.

In one embodiment of the present application, the three-dimensional memory further comprises: the grid line gap structure comprises an insulating layer and a conductor layer which are sequentially arranged from outside to inside.

Drawings

Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings, there is shown in the drawings,

FIG. 1 is a flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure;

2-10 are partial schematic views of a method of fabricating a three-dimensional memory according to some embodiments of the present application after certain steps are performed;

FIG. 11 is a schematic diagram of a three-dimensional memory according to some embodiments of the present application;

FIG. 12 is a schematic diagram of a three-dimensional memory according to other embodiments of the present application.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way. Like reference numerals refer to like elements throughout the specification.

It is noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," "exemplary," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part from the context of their use. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" but also includes the meaning of "on" and having intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" but also can include the meaning of "above" or "over" and having no intermediate features or layers therebetween (i.e., directly on something).

Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire superstructure or understructure, or may have a smaller extent than the understructure or superstructure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of levels at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of sub-layers.

In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, as used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-wise terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.

It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application.

Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

In some exemplary processes of 3D NAND, as the number of stacked layers increases, the step structure (e.g., step structure 142 hereinafter) of 3D NAND has an increasing number of step steps (e.g., step 130 hereinafter), each of which is thinner and thinner, so that a subsequently formed word line contact hole (not shown) is difficult to stop at a corresponding conductive layer (e.g., conductive layer 204 hereinafter), and the corresponding conductive layer 204 is easily broken down to contact with an adjacent conductive layer 204, thereby causing word line leakage and signal crosstalk problems.

In some embodiments, a capping layer (e.g., hereinafter, a first capping layer 143 comprising nitrogen-doped silicon carbide) having a certain thickness may be formed on the step structure 142, the first capping layer 143 may cover the corresponding conductive layer 204, and the first capping layer 143 may serve as a buffer when forming a word line contact hole (not shown). Alternatively, the word line contact hole may stop in the first capping layer 143 and then continue to extend into the corresponding conductive layer 204, thereby increasing the process window for the word line contact hole to land on the conductive layer 204 and reducing the risk of the word line contact hole breaking through the corresponding conductive layer 204. Other embodiments of the present application provide a method for fabricating a three-dimensional memory, in which fig. 1 shows a flowchart of the method 300 for fabricating a three-dimensional memory, and fig. 2-10 are partial schematic diagrams after certain steps are performed according to the method 300 for fabricating a three-dimensional memory. In describing the embodiments of the present application in detail, the cross-sectional views illustrating the structure of the device are not partially enlarged in general scale for convenience of description, and the schematic views are only examples, which should not limit the scope of protection of the present application.

The above-described method 300 of manufacturing will be described below in conjunction with the associated figures, it being understood that the operations shown in the method are not exhaustive and that other operations may be performed before, after, or between any of the illustrated operations.

Referring to fig. 1, the manufacturing method 300 includes an operation S310 in which a stacked structure including alternately stacked dielectric layers and sacrificial layers may be formed on a substrate, the stacked structure including a stepped structure at a stepped region, at least a portion of the sacrificial layer at the stepped structure being exposed.

As shown in fig. 2, the material of the substrate 10 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, a group III-V compound semiconductor, or any combination thereof. In some examples, the substrate 10 may include a base 100, and a stop layer 101 and a first sacrificial layer 102 sequentially formed on the base 100. Illustratively, the substrate 100 may have a relatively thick thickness compared to the stop layer 101 and the first sacrificial layer 102, such that the substrate 100 may serve as a structural support for a device structure (e.g., the stacked structure 200) formed thereon.

In some embodiments, the method of forming the stop layer 101 and the first sacrificial layer 102 may include one or more of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), sputtering, thermal oxidation. Illustratively, the material of the substrate 100 may include silicon, the material of the stop layer 101 may include silicon dioxide, and the material of the first sacrificial layer 102 may include polysilicon.

In this operation, the stack structure 200 may be formed on the substrate 10. The stacked structure 200 may include a plurality of dielectric layers 201 and a plurality of sacrificial layers 202 alternately stacked in a direction perpendicular or substantially perpendicular to the substrate 10. Alternatively, a plurality of dielectric layers 201 and a plurality of sacrificial layers 202 may be alternately stacked on the substrate 10 by one or more deposition processes, such as CVD, PVD, ALD.

It is to be understood that the number of dielectric layers 201 and sacrificial layers 202 is not limited to the number and thickness shown in fig. 2, and that one skilled in the art may provide any number and thickness of dielectric layers 201 and sacrificial layers 202 as desired without departing from the concepts of the present application. In addition, the materials of the dielectric layer 201 and the sacrificial layer 202 may be selected from suitable materials known in the art. For example, dielectric layer 201 may be an oxide layer (e.g., silicon oxide) and sacrificial layer 202 may be a nitride layer (e.g., silicon nitride).

Illustratively, the substrate 10 may be used to provide mechanical support for the structures formed thereon, such as the channel structure 111 (fig. 2), gate line gap structures (not shown), and the like, and may be removed during subsequent processing.

Referring again to fig. 2, optionally, prior to forming the stack structure 200, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be employed to sequentially form an oxide layer (e.g., silicon oxide) 103 and a polysilicon layer 104 on the substrate 10, e.g., on the first sacrificial layer 102.

The stacked structure 200 may include a core region 120 and a stepped region 140, and in some examples, the stepped region 140 may be located on both sides of the core region 120, and in other examples, the stepped region 140 may be located in the middle of the core region 120. It should be noted that, in the drawings of the embodiments of the present application, only the step region 140 on one side of the stacked structure 200 and the portion of the core region 120 adjacent to the step region 140 on the side are illustrated.

Optionally, the core region 120 may include a channel structure 111. As an example, the channel structure 111 may extend vertically or substantially vertically through the dielectric layer 201 and the sacrificial layer 202, optionally the channel structure 111 may extend into the first sacrificial layer 102. In some embodiments, the channel structure 111 includes a barrier layer 112, a storage layer 114, a tunneling layer 116, and a channel layer 118 disposed in that order from the outside to the inside. Alternatively, the channel layer 118 may include polysilicon. The tunneling layer 116 may comprise silicon oxide, silicon oxynitride, or any combination thereof. The memory layer 114 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 112 may include silicon oxide, silicon oxynitride, a high dielectric constant dielectric, or any combination thereof.

In some examples, the base 100, the stop layer 101, and the first sacrificial layer 102 in the substrate 10 may be removed (e.g., sequentially removed) from a side of the substrate 10 facing away from the stack of layers 200 in a suitable step using a photolithography and etching process (e.g., a dry or wet etching process), a CMP process, or any combination thereof, such that a portion of the channel structure 111 extending into the substrate 10 is exposed. Optionally, the stop layer 101 may stop the process of removing the substrate 10 from this layer, thereby facilitating control of the process uniformity of removing the substrate 10. Similarly, the first sacrificial layer 102 may stop the process of removing the stop layer 101 from that layer, thereby facilitating control of process uniformity of removing the stop layer 101.

Illustratively, portions of the barrier layer 112, the storage layer 114, and the tunneling layer 116 extending into the substrate 10 may be removed, thereby exposing portions of the channel layer 118 extending into the substrate 10. In examples including polysilicon layer 104, polysilicon layer 104 may serve as a stop layer for processes that expose portions of channel layer 118 extending into substrate 10 as described above. In some cases, polysilicon layer 104 may be removed in subsequent processes. As an example, a first semiconductor layer 401 (fig. 11) in electrical contact with the channel layer may also be formed on the side where the channel layer 118 is exposed, the first semiconductor layer 401 including, for example, polysilicon.

With continued reference to fig. 2, the stepped region 140 may include a stepped structure 142, wherein the stepped structure 142 may include a plurality of stepped steps 130. In some examples, each step 130 includes a thickness of at least one dielectric layer 201/sacrificial layer 202 pair, sidewalls of the at least one sacrificial layer 202/dielectric layer 220 pair are exposed, and at least a portion of a surface of the sacrificial layer 202 included in each step 130 away from the substrate 10 is exposed. As an example, the step structure 142 shown in fig. 2 may be formed by performing a repeated etch-trim process on the stack structure 200 using a patterned mask layer (not shown). Alternatively, the patterned mask may include a photoresist or a carbon-based polymer material, and may be removed after the step structure 142 is formed.

In some examples, the step structure 142 may be a single step structure that sequentially increases along one direction in the plane of the substrate 10, in other examples, the step structure 142 may also be a stepped step (SDS) formed in two orthogonal directions in the plane of the substrate 10, the stepped step may have different sections, such as 3 sections, 4 sections, or more sections, for example, different sectional plates may be used, and each section may be followed by one etching of the stacked structure 200 by multiple trimming of photoresist in two orthogonal directions, so as to form a stepped step.

With continued reference to fig. 1, the fabrication method 300 includes an operation S320 in which a first capping layer comprising nitrogen-doped silicon carbide may be formed on the exposed at least a portion of the sacrificial layer. As shown in fig. 3, after forming the step structure 142, a first capping layer 143 may be formed on exposed portions of the sacrificial layer 202, for example, on exposed sidewalls of the sacrificial layer 202 and a portion of the surface remote from the substrate 10. Optionally, a first capping layer 143 may also be formed on the exposed surface of the core region 120. In one example, the first capping layer 143 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the first capping layer 143 comprises, for example, Nitrogen-doped Silicon Carbide SiCN (NDC). In some examples, the thickness of the first capping layer 143 may be several nanometers to several tens of nanometers. The NDC in the first capping layer 143 may be a denser film layer with good step coverage.

Since the first capping layer 143 may be formed between the step structure 142 and the subsequently deposited filling layer 145 (fig. 6), the first capping layer 143 may act as a barrier between the filling layer 145 and the stacked structure 200, preventing impurities (e.g., radicals of H and OH) in the filling layer 145 from diffusing into the step structure 142, thereby not eroding the sacrificial layer 202 in the step structure 142.

In some examples where first capping layer 143 comprises nitrogen-doped silicon carbide, the exposed surface of first capping layer 143 is typically susceptible to forming hydrocarbon dangling bonds.

With continued reference to fig. 1, the method 300 includes an operation S330 in which a second capping layer comprising silicon-rich silicon oxide may be formed on the first capping layer. As shown in fig. 4, the second capping layer 144, which is in contact with the exposed surface of the first capping layer 143, may be formed on the first capping layer 143 by a thin film deposition process such as CVD, PVD, ALD, high density plasma-chemical vapor deposition (HDP-CVD), ion enhanced chemical vapor deposition (PECVD), magnetron sputtering (RMS), laser pulse deposition (PLD), or any combination thereof. As an example, the second capping layer 144 may be formed using an ALD process at a high temperature annealing process of 600 to 1400 ℃.

In an example in which the filling layer 145 (fig. 6) including silicon dioxide is directly formed on the first capping layer 143, water vapor may be formed due to a hydrocarbon dangling bond that may combine with a more reactive oxygen radical (O) or hydroxyl radical (OH) in silicon dioxide. Water vapor may adhere to the interface where the first capping layer 143 contacts the filling layer 145, thereby causing a decrease in the bonding force between the first capping layer 143 and the filling layer 145, and easily causing the cleavage of the first capping layer 143 or even the peeling-off problem.

To improve the above problem, some embodiments of the present application may form a second capping layer 144 comprising silicon-rich silicon oxide on the first capping layer 143 before forming the filling layer 145. Although water vapor is generated in the formation process of the second cover layer 144, the water vapor can be consumed in time, and the bonding force between the first cover layer 143 and the second cover layer 144 is ensured.

In the example of forming the second capping layer 144 by the ALD process, the ratio of oxygen source (e.g., oxygen gas) and silicon source (e.g., silane) may be increased, and the annealing temperature is controlled to be suitable, so that the second capping layer 144 is formed to include silicon-rich silicon oxide having a ratio of silicon atoms to oxygen atoms greater than 1:2, for example, the ratio may be between 1:1 and 2. Optionally, the ratio of silicon atoms to oxygen atoms in the silicon-rich silicon oxide may be between 1:1.5 and 1: 1.8. Alternatively, the suitable annealing temperature is 600 ℃ to 1400 ℃. Alternatively, the suitable annealing temperature range may be 700 ℃ to 1200 ℃.

Since the ratio of silicon atoms to oxygen atoms in the silicon-rich silicon oxide is greater than 1:2, elemental silicon may be contained in the second capping layer 144, and during the high-temperature annealing treatment, at least a portion of the elemental silicon in the second capping layer 144, for example, at least a portion of the elemental silicon on the surface of the second capping layer 144 in contact with the first capping layer 143, may undergo a wet oxidation reaction with water vapor generated at the above-mentioned interface to form the bonding layer 146 including silicon dioxide as shown in fig. 5.

Referring again to fig. 1, the manufacturing method 300 includes an operation S340 in which a filling layer may be formed on the second capping layer. As shown in fig. 6, in some examples, a filling layer 145 covering the step structure 142 may be formed on the second capping layer 144, and a material of the filling layer 145 includes, for example, silicon oxide. Optionally, the filling layer 145 may fill above the stair step 130 (fig. 2) up to the top of the stacked structure 200. In the example where the filling layer 145 includes silicon oxide, since the difference in the materials of the second capping layer 144 and the filling layer 145 is small, the bonding force therebetween is relatively high.

Some embodiments of the present application can improve the problem of the splitting or even the peeling of the first capping layer 143 by forming the second capping layer 144 including silicon-rich silicon oxide between the first capping layer 143 and the filler layer 145, so that the bonding force between the first capping layer 144 and the second capping layer 144 and the bonding force between the second capping layer 144 and the filler layer 145 are improved as compared with the bonding force between the first capping layer 143 and the filler layer 145.

In one example, a first fill layer (not shown) having good step coverage, e.g., comprising silicon oxide, may be formed on the second capping layer 144 by an HDP-CVD or ALD deposition process. Alternatively, a second filling layer (not shown) having high filling efficiency may be formed on the first filling layer, and the second filling layer may be, for example, TEOS (Tetea-Ethyl-Ortho-Silicate) -based silicon oxide. Optionally, the filling layer 145 may be further planarized by a Chemical Mechanical Polishing (CMP) process, so that the filling layer 145 provides a substantially flat upper surface for the step region 140 of the stacked structure 200.

In the subsequent manufacturing processes of the three-dimensional memory, such as processes of dummy trench holes, word line contact holes, metal interconnects, etc., Amorphous Carbon (a-C) may be formed above the step region 140 as a hard mask, and OH radicals diffused from the filling layer 140 may break down the hard mask of the Amorphous Carbon, thereby generating point discharge (Arcing), which may cause the film structure of the three-dimensional memory to be split, fall off, or even be broken, thereby affecting the performance of the device, and thus it is necessary to release the OH radicals.

During the formation of the filling layer 145 or after the planarization of the filling layer 145, a high temperature annealing process may be performed to make the filling layer 145 denser to prevent the occurrence of embrittlement of the filling layer 145, and simultaneously to release OH radicals in the filling layer 145, which can react with active silicon in the silicon-rich silicon oxide to form a thin silicon dioxide layer, thereby blocking the erosion of the sacrificial layer 202 by the OH radicals in the filling layer 145.

Referring again to fig. 1, the manufacturing method 300 includes operation S350, in which a gate line gap may be formed through the stacked structure and extending into the substrate, and the sacrificial layer is replaced with a conductive layer via the gate line gap. As shown in fig. 7, in some embodiments, after forming the fill layer 145, a plurality of dummy channel structures 113 may be formed in the stacked structure 200 extending into the substrate 10. In some examples, a dummy channel hole (not shown) extending into the first sacrificial layer 102 may be formed in the stack structure 200 using an etching process such as dry etching, wet etching, and the like, and optionally, an insulating material may be filled in the dummy channel hole to form the dummy channel structure 113. It should be understood that fig. 7 only shows one example of the dummy channel structure 113 located in the core region 120, in other examples, a plurality of dummy channel structures 113 may be formed in the step region 140, and the dummy channel structures 113 may sequentially penetrate the filling layer 145, the second capping layer 144, the first capping layer 143, and the stair step 130 in the step region 140 (fig. 2). The role of the dummy channel structure 113 may include, for example, providing structural support to relieve stress.

In some embodiments, a gate line gap (not shown) may also be formed in the stacked structure 200 by using an etching process such as dry etching, wet etching, etc., and the gate line gap may penetrate through the stacked structure 200 and extend into the substrate 10 along the thickness direction of the stacked structure 200.

As shown in fig. 8, in some embodiments, the gate gaps may be used as etching channels, and the sacrificial layer 202 in the stacked structure 200 may be removed by, for example, an isotropic wet etching process, thereby forming the sacrificial gaps 203.

As shown in fig. 9, the gate gap may be used as a deposition channel, and a conductive material may be filled in the sacrificial gap 203 to form a conductive layer 204. Alternatively, conductive layer 204 can be deposited inside sacrificial gap 203 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Illustratively, the material of the conductive layer 204 includes, for example, tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide, or any combination thereof.

In other examples, at least one TiN layer and at least one dielectric layer, such as a high-k dielectric layer, may also be formed in the sacrificial gap 203 prior to forming the conductive layer 204 to reduce leakage current of the word line and to block impurity diffusion of the conductive layer 204. Alternatively, the conductive layer 204 may be formed on a dielectric layer of high dielectric constant.

In some examples, the gate line gap may also be filled in a suitable step to form a gate line gap structure (not shown). Alternatively, an insulating layer (not shown) and a conductor layer (not shown) including, for example, tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide, or any combination thereof may be sequentially formed on the inner wall and the bottom of the gate line gap using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

With continued reference to fig. 1, the method 300 includes an operation S360 in which a word line contact may be formed sequentially through the fill layer, the second capping layer, and the first capping layer and extending into the corresponding conductive layer. As shown in fig. 10, a plurality of word line contacts 115 may be formed over the step structure 142 (fig. 9) that extend through the fill layer 145 and into the corresponding conductive layer 204.

In examples including bonding layer 146 (fig. 5), photolithography and plasma etching processes may be employed to form contact holes (not shown) extending through fill layer 145, second capping layer 144, bonding layer 146, and first capping layer 143 and step 130 (fig. 2) in that order and into corresponding conductive layer 204, over step structures 142.

In the process of forming the contact holes by using, for example, plasma etching, due to the height difference of each step 130, the depth of the contact holes extending into the conductive layer 204 of each step 130 is different, for example, plasma may first contact the conductive layer 204 far from the substrate 10, so that the depth of the contact holes extending into the conductive layers 204 is deeper than the depth of the contact holes extending into the conductive layer 204 near the substrate 10, and therefore, the contact holes may more easily break down the conductive layer 204 far from the substrate 10, so that the contact holes may stop in the dielectric layer 201 under the corresponding conductive layer 204 or extend into the adjacent conductive layer 204. As a result of the breakdown, word line contacts formed later in the contact holes are prone to contact failure or word line leakage problems.

In some embodiments of the present application, the contact holes extending into the corresponding conductive layer 204 may be formed step by step, and optionally, contact holes (not shown) sequentially penetrating through the filling layer 145, the step 130 (fig. 2) and extending into the second capping layer 144 may be formed above the step structure 142 by using processes such as photolithography and plasma etching. Alternatively, the contact hole may also penetrate through the second cover layer 144 and stop within the first cover layer 143, and the first cover layer 143 may have a relatively thicker thickness compared to the second cover layer 144, so that it is easier to adjust the depth to which the contact hole extends by controlling the thickness of the first cover layer 143. As an example, the contact holes may be further processed by etching or the like, so that the contact holes extend into the corresponding conductive layers 204, and since the first cover layer 143 and the second cover layer 144 have certain blocking and buffering functions, the contact holes at different heights may extend into the corresponding conductive layers 204 at almost the same time, thereby reducing the depth difference that the contact holes at different heights extend into the conductive layers 204.

As one example, after forming contact holes extending to the corresponding conductive layer 204, the contact holes may be filled with a conductive material by ALD, PVD, CVD, or any combination thereof to form the word line contacts 115. The word line contacts 115 may be electrically connected to their respective conductive layers 204 so that the conductive layers 204 may be electrically drawn for electrical signal interaction with peripheral circuitry (not shown). Optionally, the conductive material filled in the contact holes may be at least one of tungsten, copper, silver, platinum, iron and cobalt, or an alloy thereof.

Some embodiments of the present application can better control the landing depth of the contact hole at different step levels 130 (fig. 2) to the conductive layer 204 by depositing two step coverage layers (the first coverage layer 143 and the second coverage layer 144) as the landing buffer layer for forming the contact hole, and reduce the problem of poor contact (the contact hole is landed in the dielectric layer 201, for example) or word line leakage (the contact hole is landed in the adjacent conductive layer 204, for example) caused by the contact hole breaking through the conductive layer 204.

Other embodiments of the present application provide a three-dimensional memory 400, wherein the three-dimensional memory 400 can be manufactured by the method 300. As shown in fig. 11, the three-dimensional memory 400 may include: a first semiconductor layer 401, a stacked structure 200 'on the first semiconductor layer 401, wherein the stacked structure 200' may include a plurality of dielectric layers 201 and conductive layers 204 stacked alternately. As an option, the first semiconductor layer 401 may comprise, for example, polysilicon.

As an example, the stacked structure 200' may include a core region 120 and step regions 140 located at both sides of the core region 120; optionally, the stepped region 140 may also be located in the middle of the core region 120. It will be appreciated that for clarity of illustration, only the stepped region 140 is shown in fig. 11 on one side of the core region 120.

In some examples, the stack structure 200' further includes a channel structure 111 located in the core region 120. Alternatively, the channel structure 111 may pass through the alternately stacked dielectric layers 201 and conductive layers 204. In some embodiments, the channel structure 111 may include a barrier layer 112, a storage layer 114, a tunneling layer 116, and a channel layer 118, which are sequentially disposed from the outside to the inside. Optionally, the first semiconductor layer may be in electrical contact with the channel layer 118. In other examples, the stack structure 200' may further include a dummy channel structure 113.

In some examples, stack structure 200' includes a step structure 142 located in step region 140, and step structure 142 may include a plurality of step steps (not shown), each of which may include a thickness of at least one conductive layer 204/dielectric layer 201 pair.

In some examples, as shown in fig. 11, the three-dimensional memory 400 further includes a first capping layer 143 on the step structure 142, the material including, for example, nitrogen-doped silicon carbide. Illustratively, the first capping layer 143 may cover respective step steps of the step structure, and as one example, the first capping layer 143 may cover at least a portion of the conductive layer 204 at each step. Optionally, the first covering layer 143 may cover a surface of the conductive layer 204 located away from the first semiconductor layer 401 of each step, and optionally, the first covering layer 143 may also cover a sidewall of each step.

In some examples, as shown in fig. 11, the three-dimensional memory 400 further includes a second capping layer 144 on the first capping layer 143, and as an example, the material of the second capping layer 144 includes silicon-rich silicon oxide, and the ratio of silicon atoms to oxygen atoms in the silicon-rich silicon oxide is, for example, 1:1 to 2. Optionally, the three-dimensional storage 400 may further include a bonding layer (e.g., bonding layer 146 shown in fig. 5) between the first and second capping layers 143 and 144.

In some examples, as shown in fig. 11, the three-dimensional memory 400 further includes a filling layer 145 located above the step structure 142, and the filling layer 145 may provide a relatively flat surface for the step region 140.

In some examples, the three-dimensional memory 400 may further include a gate line gap structure (not shown) that may penetrate the stack structure 200' in the core region 120 and the step region 140, respectively. Alternatively, the gate gap structure may include an insulating layer (not shown) and a conductive layer (not shown) sequentially disposed from the outside to the inside.

With continued reference to fig. 11, in some examples, the three-dimensional memory 400 further includes word line contacts 115, optionally the word line contacts 115 may extend through the fill layer 145, the second capping layer 144, and the first capping layer 143 in sequence and into the corresponding conductive layer 204. In some examples where three-dimensional memory 400 includes bonding layer 146, word line contacts 115 may extend through fill layer 145, second capping layer 144, bonding layer 146, and first capping layer 143 in that order and into corresponding conductive layers 204.

Since the contents and structures referred to in the above description of the method 300 may be fully or partially applicable to the three-dimensional memory 400 described herein, the contents related or similar thereto will not be described in detail.

Further embodiments of the present application provide a three-dimensional memory 500, the three-dimensional memory 400 can be manufactured by the method 300. As shown in fig. 12, unlike the first semiconductor layer 401 included in the three-dimensional memory 400, the three-dimensional memory 500 may include a second semiconductor layer 502 and a third semiconductor layer 503 thereon. Alternatively, the stacked-layer structure 200' may be disposed on the third semiconductor layer 503.

In some examples, the channel structure 111 may extend into the second semiconductor layer 502, and the third semiconductor layer 503 may sequentially pass through the barrier layer 112, the storage layer 114, and the tunneling layer 116 to electrically contact the channel layer 118. Alternatively, the second semiconductor layer 502 and the third semiconductor layer 503 may be electrically contacted, so that the channel layer 118 can be electrically connected to the second semiconductor layer 502 through the third semiconductor layer 503.

Since the contents and structures referred to in the above description of the method 300 and the three-dimensional memory 400 may be fully or partially applicable to the three-dimensional memory 500 described herein, the contents related or similar thereto will not be described in detail.

Although exemplary methods and structures for fabricating a three-dimensional memory are described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the three-dimensional memory. In addition, the illustrated layers and materials thereof are exemplary only.

As described above, the object, technical means, and advantageous effects of the present application will be described in further detail with reference to the embodiments. It should be understood that the above are only specific embodiments of the present application and are not intended to limit the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. The preparation method of the three-dimensional memory comprises the following steps:

forming a stacked structure comprising alternately stacked dielectric layers and sacrificial layers on a substrate, wherein the stacked structure comprises a step structure located in a step area, and at least one part of the sacrificial layer located in the step structure is exposed;

forming a first capping layer comprising nitrogen-doped silicon carbide on the exposed at least a portion of the sacrificial layer;

forming a second capping layer comprising silicon-rich silicon oxide on the first capping layer; and

and forming a filling layer on the second covering layer.

2. The method of claim 1, wherein at least a portion of the second capping layer in contact with the first capping layer is converted to a bonding layer comprising silicon oxide.

3. The method of claim 2, wherein the silicon-rich silicon oxide comprises elemental silicon, and at least a portion of the elemental silicon in the second capping layer oxidizes to the bonding layer.

4. The method of claim 1, wherein the second capping layer is formed using an atomic layer deposition process or a high density plasma chemical vapor deposition process.

5. The method of claim 1, wherein forming the second capping layer comprises an annealing process at a temperature in a range of 600 ℃ to 1400 ℃.

6. The method of claim 1, further comprising:

forming a gate line gap extending through the stacked structure and into the substrate; and

replacing the sacrificial layer with a conductive layer via the gate line gap.

7. The method of claim 6, further comprising:

and forming word line contact parts which sequentially penetrate through the filling layer, the second covering layer and the first covering layer and extend into the corresponding conductive layers.

8. The method of claim 7, wherein forming the word line contact comprises:

forming a contact hole penetrating through the filling layer and extending into the first covering layer above the step structure; and

and processing the contact holes extending into the first covering layer to extend to the corresponding conductive layers.

9. The method of claim 8, wherein forming the word line contact comprises:

and filling a conductive material in the contact hole to form the word line contact part.

10. A three-dimensional memory, comprising:

the laminated structure comprises dielectric layers and conducting layers which are alternately stacked, and the laminated structure comprises a step structure positioned in a step area;

a first capping layer comprising nitrogen-doped silicon carbide, the first capping layer covering at least a portion of the conductive layer located at the step structure;

a second capping layer comprising silicon-rich silicon oxide, the second capping layer being on the first capping layer; and

and the filling layer is positioned on the second covering layer.

11. The three-dimensional memory of claim 10, further comprising:

a bonding layer between the first capping layer and the second capping layer.

12. The three-dimensional memory according to claim 10, wherein the second capping layer comprises silicon-rich silicon oxide having a ratio of silicon atoms to oxygen atoms of between 1:1 and 2.

13. The three-dimensional memory of claim 10, further comprising:

and the word line contact part sequentially penetrates through the filling layer, the second covering layer and the first covering layer and extends into the corresponding conducting layer.

14. The three-dimensional memory of claim 10, further comprising:

the grid line gap structure comprises an insulating layer and a conductor layer which are sequentially arranged from outside to inside.