CN113937106B - Manufacturing method of three-dimensional memory - Google Patents

Manufacturing method of three-dimensional memory

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Publication number
CN113937106B
CN113937106B CN202111067677.3A CN202111067677A CN113937106B CN 113937106 B CN113937106 B CN 113937106B CN 202111067677 A CN202111067677 A CN 202111067677A CN 113937106 B CN113937106 B CN 113937106B
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China
Prior art keywords
layer
conductive
recess
isolation layer
sublayer
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CN113937106A (en
Inventor
艾义明
颜元
任德营
伍术
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Non-Volatile Memory (AREA)

Abstract

本公开提供一种三维存储器的制造方法，包括：提供半导体结构；半导体结构包括：基底，堆叠结构，位于堆叠结构和基底间的隔离层，贯穿堆叠结构和隔离层并延伸至基底中的栅线隙结构及存储柱；去除基底，显露栅线隙结构的第一端部和存储柱的第二端部；存储柱包括：沟道层，及环绕沟道层的功能层；去除第一端部，形成从隔离层向堆叠结构下凹的第一凹陷，剩余栅线隙结构端部与隔离层接触；去除第二端部显露的功能层，形成从隔离层向堆叠结构下凹的第二凹陷，剩余存储柱端部与隔离层接触；利用导电材料覆盖第一凹陷、第二凹陷及显露的隔离层，对导电材料进行粒子注入形成第二导电层。

This disclosure provides a method for manufacturing a three-dimensional memory, comprising: providing a semiconductor structure; the semiconductor structure including: a substrate, a stacked structure, an isolation layer located between the stacked structure and the substrate, a gate line gap structure extending through the stacked structure and the isolation layer and into the substrate, and a memory pillar; removing the substrate to expose a first end of the gate line gap structure and a second end of the memory pillar; the memory pillar including: a channel layer and a functional layer surrounding the channel layer; removing the first end to form a first recess recessing from the isolation layer into the stacked structure, with the remaining end of the gate line gap structure contacting the isolation layer; removing the functional layer exposed at the second end to form a second recess recessing from the isolation layer into the stacked structure, with the remaining end of the memory pillar contacting the isolation layer; covering the first recess, the second recess, and the exposed isolation layer with a conductive material, and performing particle implantation of the conductive material to form a second conductive layer.

Description

Method for manufacturing three-dimensional memory
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a manufacturing method of a three-dimensional memory.
Background
As semiconductor manufacturing processes continue to increase, process feature sizes become smaller and memory devices have increased in storage density. In order to meet the demand for higher memory density, three-dimensional structured memory devices have been developed. The 3D NAND memory has the advantages of high writing speed, simple erasing operation, higher storage density and the like, and is widely applied.
The conventional 3D NAND memory includes a plurality of storage units stacked in a vertical direction, and can increase storage density in multiple times on a wafer per unit area while reducing costs. In the related art, a means of increasing the number of stacked memory cells is generally adopted to increase the memory density, but the process is more and more complex while the number of stacked memory chips is continuously increased, and defects caused by interaction between different processes are more and more obvious. Therefore, how to optimize the effect between the processes while the number of stacked layers is continuously increased, and reducing the occurrence of defects is a problem to be solved.
Disclosure of Invention
The embodiment of the disclosure provides a method for manufacturing a three-dimensional memory, which comprises the following steps:
the semiconductor structure comprises a substrate, a stacking structure, an isolation layer positioned between the stacking structure and the substrate, a grid line gap structure and a storage column, wherein the grid line gap structure penetrates through the stacking structure and the isolation layer and extends into the substrate;
Removing the substrate to expose the first end of the gate line gap structure and the second end of the storage column, wherein the storage column comprises a channel layer and a functional layer surrounding the channel layer along the radial direction of the storage column;
removing at least part of the first end part to form a first concave which is concave from the isolation layer to the stacking structure, and enabling the end part of the rest grid line gap structure to be in contact with the isolation layer;
Removing the functional layer exposed from the second end part to form a second concave which is concave from the isolation layer to the stacking structure, and enabling the end parts of the rest storage columns to be in contact with the isolation layer;
and covering the first recess, the second recess and the exposed isolation layer by using a conductive material, and performing particle implantation on the conductive material to form a second conductive layer.
In some embodiments of the present invention, in some embodiments,
The gate line gap structure comprises a third conductive layer and a second insulating layer surrounding the third conductive layer;
Removing at least part of the first end portion to form a first recess recessed from the isolation layer toward the stacked structure, and contacting the end portion of the gate line gap structure with the isolation layer, wherein the method comprises the following steps:
And removing the second insulating layer at the first end part to form the first recess based on the isolation layer, the third conductive layer and the rest of the second insulating layer, wherein the first recess surrounds the third conductive layer, and the depth of the side wall of the first recess is smaller than the thickness of the isolation layer along the first direction perpendicular to the substrate.
In some embodiments of the present invention, in some embodiments,
The second insulating layer comprises a first sub-layer and a second sub-layer surrounding at least part of the first sub-layer;
the removing the second insulating layer of the first end portion to form the first recess includes:
The first and second sub-layers of the first end portion are removed with an etchant to form the first recess based on the isolation layer, the third conductive layer, the remaining first sub-layer, and the remaining second sub-layer.
In some embodiments of the present invention, in some embodiments,
The functional layer comprises a blocking sub-layer, a storage sub-layer and a tunneling sub-layer along the radial direction of the storage column, wherein the tunneling sub-layer is positioned between the storage sub-layer and the channel layer;
The removing the functional layer exposed from the second end portion, forming a second recess recessed from the isolation layer toward the stacked structure, and the remaining end portion of the storage column being in contact with the isolation layer, includes:
And removing the blocking sub-layer, the storage sub-layer and the tunneling sub-layer exposed by the second end part to form the second recess based on the isolation layer, the storage column, the rest of the blocking sub-layer, the rest of the storage sub-layer and the rest of the tunneling sub-layer, wherein the depth of the side wall of the second recess is smaller than the thickness of the isolation layer along the first direction perpendicular to the substrate.
In some embodiments of the present invention, in some embodiments,
The thickness of the second conductive layer is smaller than the thickness of the channel layer protruding out of the isolation layer along the first direction perpendicular to the substrate;
the method further comprises the steps of:
and forming a fourth conductive layer covering the second conductive layer, wherein the thickness of the fourth conductive layer is larger than that of the channel layer protruding out of the isolation layer.
In some embodiments of the present invention, in some embodiments,
The thickness of the second conductive layer is 20nm to 100nm, and the thickness of the fourth conductive layer is 200nm to 500nm.
In some embodiments of the present invention, in some embodiments,
The isolation layer comprises a first insulating sub-layer, a first conductive sub-layer and a second insulating sub-layer which are sequentially arranged along a first direction perpendicular to the substrate, wherein the first insulating sub-layer is positioned between the first conductive sub-layer and the substrate, and the second insulating sub-layer is positioned between the first conductive sub-layer and the stacked structure;
the method further comprises the steps of:
after removing the substrate, removing the first insulating sub-layer to expose the first conductive sub-layer.
In some embodiments, the method further comprises:
Forming the isolation layer on the substrate along a first direction perpendicular to the substrate;
forming a laminated structure on the isolation layer, wherein the laminated structure comprises a plurality of sacrificial layers and a plurality of first insulating layers which are alternately laminated in turn;
Forming a channel hole penetrating the laminated structure, the isolation layer and extending into the substrate along the first direction;
filling the side wall of the channel hole to form the functional layer;
The channel layer is formed to cover the functional layer.
In some embodiments, the method further comprises:
forming a trench penetrating through the laminated structure, the isolation layer and extending into the substrate along the first direction after forming the channel layer;
Removing the plurality of sacrificial layers in the stacked structure based on the trench to form a gap between adjacent first insulating layers;
And filling the gaps to form a plurality of first conductive layers.
In some embodiments, the method further comprises:
And forming a dielectric layer covering the first insulating layer and the functional layer exposed by the gaps in the gaps and in the grooves before forming the plurality of first conductive layers, wherein the dielectric layer is positioned between the first conductive layers and the insulating layers and between the first conductive layers and the functional layers.
In the related art, particle implantation is generally performed on the first end portion of the exposed gate line gap structure and the second end portion of the memory pillar, then at least part of the first end portion of the gate line gap structure and the second end portion of the memory pillar are etched away, and finally a conductive material is deposited. However, after the particle implantation is performed on the first end portion and the second end portion, the etching rate in the subsequent etching process may be increased, which results in overetching the first end portion and/or the second end portion, so that the subsequently deposited conductive material is electrically connected to the conductive layer in the stacked structure, resulting in leakage current and failure of the device.
According to the scheme provided by the embodiment of the disclosure, through optimizing the process steps, at least part of the first end part and part of the second end part are removed firstly, then the conductive material is deposited, finally the particle injection is carried out to form the conductive layer, so that the influence of the particle injection process on the gate line gap structure and the performance of the storage column is reduced, the formed first concave and second concave are in contact with the isolation layer, the conductive layer in the stacked structure is not exposed by the first concave and the second concave, the finally formed second conductive layer is electrically insulated from the conductive layer in the stacked structure, the occurrence probability of electric leakage between the second conductive layer and the conductive layer in the stacked structure is reduced, and the yield of the device is improved.
Drawings
FIGS. 1a to 1e are schematic views of a method of manufacturing a three-dimensional memory;
FIG. 2 is a flow diagram illustrating a method of fabricating a three-dimensional memory according to an embodiment of the present disclosure;
Fig. 3a to 3f are schematic views showing a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure;
Fig. 4a to 4g are schematic views illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure.
Detailed Description
The technical scheme of the present disclosure is further elaborated below in conjunction with the drawings of the specification and the specific embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.
It is to be understood that the meaning of "on," "over," "above," and "above" of the present disclosure should be read in the broadest manner so that "on" means not only that it is "on" something and there is no intervening feature or layer therebetween (i.e., directly on something), but also that it is "on" and there is an intervening feature or layer therebetween.
In the presently disclosed embodiments, the terms "first," "second," and the like are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
In the presently disclosed embodiments, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entirety of the underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal facing at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along an inclined surface. The layer may comprise a plurality of sub-layers. For example, the isolation layer includes a first insulating sub-layer, a first conductive sub-layer, and a second insulating sub-layer sequentially disposed along the first direction.
The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.
Fig. 1a to 1e are schematic diagrams illustrating a method of manufacturing a three-dimensional memory according to an exemplary embodiment, the method comprising the steps of:
Referring to fig. 1a, a semiconductor structure is provided, wherein the semiconductor structure comprises a substrate 100, a stack structure 110, an isolation layer 120 between the stack structure 110 and the substrate 100, a gate line gap structure 130 penetrating the stack structure 110 and the isolation layer 120 and extending into the substrate 100, and a storage column 140, and the stack structure 110 comprises a plurality of first conductive layers 111 and a plurality of first insulating layers 112 which are alternately stacked in sequence along a first direction perpendicular to the substrate 100. The isolation layer 120 further includes a first insulating sub-layer 121, a first conductive sub-layer 122, and a second insulating sub-layer 123.
Step two, referring to fig. 1b, the substrate 100 is removed to expose the first end 131 of the gate line gap structure 130 and the second end 141 of the storage pillar 140, and the storage pillar 140 includes a channel layer 142 and a functional layer 143 between the channel layer 142 and the stacked structure 110 along the radial direction of the storage pillar 140. The functional layer 143 may include a silicon oxide/silicon nitride/silicon oxide (ONO) composite layer.
Referring to fig. 1c, the functional layer 143 exposed at the second end 141 is etched and removed to form a second recess 160 recessed from the isolation layer 120 toward the stacked structure 110, the end of the remaining memory pillar 140 is in contact with the isolation layer 120, and the channel layer 142 in the second recess 160 is subjected to particle implantation.
Illustratively, the process of etching to remove the second end may be one or any combination of wet etching, dry etching.
Step four, referring to fig. 1d, the first end 131 is etched away, forming a first recess 150 recessed from the isolation layer 120 toward the stack structure 110, and the end of the remaining gate line gap structure is in contact with the isolation layer 120. In this embodiment, the first insulating sublayer 121 is also etched away during the etching process.
Illustratively, the process of etching away the first end may be one or any combination of wet etching, dry etching.
Referring to fig. 1e, a conductive layer 170 is formed by covering the first recess 150, the second recess 160 and the exposed isolation layer 120 with a conductive material, and can be electrically connected to the channel layer 142 of the memory pillar 140 to serve as an array common source (Array Common Source, ACS) of the 3D NAND to supply power to the memory cell. The conductive material is preferably polysilicon.
The first direction is a direction perpendicular to the substrate, which may be a Z direction in the drawing, and the second direction is a direction parallel to the substrate, which may be an X direction in the drawing.
However, in the actual memory manufacturing process, defects may be generated due to the mutual influence between successive processes. Specifically, referring to fig. 1c and 1d, when the particle implantation process is performed on the second recess 160, the first end 131 is damaged by the high-energy particles of the particle implantation, so that the etching rate of the first end 131 in the fourth step is increased when the etching removal process is performed, resulting in the occurrence of the overetching phenomenon.
Referring to fig. 1d, the gate line gap structure may include a second insulating layer 135 and a third conductive layer 134, and in the second direction, the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133 between the first sub-layer 132 and the stack structure 110. The first sub-layer 132 is a high dielectric material, preferably an alumina material in the disclosed embodiment, the second sub-layer 133 is an insulating material, preferably a low temperature silicon oxide (LTO) material in the disclosed embodiment, and the third conductive layer 134 is preferably a polysilicon material.
After the particle implantation is performed, the etching rate of the first sub-layer 132 is increased by 5 to 15 times and the etching rate of the low temperature silicon oxide Layer (LTO) is increased by 1 to 2 times by etching with the HF etchant, so that the first recess 150 exposes the first conductive layer 111 to form a circle in fig. 1e after the step five is completed, that is, the conductive layer 170 contacts the first conductive layer 111, resulting in leakage defect and affecting the electrical performance of the memory.
Based on this, the disclosed embodiments provide a manufacturing method.
Fig. 2 is a flow diagram illustrating a method of manufacturing a three-dimensional memory according to an embodiment of the present disclosure. Referring to fig. 2, the method comprises the steps of:
S100, providing a semiconductor structure, wherein the semiconductor structure comprises a substrate, a stacking structure, an isolation layer positioned between the stacking structure and the substrate, a grid line gap structure penetrating through the stacking structure and the isolation layer and extending into the substrate, and a storage column;
s200, removing the substrate to expose the first end of the grid line gap structure and the second end of the storage column, wherein the storage column comprises a channel layer and a functional layer surrounding the channel layer along the radial direction of the storage column;
S300, removing at least part of the first end part to form a first concave which is concave from the isolation layer to the stacking structure, wherein the end part of the residual grid line gap structure is contacted with the isolation layer;
S400, removing the functional layer exposed from the second end part to form a second concave which is concave from the isolation layer to the stacking structure, wherein the end parts of the rest storage columns are contacted with the isolation layer;
and S500, covering the first concave, the second concave and the exposed isolation layer by using a conductive material, and performing particle implantation on the conductive material to form a second conductive layer.
Fig. 3a to 3f are schematic views illustrating a method for manufacturing a three-dimensional memory according to an embodiment of the present disclosure, and the method provided by the present disclosure will be described in further detail with reference to fig. 3a to 3 f.
First, referring to FIG. 3a, a step S100 is performed in which a semiconductor structure is provided, wherein the semiconductor structure comprises a substrate 100, a stack structure 110, an isolation layer 120 between the stack structure 110 and the substrate 100, a gate line gap structure 130 extending into the substrate 100 through the stack structure 110 and the isolation layer 120, and a memory pillar 140, wherein the stack structure 110 comprises a plurality of first conductive layers 111 and a plurality of first insulating layers 112 alternately stacked in sequence along a first direction perpendicular to the substrate 100.
By way of example, the constituent materials of the substrate 100 may include elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art. The preferred semiconductor material in fig. 3a is polysilicon.
By way of example, the constituent materials of the plurality of first conductive layers 111 may include monocrystalline silicon material, polycrystalline silicon material, metallic tungsten material, or other conductive materials known in the art.
By way of example, the constituent materials of the plurality of first insulating layers 112 may include a high temperature silicon oxide material, a low temperature silicon oxide material, a silicon nitride material, a silicon oxynitride material, or other insulating materials known in the art. Wherein the high temperature silicon oxide material may comprise a silicon oxide material deposited at a chemical vapor deposition temperature in the range of 600 ℃ to 800 ℃, and the low temperature silicon oxide material may comprise a silicon oxide material deposited at a chemical vapor deposition temperature in the range of 350 ℃ to 450 ℃.
It is emphasized that the constituent materials of the different first conductive layers 111 may be different, and the constituent materials of the different first insulating layers 112 may be different.
Referring to fig. 3a, the isolation layer 120 may also be a different material layer formed by depositing different materials, and the isolation layer 120 may include a first insulating sub-layer 121, a first conductive sub-layer 122, and a second insulating sub-layer 123 sequentially disposed along a first direction, the first insulating sub-layer 121 being located between the first conductive sub-layer 122 and the substrate 100, and the second insulating sub-layer 123 being located between the first conductive sub-layer 122 and the stacked structure 110.
The formation method of the above material layer may be any technique known to those skilled in the art, such as a low temperature chemical Vapor Deposition (Low Temperature Chemical Vapor Deposition, LTCVD) process, a low pressure chemical Vapor Deposition (Low Pressure Chemical Vapor Deposition, LPCVD) process, a rapid thermal chemical Vapor Deposition (Rapid Thermo Chemical Vapor Deposition, RTCVD) process, an atomic layer Deposition (Atomics Layer Deposition, ALD) process, or an ion-enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD) process.
Referring to fig. 3b, step S200 is performed by removing the substrate 100 to expose the first end 131 of the gate line gap structure 130 and the second end 141 of the memory pillar 140, wherein the memory pillar 140 includes a channel layer 142 and a functional layer 143 between the channel layer 142 and the stacked structure 110 in a radial direction of the memory pillar 140.
By way of example, the removal process of the substrate 100 may include dry etching, wet etching, chemical mechanical polishing planarization, or a combination thereof. The dry etching gas may include CF 4,C2F6,NF3,Cl2,O2,NH3 or a combination of the above gases. The wet etchant may include HF, H 3PO4, KOH, or a combination of the above solutions.
After the substrate is removed, the conductive layer may be reformed from where the original substrate was located to electrically connect the sources of the plurality of channel structures, thereby increasing the conductance of the Array Common Source (ACS) of the channel structures. In some embodiments, the conductive layer includes a metal silicide layer in contact with the semiconductor channel of the channel structure to reduce contact resistance, and further includes a metal layer in contact with the metal silicide layer to further reduce overall resistance. As a result, the thickness of the semiconductor layer (N-type doping or P-type doping) as part of ACS can be reduced without affecting ACS conductance.
Referring to fig. 3c, step S300 is performed in which the first end portion 131 is removed, forming a first recess 150 recessed from the isolation layer 120 toward the stack structure 110, and the end portion of the remaining gate line gap structure is in contact with the isolation layer 120.
In some embodiments, the gate gap structure includes a third conductive layer 134, and a second insulating layer 135 surrounding the third conductive layer 134.
Step S300 may further include removing the second insulating layer 135 of the first end portion 131 to form a first recess 150 based on the isolation layer 120, the third conductive layer 134, and the remaining second insulating layer 135, wherein the first recess 150 surrounds the third conductive layer 134, and a sidewall depth of the first recess 150 is smaller than a thickness of the isolation layer 120 in the first direction.
Illustratively, the constituent materials of the third conductive layer 134 may include any materials referred to in the art, including single crystal silicon, polysilicon, metallic tungsten, metallic copper, metallic titanium, or any combination thereof. In the embodiments of the present disclosure, a polysilicon material is preferably used.
Illustratively, the removal process may include dry etching, wet etching, or any combination thereof.
It is emphasized that the role of the conductive material is not limited to the conductive connection, but can also be used as a support. The third conductive layer 134 may be replaced by an insulating material, such as a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., as required by the process, and may be flexibly selected by those skilled in the art.
Referring to fig. 3c, in the embodiment of the present disclosure, the sidewall of the first recess 150 has a depth D 1 in the first direction, the thickness D 2,D1 of the isolation layer 120 in the first direction has a value smaller than that of D 2, and the magnitudes of the depths D 1 and D 2 can be controlled by the etching time, the etchant ratio, and the etching temperature. Further, during the etching removal of the first end 131, the etchant may also have a small etching removal of the second end 141, the removal being related to the selectivity of the etchant.
It is understood that in the embodiment of the present disclosure, the first recess is not in contact with the first conductive layer, so that defects similar to the leakage of the sidewalls of the first recess to the gate shown in fig. 1d are avoided when the conductive layer is deposited later.
With continued reference to fig. 3c, in some embodiments, the second insulating layer 135 includes a first sub-layer 132 and a second sub-layer 133 surrounding at least a portion of the first sub-layer.
Step S300 may further include removing the first sub-layer 132 and the second sub-layer 133 of the first end portion 131 using an etchant to form the first recess 150 based on the isolation layer 120, the third conductive layer 134, the remaining first sub-layer 132, and the remaining second sub-layer 133.
The second direction is a direction parallel to the plane of the substrate 100, and the first sub-layer 132 is a high dielectric material having a dielectric constant higher than that of silicon dioxide, preferably an alumina material in the embodiments of the present disclosure. The second sub-layer 133 is an insulating material, including a silicon oxide material and a silicon nitride material. The low temperature silicon oxide materials described above are preferred in the embodiments of the present disclosure.
During etching of the first end portion 131, the etchant etches the first sub-layer 132 and the second sub-layer 133 at a comparable rate, and the third conductive layer 134 etches less or substantially no than the first sub-layer 132 and the second sub-layer 133, thereby forming a first recess 150 surrounding the third conductive layer 134.
Further, the first sub-layer 132 and the second sub-layer 133 are etched to be substantially on the same horizontal plane, so that the surface of the formed first recess 150 is smoother, a better deposition interface is provided for the formation of the subsequent second conductive layer 171, the morphology of the subsequent second conductive layer 171 is optimized, and meanwhile, the structural integrity of the third conductive layer 134 is maintained, so that defects are further reduced and the yield is improved.
Referring to fig. 3d, step S400 is performed in which the functional layer 143 exposed at the second end 141 is removed, forming a second recess 160 recessed from the isolation layer 120 toward the stack structure 110, and the ends of the remaining memory pillars 140 are in contact with the isolation layer 120.
The second recess 160 is recessed in a direction perpendicular to the substrate 100, and is also directed away from the substrate 100 and toward the stacked structure 110.
With continued reference to FIG. 3d, in some embodiments, in the radial direction of the memory pillar 140, the functional layer 143 includes a blocking sublayer 144, a memory sublayer 145, and a tunneling sublayer 146, wherein the tunneling sublayer 144 is located between the memory sublayer 145 and the channel layer 142.
Step S400 may further include removing the blocking sub-layer 144, the memory sub-layer 145, and the tunneling sub-layer 146 exposed at the second end 141 to form a second recess 160 based on the isolation layer 120, the memory pillar, the remaining blocking sub-layer 144, the remaining memory sub-layer 145, and the remaining tunneling sub-layer 146, wherein a sidewall depth of the second recess 160 is less than a thickness of the isolation layer 120 in the first direction.
Illustratively, the barrier sublayer 144 may comprise silicon oxide, silicon oxynitride, high dielectric, or any combination thereof. Tunneling sublayer 146 may comprise silicon oxide, silicon oxynitride, or any combination thereof. The memory sub-layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. In this embodiment, the combination of functional layers 143 is preferably a composite layer of silicon oxide/silicon nitride/silicon oxide (ONO).
The removal process may be dry etching, wet etching, or any combination thereof. Referring to fig. 3d, the etching removal process has a comparable selectivity to the functional layer 143, i.e., the etched stop layers of the sub-layers of the functional layer 143 are substantially on the same level, and the remaining stop layers and the memory pillars form the second recesses 160 based on the isolation layer 120. The second recess 160 having a flatter surface provides a better deposition interface for subsequent formation of the second conductive layer 171, optimizing the topography of the subsequently formed second conductive layer 171. Meanwhile, the removal etching has low selectivity to the channel layer 142, reduces defects of the channel layer 142, and further optimizes the conductivity of the channel layer 142.
Referring to fig. 3D, the second recess 160 has thicknesses D 3 and D 4, respectively, in a first direction perpendicular to the substrate 100 and a second direction parallel to the substrate 100, both of which are smaller than the thickness D 5 of the isolation layer 120 in the corresponding direction, and in some embodiments, the sizes of D 3 and D 4 may be controlled by the etching time, the etchant ratio, and the etching temperature.
It is understood that the second recess 160 is not in contact with the first conductive layer at the bottom layer, so as to avoid the occurrence of defects in the subsequent process, such as leakage of electricity from the second recess 160 to the first conductive layer as shown in fig. 1 d.
Referring to fig. 3e, step S500 is performed in which the first recess 150, the second recess 160, and the exposed isolation layer 120 are covered with a conductive material, and the conductive material is subjected to particle implantation to form a second conductive layer 171.
The conductive material may include a monocrystalline silicon material, a polycrystalline silicon material, or an amorphous silicon material, and in this embodiment, the polycrystalline silicon material is used and is subjected to particle implantation to form the second conductive layer 171, thereby reducing resistance and optimizing conductive performance. In some embodiments, the particle implant element comprises any one of boron, arsenic, phosphorus, germanium, gallium, antimony.
In some embodiments, the second conductive layer 171 is formed to electrically connect the channel layers 142 of the respective memory pillars 140 by doping (N-type doping or P-type doping), and serves as an Array Common Source (ACS) of the three-dimensional memory to supply power to the memory cells.
Referring to fig. 3f, in some embodiments, step S500 further comprises:
The thickness of the second conductive layer 171 is smaller than the thickness of the channel layer 142 protruding from the isolation layer 120 along the first direction, and a fourth conductive layer 172 is formed to cover the second conductive layer 171, wherein the thickness of the fourth conductive layer 172 is larger than the thickness of the channel layer 142 protruding from the isolation layer 120.
By controlling the thickness of the second conductive layer 171 in fig. 3e to be smaller than the thickness of the channel layer 142 protruding from the isolation layer 120, i.e., the second conductive layer 171 does not completely cover the exposed isolation layer 120. Referring to fig. 3f, immediately after the second conductive layer 171 is formed as shown in fig. 3e, a fourth conductive layer 172 is formed over the second conductive layer to cover the portion of the channel layer 142 protruding from the isolation layer 120.
The thickness of the fourth conductive layer 172 may be selected according to process requirements in some embodiments, the deposition material may be the same as the first conductive layer 111, and then the same particle implantation process as the fourth conductive layer 172 may be performed. In other words, this is manufactured by dividing the second conductive layer 171 shown in fig. 3e into two parts, and manufacturing one part of the conductive layer and then manufacturing the other part of the conductive layer according to the process.
In some embodiments, fourth conductive layer 172 has a thickness D 5 that is greater than a thickness D 6 of second conductive layer 171, wherein the second conductive layer has a thickness of 20nm to 100nm and the fourth conductive layer has a thickness of 200nm to 500nm. Preferred D 5 in the presently disclosed embodiments is 100nm and D 6 is 300nm.
It can be appreciated that the conductive layer to be implanted with particles can be made thick and the conductive performance can be optimized by forming the conductive layer in steps, and meanwhile, the thin conductive layer deposited earlier can protect the bottom of the stacked structure 110, so as to avoid defects caused by overlarge particle implantation energy and enlarge the process window of particle implantation.
In some embodiments, the method for manufacturing a three-dimensional memory further includes:
After the step S100 is performed, the isolation layer of the semiconductor structure provided includes a plurality of sub-layers, and then the subsequent step S200 is performed, so that the isolation sub-layers to be removed can be flexibly selected according to the requirements of the manufacturing process in the process of removing the substrate, so as to meet the manufacturing requirements.
Referring to fig. 3a and 3b, the spacer layer thickness of embodiments of the present disclosure is preferably 100nm and may comprise layers of different materials. The isolation layer 120 includes a first insulating sub-layer 121, a first conductive sub-layer 122, and a second insulating sub-layer 123 sequentially disposed along a first direction, the first insulating sub-layer 121 being positioned between the first conductive sub-layer 122 and the substrate 100, and the second insulating sub-layer 123 being positioned between the first conductive sub-layer 122 and the stacked structure 110.
After removing the substrate 100, the first insulating sub-layer 121 is removed to expose the first conductive sub-layer 122 as shown in fig. 3 c.
Referring to fig. 3e and 3f, in the embodiment of the present disclosure, after the first insulating sub-layer 121 is removed, the exposed first conductive sub-layer 122 may be in contact with the second conductive layer 171 formed in the subsequent step S500, the first conductive sub-layer 122 is in close contact with the second conductive layer 171, increasing the thickness of the conductive layer and optimizing the conductive performance, and the first conductive sub-layer 122 may be the same material as the second conductive layer 171, and may further optimize the contact performance between the two material layers. The material of the first insulating layer 112 and the second insulating layer 135 may be one of silicon oxide, silicon nitride, and silicon oxynitride, and in this embodiment, silicon oxide is preferred, and the material of the first conductive sub-layer 122 may be one of monocrystalline silicon and polycrystalline silicon, and in this embodiment, polycrystalline silicon is preferred, and the same material as that of the second conductive layer 171.
The method of fabricating the semiconductor structure is described in detail below in conjunction with fig. 4 a-4 g:
Referring to fig. 4a, a substrate 100 is provided, and an isolation layer 120 is formed along a first direction perpendicular to the substrate 100, wherein the isolation layer 120 may include a plurality of sub-layers including a first insulating sub-layer 121, a first conductive sub-layer 122, and a second insulating sub-layer 123, the first insulating sub-layer 121 being located between the first conductive sub-layer 122 and the substrate 100, and the second insulating sub-layer 123 being located between the first conductive sub-layer 122 and the stacked structure 110. A stacked structure including a plurality of sacrificial layers and a plurality of first insulating layers 112 alternately stacked in this order is formed on the spacer layer 120. In this embodiment, the first insulating sub-layer 121 and the second insulating sub-layer 123 are preferably made of silicon oxide, and the first conductive sub-layer 122 is preferably made of polysilicon. The sacrificial layer material may comprise one of silicon nitride, silicon oxynitride, monocrystalline silicon, and polycrystalline silicon material, and is preferably a silicon nitride material, and the first insulating layer 112 material comprises one of silicon oxide and silicon oxynitride material, and is preferably a silicon oxide material.
Referring to fig. 4b, a channel hole 14 is formed, the channel hole 14 vertically penetrating the stacked structure in the first direction, the isolation layer 120 extending to the channel hole 14 in the substrate 100;
referring to fig. 4c, the sidewalls of the channel hole 14 are filled to form a functional layer 143. In this embodiment, the combination of the functional layers 143 is preferably a composite layer of a blocking sub-layer 144, a memory sub-layer 145, and a tunneling sub-layer 146, and the material is preferably silicon oxide/silicon nitride/silicon oxide (ONO).
Referring to fig. 4d, a channel layer 142 is formed to cover the functional layer 143, and the channel layer 142 is preferably made of a polysilicon material. In some embodiments, the channel layer 142 may entirely fill the channel hole 14, the channel layer 142 may be filled along the sidewalls based on the morphology of the functional layer 143, and then the channel hole 14 is filled with silicon oxide to form a channel core 147, and the channel core 147 may also include an air gap 148 to improve stress.
Referring to fig. 4e, after forming the channel layer 142, forming a trench penetrating the stacked structure, the isolation layer 120, and extending into the substrate 100 in the first direction;
Referring to fig. 4f, the conductive material fills the gaps, forming a plurality of first conductive layers 111. The conductive material may be one of tungsten metal, monocrystalline silicon, and polycrystalline silicon, and the embodiment is preferably tungsten metal. The trench is filled with a third conductive layer 134, and a second insulating layer 135 located between the third conductive layer 134 and the stacked structure 110, to form a gate line gap structure, preferably the third conductive layer 134 is preferably made of polysilicon, the second insulating layer 135 is composed of a first sub-layer 132 and a second sub-layer 133, the first sub-layer 132 is preferably made of alumina, and the second sub-layer 133 is preferably made of low temperature silicon oxide.
Referring to fig. 4g, in some embodiments, before forming the first conductive layer 111, a dielectric layer 115 is formed in the gap and in the trench to cover the first insulating layer 112 and the functional layer 143 exposed by the gap, and the dielectric layer 115 is located between the first conductive layer 111 and the insulating layer 112 and between the first conductive layer 111 and the functional layer 143. The dielectric layer material can be one of silicon oxide, silicon oxynitride, titanium nitride and aluminum oxide. In this embodiment, the dielectric layer material is preferably alumina, which is the same as the material of the first sub-layer 132, so as to reduce the interlayer contact stress between the first sub-layer 132 and the dielectric layer 115, and save the process cost.
In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other manners. The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1.一种三维存储器的制造方法，其特征在于，包括：1. A method for manufacturing a three-dimensional memory, characterized in that it comprises: 提供半导体结构；其中，所述半导体结构包括：基底，堆叠结构，位于所述堆叠结构和所述基底间绝缘的隔离层，贯穿所述堆叠结构和所述隔离层并延伸至所述基底中的栅线隙结构以及存储柱；A semiconductor structure is provided; wherein the semiconductor structure includes: a substrate, a stacked structure, an isolation layer insulating between the stacked structure and the substrate, a gate gap structure extending through the stacked structure and the isolation layer and into the substrate, and a memory pillar; 去除所述基底，以显露所述栅线隙结构的第一端部和所述存储柱的第二端部；其中，沿所述存储柱的径向，所述存储柱包括：沟道层，以及环绕所述沟道层的功能层；所述栅线隙结构包括：第三导电层，以及包围所述第三导电层的第二绝缘层；The substrate is removed to expose a first end of the gate gap structure and a second end of the memory pillar; wherein, along the radial direction of the memory pillar, the memory pillar includes: a channel layer and a functional layer surrounding the channel layer; the gate gap structure includes: a third conductive layer and a second insulating layer surrounding the third conductive layer; 去除至少部分所述第一端部，形成从所述隔离层向所述堆叠结构下凹的第一凹陷，剩余所述栅线隙结构的端部与所述隔离层接触；所述第三导电层凸出于所述第一凹陷；沿垂直于所述基底的第一方向，所述第一凹陷的侧壁深度小于所述隔离层的厚度；At least a portion of the first end is removed to form a first recess that is recessed from the isolation layer into the stacked structure, with the remaining end of the gate gap structure contacting the isolation layer; the third conductive layer protrudes from the first recess; along a first direction perpendicular to the substrate, the sidewall depth of the first recess is less than the thickness of the isolation layer; 去除所述第二端部显露的所述功能层，形成从所述隔离层向所述堆叠结构下凹的第二凹陷，剩余所述功能层的端部与所述隔离层接触；所述沟道层凸出于所述第二凹陷；沿所述第一方向，所述第二凹陷的侧壁深度小于所述隔离层的厚度；The functional layer exposed at the second end is removed to form a second recess that is recessed from the isolation layer into the stacked structure, and the end of the remaining functional layer contacts the isolation layer; the channel layer protrudes from the second recess; along the first direction, the sidewall depth of the second recess is less than the thickness of the isolation layer; 利用导电材料覆盖所述第一凹陷、所述第二凹陷以及显露的所述隔离层，并对所述导电材料进行粒子注入形成第二导电层。A conductive material is used to cover the first recess, the second recess, and the exposed isolation layer, and the conductive material is then subjected to particle implantation to form a second conductive layer. 2.根据权利要求1所述的方法，其特征在于，2. The method according to claim 1, characterized in that, 所述去除至少部分所述第一端部，形成从所述隔离层向所述堆叠结构下凹的第一凹陷，剩余所述栅线隙结构的端部与所述隔离层接触，包括：The removal of at least a portion of the first end, forming a first recess that extends from the isolation layer into the stacked structure, wherein the remaining end of the gate gap structure contacts the isolation layer, includes: 去除所述第一端部的所述第二绝缘层，以基于所述隔离层、所述第三导电层以及剩余的所述第二绝缘层形成所述第一凹陷；其中，所述第一凹陷围绕所述第三导电层。The second insulating layer at the first end is removed to form the first recess based on the isolation layer, the third conductive layer, and the remaining second insulating layer; wherein the first recess surrounds the third conductive layer. 3.根据权利要求2所述的方法，其特征在于，所述第二绝缘层包括：第一子层，以及至少包围部分所述第一子层的第二子层；3. The method according to claim 2, wherein the second insulating layer comprises: a first sublayer, and a second sublayer that at least partially surrounds the first sublayer; 所述去除所述第一端部的所述第二绝缘层，形成所述第一凹陷，包括：The step of removing the second insulating layer at the first end to form the first recess includes: 利用刻蚀剂去除所述第一端部的所述第一子层和所述第二子层，以基于所述隔离层、所述第三导电层、剩余的所述第一子层以及剩余的所述第二子层形成所述第一凹陷。The first sublayer and the second sublayer at the first end are removed using an etchant to form the first recess based on the isolation layer, the third conductive layer, the remaining first sublayer, and the remaining second sublayer. 4.根据权利要求1所述的方法，其特征在于，沿所述存储柱的径向，所述功能层包括：阻挡子层、存储子层和隧穿子层，所述隧穿子层位于所述存储子层和所述沟道层之间；4. The method according to claim 1, wherein, along the radial direction of the storage column, the functional layer comprises: a barrier sublayer, a storage sublayer, and a tunneling sublayer, wherein the tunneling sublayer is located between the storage sublayer and the channel layer; 所述去除所述第二端部显露的所述功能层，形成从所述隔离层向所述堆叠结构下凹的第二凹陷，剩余所述存储柱的端部与所述隔离层接触，包括：The step of removing the functional layer exposed at the second end to form a second recess extending from the isolation layer into the stacked structure, with the remaining end of the storage column contacting the isolation layer, includes: 去除所述第二端部显露的所述阻挡子层、所述存储子层和所述隧穿子层，以基于所述隔离层、所述存储柱、剩余的所述阻挡子层、剩余的所述存储子层和剩余的所述隧穿子层形成所述第二凹陷。Remove the barrier sublayer, storage sublayer, and tunneling sublayer exposed at the second end to form the second recess based on the isolation layer, the storage pillar, the remaining barrier sublayer, the remaining storage sublayer, and the remaining tunneling sublayer. 5.根据权利要求1所述的方法，其特征在于，沿所述第一方向，所述第二导电层的厚度，小于所述沟道层凸出于所述隔离层的厚度；5. The method according to claim 1, wherein, along the first direction, the thickness of the second conductive layer is less than the thickness of the channel layer protruding from the insulating layer; 所述方法还包括：形成覆盖所述第二导电层的第四导电层；其中，所述第四导电层的厚度，大于所述沟道层凸出于所述隔离层的厚度。The method further includes: forming a fourth conductive layer covering the second conductive layer; wherein the thickness of the fourth conductive layer is greater than the thickness of the channel layer protruding from the isolation layer. 6.根据权利要求5所述的方法，其特征在于，所述第二导电层厚度为20nm至100nm；所述第四导电层厚度为200nm至500nm。6. The method according to claim 5, wherein the thickness of the second conductive layer is 20 nm to 100 nm; and the thickness of the fourth conductive layer is 200 nm to 500 nm. 7.根据权利要求1所述的方法，其特征在于，所述隔离层包括：沿所述第一方向依次设置的第一绝缘子层、第一导电子层和第二绝缘子层，所述第一绝缘子层位于所述第一导电子层和所述基底之间，所述第二绝缘子层位于所述第一导电子层和所述堆叠结构之间；7. The method according to claim 1, wherein the isolation layer comprises: a first insulator layer, a first conductive layer and a second insulator layer disposed sequentially along the first direction, wherein the first insulator layer is located between the first conductive layer and the substrate, and the second insulator layer is located between the first conductive layer and the stacked structure; 所述方法还包括：在去除所述基底之后，去除所述第一绝缘子层，以显露所述第一导电子层。The method further includes removing the first insulator layer after removing the substrate to expose the first conductive layer. 8.根据权利要求1所述的方法，其特征在于，所述方法还包括：8. The method according to claim 1, characterized in that the method further comprises: 沿所述第一方向，在所述基底上形成所述隔离层；The isolation layer is formed on the substrate along the first direction; 在所述隔离层上形成叠层结构；其中，所述叠层结构包括依次交替层叠设置的多个牺牲层和多个第一绝缘层；A stacked structure is formed on the isolation layer; wherein the stacked structure includes a plurality of sacrificial layers and a plurality of first insulating layers that are alternately stacked in sequence; 形成沿所述第一方向贯穿所述叠层结构、所述隔离层且延伸至所述基底中的沟道孔；A channel hole is formed that penetrates the stacked structure and the isolation layer along the first direction and extends into the substrate; 填充所述沟道孔的侧壁，形成所述功能层；The sidewalls of the channel holes are filled to form the functional layer; 形成覆盖所述功能层的所述沟道层。The channel layer is formed to cover the functional layer. 9.根据权利要求8所述的方法，其特征在于，所述方法还包括：9. The method according to claim 8, characterized in that the method further comprises: 在形成所述沟道层后，形成沿所述第一方向贯穿所述叠层结构、所述隔离层且延伸至所述基底中的沟槽；After the trench layer is formed, a trench is formed that penetrates the stacked structure and the isolation layer along the first direction and extends into the substrate; 基于所述沟槽，去除所述叠层结构中的所述多个牺牲层，以在相邻所述第一绝缘层之间形成间隙；Based on the trench, the plurality of sacrificial layers in the stacked structure are removed to form a gap between adjacent first insulating layers; 填充所述间隙，形成多个第一导电层。The gaps are filled to form a plurality of first conductive layers. 10.根据权利要求9所述的方法，其特征在于，所述方法还包括：10. The method according to claim 9, wherein the method further comprises: 在形成所述多个第一导电层之前，在所述间隙内和所述沟槽内，形成覆盖所述第一绝缘层和所述间隙显露的所述功能层的介电层；其中，所述介电层，位于所述第一导电层和所述绝缘层之间，且位于所述第一导电层和所述功能层之间。Before forming the plurality of first conductive layers, a dielectric layer is formed within the gap and the trench, covering the first insulating layer and the functional layer exposed by the gap; wherein the dielectric layer is located between the first conductive layer and the insulating layer, and between the first conductive layer and the functional layer.
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