CN113810070B - Signal transmission device capable of transmitting multiple sets of data streams - Google Patents

Abstract

The disclosure provides a signal transmission device, which includes multiple positive differential pins, multiple negative differential pins, multiple ground pins, multiple power signal pins and multiple control signal pins. The first positive differential pin in the plurality of positive differential pins transmits the positive signal component of the first differential signal, and the second positive differential pin in the multiple positive differential pins transmits the positive signal component of the second differential signal; The first negative differential pin of the negative differential pins transmits the negative signal component of the first differential signal, and the second negative differential pin of the plurality of negative differential pins transmits the negative signal component of the second differential signal; the first positive differential pin transmits the negative signal component of the second differential signal; The pin and the first negative differential pin are located on one side of the first ground pin among the plurality of ground pins, and the second positive differential pin and the second negative differential pin are located on the other side of the first ground pin.

Description

Signal transmission device capable of transmitting multiple sets of data streams

technical field

The invention relates to a signal transmission device capable of transmitting multiple groups of data streams.

Background technique

With the higher and higher requirements for the quality of the video playback screen, the original 4K has been upgraded to 8K resolution, so it is transmitted from the player as the signal source (Signal Source) to the display as the signal sink (Signal Sink), etc. The amount of data transfer required also increases. Moreover, due to the rise of home theaters, it is often necessary to use longer transmission lines to connect signal generators and signal receivers to meet the needs of various living room arrangements.

In the current signal transmission device specification, if we look at the definition of the pin position, the ground shielding (Ground Shielding) that is important to the differential signal is not the best planning method, which makes the signal quality easy to be affected when transmitting high-speed signals. Due to the effects of Crosstalk and Delay, it is difficult to transmit to a longer distance.

Contents of the invention

In some embodiments, a signal transmission device includes a plurality of positive differential pins, a plurality of negative differential pins, a plurality of ground pins, a plurality of power signal pins and a plurality of control signal pins. The first positive differential pin among the multiple positive differential pins is used to transmit the positive signal component of the first differential signal, and the second positive differential pin among the multiple positive differential pins is used to transmit the positive signal of the second differential signal component; the first negative differential pin among the multiple negative differential pins is used to transmit the negative signal component of the first differential signal, and the second negative differential pin among the multiple negative differential pins is used to transmit the negative signal component of the second differential signal Negative signal component; wherein, the first positive differential pin and the first negative differential pin are located on one side of the first ground pin among the plurality of ground pins, and the second positive differential pin and the second negative differential pin are located on the other side of the first ground pin.

Description of drawings

FIG. 1 is a schematic diagram of an embodiment of a signal transmission device according to the disclosure.

FIG. 2 is a schematic diagram of another embodiment of the signal transmission device in FIG. 1 .

FIG. 3 is a schematic diagram of an embodiment of a pin arrangement of a signal transmission device according to the present disclosure.

FIG. 4 is a schematic diagram of an embodiment of a pin arrangement of a signal transmission device according to the present disclosure.

FIG. 5A is a schematic diagram of an appearance of an embodiment of a female connector of a signal transmission device according to the present disclosure.

FIG. 5B is a schematic appearance diagram of an embodiment of a male connector of the signal transmission device corresponding to FIG. 5A .

FIG. 5C is a schematic side view of an embodiment of the signal transmission device in FIG. 5A .

FIG. 5D is a schematic side view of an embodiment of the signal transmission device shown in FIG. 5B .

6A is a schematic side view of another embodiment of a female connector of a signal transmission device according to the present disclosure.

FIG. 6B is a schematic side view of another embodiment of the male connector of the signal transmission device corresponding to FIG. 6A .

7A is a schematic side view of another embodiment of a female connector of a signal transmission device according to the present disclosure.

FIG. 7B is a schematic side view of another embodiment of the male connector of the signal transmission device corresponding to FIG. 7A .

FIG. 8 is a schematic diagram of an embodiment of a transmission line including a signal transmission device and an electronic device according to the present disclosure.

FIG. 9 is a schematic diagram of another embodiment of a signal transmission device according to the present disclosure.

FIG. 10 is a schematic diagram of another embodiment of the signal transmission device in FIG. 9 .

Symbol Description

111: The first positive differential pin

112: First negative differential pin

121: Second positive differential pin

122: Second negative differential pin

131: The third positive differential pin

132: The third negative differential pin

141: The fourth positive differential pin

142: Fourth negative differential pin

151: The first positive differential high-speed pin

152: The first negative differential high-speed pin

161: The second positive differential high-speed pin

162: The second negative differential high-speed pin

171: Seventh positive differential pin

172: Seventh negative differential pin

181: Eighth positive differential pin

182: Eighth negative differential pin

191: Ninth positive differential pin

192: Ninth negative differential pin

101: Tenth positive differential pin

102: Tenth negative differential pin

21: First ground pin

22: Second ground pin

23: The third ground pin

24: Fourth ground pin

25: Fifth ground pin

26: The sixth ground pin

27: Seventh ground pin

28: Eighth ground pin

29: The ninth ground pin

20: Tenth ground pin

31: Power signal pin

32: Power signal pin

33: Power signal pin

34: Power signal pin

410: System main power supply pin

411: Hot plug detection pin

412: SDA/PCIE_PERST_N pin

413: CLK pin

414: SCL/PCIE_WAKE_N pin

415: ARC/SPDIF pin

416: SPI_DI pin

417: SPI_CS pin

418: SPI_CLK pin

419: REALONE_SCL pin

420: REALONE_SDA pin

421: SPI_WP_PWM pin

422: SPI_HOLD_PWM pin

423: SPI_DO pin

51: Positive differential low-speed pin

52: Negative differential low-speed pin

61: Power ground pin

62: Power ground pin

I: insulating layer

M: metal isolation layer

D1: Direction

D2: direction

G1: wire

G2: wire

G3: wire

G4: wire

SA: one side

SB: one side

A: terminal

A': end

B: side

B': end

C: end

C': terminal

D: side

D': end

E: end

E': end

F: side

F': end

P: signal transmission device

Q: Signal transmission device

R: signal transmission device

L: connecting part

N: electronic device

detailed description

Please refer to FIG. 1 , which is a schematic diagram of an embodiment of a signal transmission device according to the present disclosure. The signal transmission device includes multiple positive differential pins, multiple negative differential pins, multiple control signal pins, multiple power signal pins and multiple ground pins. Among them, the number of positive differential pins, the number of negative differential pins, the number of ground pins, the number of power signal pins and the number of control signal pins can be adjusted according to different product requirements (such as required current size, signal transmission rate, etc.) ) for customized design, FIG. 1 is only an example of one embodiment of the signal transmission device, and the present disclosure is not limited thereto.

Figure 1 illustrates multiple positive differential pins 111, 121, 131, 141, multiple negative differential pins 112, 122, 132, 142 and corresponding differential pins 111, 112, 121, 122, 131, 132, 141 , 142 a plurality of ground pins (GND) 21-25. Positive differential pins 111, 121, 131, 141 and negative differential pins 112, 122, 132, 142 respectively transmit the positive signal component and negative signal component of the differential signal, here the positive differential pins 111, 121 (for convenience) Description, respectively referred to as the first positive differential pin 111 and the second positive differential pin 121), negative differential pins 112, 122 (respectively referred to as the first negative differential pin 112 and the second negative differential pin 122) and The corresponding ground pin 21 (hereinafter referred to as the first ground pin 21 ) is described as an example.

The first positive differential pin 111 and the first negative differential pin 112 transmit the first differential signal, wherein the first positive differential pin 111 transmits the positive signal component of the first differential signal, and the first negative differential pin 112 transmits the first The negative signal component of the differential signal; the second positive differential pin 121 and the second negative differential pin 122 transmit another differential signal (hereinafter referred to as the second differential signal) different from the first differential signal, and the second positive differential pin The pin 121 transmits the positive signal component of the second differential signal, and the second negative differential pin 122 transmits the negative signal component of the second differential signal. In terms of configuration, the first positive differential pin 111 and the first negative differential pin 112 are located on one side of the first ground pin 21 (that is, the two differential pins 111, 112 that transmit the same differential signal are located on the first ground pin 21). pin 21 on the same side), the second positive differential pin 121 and the second negative differential pin 122 are located on the other side of the first ground pin 21 (that is, the two differential pins 121, 122 that transmit the same differential signal are located on the same side of the first ground pin 21 ), that is, the two differential pins 111 and 122 transmitting different differential signals are located on different sides of the first ground pin 21 .

Furthermore, FIG. 1 illustrates four power signal pins 31 - 34 and multiple control signal pins. The power signal pins 31-34 can transmit power signals conforming to specific communication specifications, and the control signal pins can transmit control signals conforming to specific communication specifications. power signal and control signal, and meet specific communication specifications. Based on this, different from the existing signal transmission device, the signal transmission device of the present disclosure can avoid crosstalk between different differential signals when transmitting the first differential signal and the second differential signal, and obtain better impedance Matching characteristics, so the transmission quality of the signal transmission device is improved, and the signal can be transmitted to the electronic device more efficiently.

In some embodiments, as shown in FIG. 1, the signal transmission device can transmit at least four pairs of differential signals, the third positive differential pin 131 and the third negative differential pin 132 can transmit the third differential signal, the third positive differential pin The pin 131 transmits the positive signal component of the third differential signal, the third negative differential pin 132 transmits the negative signal component of the third differential signal, and the fourth positive differential pin 141 and the fourth negative differential pin 142 can transmit the fourth differential signal , the fourth positive differential pin 141 transmits the positive signal component of the fourth differential signal, and the fourth negative differential pin 142 transmits the negative signal component of the fourth differential signal. In order to prevent the above four pairs of differential signals from interfering with each other, as shown in FIG. , the fourth ground pin 24 and the fifth ground pin 25 . The second positive differential pin 121 and the second negative differential pin 122 are located between the first ground pin 21 and the fourth ground pin 24, that is, the second positive differential pin 121 and the second negative differential pin 122 are located at the first ground pin 21 and the fourth ground pin 24. One side of the four ground pins 24, the third positive differential pin 131 and the third negative differential pin 132 are located on the other side of the fourth ground pin 24; the third positive differential pin 131 and the third negative differential pin 132 is located between the fourth ground pin 24 and the fifth ground pin 25, that is, the third positive differential pin 131 and the third negative differential pin 132 are located on one side of the fifth ground pin 25, and the fourth positive differential pin The pin 141 and the fourth negative differential pin 142 are located on the other side of the fifth ground pin 25 . Based on this, the second positive differential pin 121 and the third negative differential pin 132 are shielded by the fourth ground pin 24, and the third positive differential pin 131 and the fourth negative differential pin 142 are shielded by the fifth ground pin 142. The pin 25 is shielded, and the first differential signal, the second differential signal, the third differential signal and the fourth differential signal do not interfere with each other.

In some embodiments, a plurality of positive differential pins 111, 121, 131, 141 and a plurality of negative differential pins 112, 122, 132, 142 are along the same linear direction D1 (for example, the length direction of the signal transmission device) Arranged, the signal transmission device can be more easily compatible with existing communication transmission standards.

In some embodiments, please refer to FIG. 2, which is a schematic diagram of another embodiment of the signal transmission device in FIG. 1. The signal transmission device may also include eight pairs of differential pins, and each pair of differential pins that transmit the same differential signal pin is shielded by two ground pins. The signal transmission device also includes positive differential pins 171, 181, 191, 101 (hereinafter respectively referred to as the seventh positive differential pin 171, the eighth positive differential pin 181, the ninth positive differential pin 191 and the tenth positive differential pin). pin 101), negative differential pins 172, 182, 192, 102 (hereinafter respectively referred to as the seventh negative differential pin 172, the eighth negative differential pin 182, the ninth negative differential pin 192 and the tenth negative differential pin 102) and the corresponding ground pins 26, 27, 28, 29. The positive differential pins 171 , 181 , 191 , 101 and the negative differential pins 172 , 182 , 192 , 102 are also arranged along the same straight line direction D1. The seventh positive differential pin 171 and the seventh negative differential pin 172 can transmit the seventh differential signal, the seventh positive differential pin 171 transmits the positive signal component of the seventh differential signal, and the seventh negative differential pin 172 transmits the seventh differential signal The negative signal component of the signal. The eighth positive differential pin 181 and the eighth negative differential pin 182 can transmit the eighth differential signal, the eighth positive differential pin 181 transmits the positive signal component of the eighth differential signal, and the eighth negative differential pin 182 transmits the eighth differential signal The negative signal component of the signal. The ninth positive differential pin 191 and the ninth negative differential pin 192 can transmit the ninth differential signal, the ninth positive differential pin 191 transmits the positive signal component of the ninth differential signal, and the ninth negative differential pin 192 transmits the ninth differential signal The negative signal component of the signal. The tenth positive differential pin 101 and the tenth negative differential pin 102 can transmit the tenth differential signal, the tenth positive differential pin 101 transmits the positive signal component of the tenth differential signal, and the tenth negative differential pin 102 transmits the tenth differential signal The negative signal component of the signal.

In order to prevent mutual interference between the aforementioned eight differential signals, as shown in FIG. 2, the fourth positive differential pin 141 and the fourth negative differential pin 142 are located between the fifth ground pin 25 and the sixth ground pin 26. Between, that is, the fourth positive differential pin 141 and the fourth negative differential pin 142 are located on one side of the sixth ground pin 26, and the seventh positive differential pin 171 and the seventh negative differential pin 172 are located on the sixth ground pin The other side of 26; the seventh positive differential pin 171 and the seventh negative differential pin 172 are located between the sixth ground pin 26 and the seventh ground pin 27, that is, the seventh positive differential pin 171 and the seventh negative differential pin 172 The differential pin 172 is located on one side of the seventh ground pin 27, the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on the other side of the seventh ground pin 27; the eighth positive differential pin 181 and The eighth negative differential pin 182 is located between the seventh ground pin 27 and the eighth ground pin 28, that is, the eighth positive differential pin 181 and the eighth negative differential pin 182 are located on one side of the eighth ground pin 28 , the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on the other side of the eighth ground pin 28; the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on the eighth ground pin 28 and the ninth ground pin 29, that is, the ninth positive differential pin 191 and the ninth negative differential pin 192 are located on one side of the ninth ground pin 29, the tenth positive differential pin 101 and the tenth negative differential pin The pin 102 is located on the other side of the ninth ground pin 29 . Based on this, the fourth positive differential pin 141 and the seventh negative differential pin 172 are shielded by the sixth ground pin 26, and the seventh positive differential pin 171 and the eighth negative differential pin 182 are shielded by the seventh ground pin 26. Pin 27 is shielded, the eighth positive differential pin 181 and the ninth negative differential pin 192 are shielded by the eighth grounding pin 28, and the ninth positive differential pin 191 and the tenth negative differential pin 102 are shielded by the eighth ground pin 102. Nine grounding pins 29 are shielded, the first differential signal, the second differential signal, the third differential signal, the fourth differential signal, the seventh differential signal, the eighth differential signal, the ninth differential signal and the tenth differential signal are not mutually interference. Based on this, the signal transmission device can transmit at least eight pairs of differential signals, and the eight pairs of differential pins are arranged along the same straight line direction D1, and the signal transmission device can be more easily compatible with existing communication transmission specifications.

In some embodiments, as shown in FIG. 1 and FIG. 2 , one side of the third ground pin 23 among the plurality of ground pins (that is, the side away from the first negative differential pin 112 ) is not provided with Positive differential pins and negative differential pins can be provided with power signal pins 31, 32, and the other side of the third ground pin 23 is the first positive differential pin 111 and the first negative differential pin 112, That is, the first positive differential pin 111 and the first negative differential pin 112 are located between the first ground pin 21 and the third ground pin 23, and the first positive differential pin 111 and the first negative differential pin 112 are controlled by two The two ground pins 21, 23 are shielded, and the ground pins 21, 23 can jointly provide the first differential signal ground. Based on this, the setting of the third ground pin 23 separates the first positive differential pin 111 and the first negative differential pin 112 from a plurality of power signal pins 31, 32, thus preventing the first positive differential pin 111 and the first negative differential pin 112 from The first negative differential pin 112 is interfered by the power signal when transmitting the first differential signal, which causes the transmission quality of the first differential signal to degrade.

In some embodiments, as shown in FIG. 2 , the second ground pin 22 is located at the edge of the signal transmission device, that is, one side of the second ground pin 22 in the linear direction D1 is not provided with a positive differential pin and the negative differential pin, the other side of the second ground pin 22 in the straight line direction D1 is the tenth positive differential pin 101 and the tenth negative differential pin 102 . That is, the tenth positive differential pin 101 and the tenth negative differential pin 102 are located between the ninth ground pin 29 and the second ground pin 22, and the tenth positive differential pin 101 and the tenth negative differential pin 102 are influenced by two The ground pins 29 and 22 are shielded, that is, the ground pins 29 and 22 can jointly provide the tenth differential signal ground. Based on this, it can be further avoided that the tenth positive differential pin 101 and the tenth negative differential pin 102 are interfered by noise outside the signal transmission device when transmitting the tenth differential signal, which causes the transmission quality of the tenth differential signal to degrade.

In some embodiments, as shown in FIG. 2 , the multiple differential pins of the signal transmission device also include two positive differential pins 151, 161 and two negative differential pins 152, 162 (hereinafter referred to as positive differential pin 151 161 are respectively called the first positive differential high-speed pin 151 and the second positive differential high-speed pin 161, and the negative differential pins 152 and 162 are respectively called the first negative differential high-speed pin 152 and the second negative differential high-speed pin 152. pin 162), and the plurality of ground pins of the signal transmission device also includes the tenth ground pin 20. The first positive differential high-speed pin 151 is used to transmit the positive signal component of the fifth differential signal, the first negative differential high-speed pin 152 is used to transmit the negative signal component of the fifth differential signal; the second positive differential high-speed pin 161 is used for The positive signal component of the sixth differential signal is transmitted, and the second negative differential high-speed pin 162 is used for transmitting the negative signal component of the sixth differential signal. In terms of configuration, the first positive differential high-speed pin 151 and the first negative differential high-speed pin 152 are located on one side of the tenth ground pin 20, and the second positive differential high-speed pin 161 and the second negative differential high-speed pin 162 are located on the side of the tenth ground pin 20. On the other side of the tenth ground pin 20 , the positive differential high-speed pins 151 and 161 , the tenth ground pin 20 and the negative differential high-speed pins 152 and 162 are arranged along the same straight line direction D1.

In some embodiments, the multiple positive differential pins and multiple negative differential pins of the signal transmission device are used to transmit high-speed data signals, for example, the first differential signal transmitted by the differential pins 111, 112, the differential pins 121, 122 The second differential signal transmitted, the third differential signal transmitted by differential pins 131, 132, the fourth differential signal transmitted by differential pins 141, 142, the seventh differential signal transmitted by differential pins 171, 172, differential pin 181 , the eighth differential signal transmitted by 182, the ninth differential signal transmitted by differential pins 191 and 192, the tenth differential signal transmitted by differential pins 101 and 102, the fifth differential signal and differential signal transmitted by differential high-speed pins 151 and 152 Both the sixth differential signals transmitted by the high-speed pins 161 and 162 are high-speed data signals. And, as shown in Figure 1 and Figure 2, the signal transmission device can also include positive differential low-speed pins 51 and negative differential low-speed pins 52 for transmitting low-speed data signals, and the positive differential low-speed pins 51 and negative differential low-speed pins 52 The differential high-speed pins 151, 152, 161, 162 are arranged along the same straight line direction D1. The positive differential low-speed pin 51 and the negative differential low-speed pin 52 transmit low-speed differential signals as low-speed data, the positive differential low-speed pin 51 transmits the positive signal component of the low-speed differential signal, and the negative differential low-speed pin 52 transmits the negative signal of the low-speed differential signal portion. Based on this, the signal transmission device can simultaneously support the transmission of high-speed data signals and low-speed data signals.

In some embodiments, the signal transmission device illustrated in FIGS. 1 to 2 can support the specification of Universal Serial Bus (Universal Serial Bus; USB) 2.0, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are suitable for USB2.0. Specifications, the low-speed differential signals transmitted by the positive differential low-speed pin 51 and the negative differential low-speed pin 52 are USB2.0 USB signals, the positive differential low-speed pin 51 can transmit USB-DP signals, and the negative differential low-speed pin 52 can transmit USB -DM signal. Moreover, the signal transmission device illustrated in FIG. 2 can also support various specifications using differential transmission methods. In the signal transmission device, multiple positive differential pins and multiple negative differential pins (that is, differential Any two pairs of pins 111, 112, 121, 122, 131, 132, 141, 142, 171, 172, 181, 182, 191, 192, 101, 102 and differential high-speed pins 151, 152, 161, 162) Differential pins can transmit high-speed data transmission and reception signals that comply with USB 2.0 or PCIe 1.0 and later versions, or other differential transmission methods.

In some embodiments, the signal transmission device illustrated in FIGS. 1 to 2 can also support the specification of the PCIe interface, wherein, the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the second A negative differential high-speed pin 152, a second positive differential high-speed pin 161, and a second negative differential high-speed pin 162 are also applicable to the transmission of the PCIe interface, and the positive differential low-speed pin 51 and the negative differential low-speed pin 52 can transmit A clock signal conforming to the PCIe interface specification (may include a positive clock component and a negative clock component).

In some embodiments, the signal transmission device can support High Definition Multimedia Interface (High DefinitionMultimedia Interface; HDMI), as shown in Figure 1 and Figure 2, the aforementioned multiple control signal pins can be multiple SCL pins, multiple The SDA pin and the hot plug detection (Hot Plug Detection) pin 411 may be selected from a combination formed by the aforementioned items. Multiple SCL pins are SCL/PCIE_WAKE_N pins 414 and REALONE_SCL pins 419 for transmitting SCL (Serial Clock) signals; multiple SDA pins are SDA/PCIE_PERST_N pins for transmitting SDA (Serial Data) signals pin 412 and REALONE_SDA pin 420 . The SCL pin and the SDA pin can be used for communication between the signal generating source (such as Digital Video Disc, or DVD) device and the signal receiving end (such as television, or TV) device, and the source device reads through the SCL pin and the SDA pin. Get the resolution supported by the playback device, so that the source device displays an image screen that matches the resolution of the playback device. Moreover, the four pairs of differential pins in the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101 and the negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 can be used in total. Three pairs of Transition Minimized Differential Signaling (TMDS) and one pair of clock signals suitable for HDMI specifications are transmitted to support the transmission of HDMI signals.

In some embodiments, the multiple control signal pins of the signal transmission device can be ARC (Audio Return Channel)/SPDIF pin 415, CLK (AUDIO-SYNC clock) pin 413, multiple serial peripheral interface (SPI) Pins or combinations formed from the aforementioned items to transmit voice and video related control signals between electronic devices, wherein a plurality of pins suitable for SPI include SPI_DI pin 416, SPI_CS pin 417, SPI_WP_PWM pin Pin 421 , SPI_DO pin 423 , SPI_HOLD_PWM pin 422 and SPI_CLK pin 418 .

In some embodiments, one of the multiple control signal pins of the signal transmission device may be the system main power pin 410, and the system main power pin 410 is used to transmit a control signal for turning on or off whether the external device provides power ( Or called enabling signal), for example, the signal transmission device can be connected between the notebook computer and the tablet computer, the tablet computer can be regarded as an external device of the notebook computer, and the tablet computer has a power supply function that can supply power to the notebook computer, The system main power supply pin 410 can transmit a control signal to enable or disable the aforementioned power supply function. In terms of configuration, the main power supply pin 410 of the system is located at the positive differential low-speed pin 51, the negative differential low-speed pin 52, the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, and the second positive differential high-speed pin 161 , between the second negative differential high-speed pins 162 to isolate the transmission of low-speed data signals and high-speed data signals. In some embodiments, the aforementioned plurality of control signal pins are arranged along the same straight line direction D1.

In some embodiments, the power signal pins 31-34 can be multiple low-voltage power pins and multiple high-voltage power pins, wherein the power signal pins 31, 32 are low-voltage power pins, that is, HV-POWER power pins Pins, power signal pins 31, 32 supply low-voltage power signals related to HV, and its voltage can be 12 volts (V); power signal pins 33, 34 are high-voltage power pins, that is, UHV-POWER power pins, power The signal pins 33 and 34 supply high voltage power signals related to the UHV, and the voltage may be 350V. In some embodiments, the number of the multiple low-voltage power supply pins and the multiple high-voltage power supply pins can be adjusted according to the actual conduction current of the signal transmission device and the differential signal transmission rate.

In some embodiments, as shown in FIG. 1 and FIG. 2, multiple ground pins of the signal transmission device can provide power signal ground, that is, the power ground pins 61, 62 of the multiple ground pins can provide The power signal pins 33 and 34 of the high-voltage power supply pins are used for grounding, and the power signal pins 33 and 34 and the power ground pins 61 and 62 are arranged along the same straight line direction D1. Moreover, the signal transmission device also includes an insulating layer 1, and the insulating layer 1 is located between the power signal pins 33, 34 and the power ground pins 61, 62 of the multiple ground pins that supply the power signal pins 33, 34 to ground, That is to say, the power signal pins 33 and 34 which are UHV-POWER pins are located on one side of the insulating layer I, and the power grounding pins 61 and 62 are located on the other side of the insulating layer I. Therefore, providing an insulating layer I between the power signal pins 33, 34 and the power ground pins 61, 62 can prevent arcing or damage to the signal transmission device due to excessive cross-voltage.

In some embodiments, please refer to FIG. 1 and FIG. 2 , the signal transmission device is provided with a metal isolation layer M as an isolation between the electrical structure and the physical structure (between multiple pins of the signal transmission device). In detail, as shown in Fig. 1 and Fig. 2, power signal pins 31, 32, positive differential pins 111, 121, 131, 141, 171, 181, 191, 101 and negative differential pins 112, 122, 132 . , negative differential low-speed pin 52, first positive differential high-speed pin 151, first negative differential high-speed pin 152, tenth ground pin 20, second positive differential high-speed pin 161, second negative differential high-speed pin 162 , a plurality of control signal pins, power signal pins 33, 34, power ground pins 61, power ground pins 62 and insulating layer I are located on the other side of the metal isolation layer M in direction D2, and direction D2 is perpendicular to Direction D1 (for example, direction D2 may be the length direction of the signal transmission device), in other words, positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, negative differential pins 112, 122, 132, 142 , 172, 182, 192, 102 and the positive differential low-speed pin 51, the negative differential low-speed pin 52 are arranged in parallel along the direction D2 through the metal isolation layer M; the positive differential pins 111, 121, 131, 141, 171, 181, 191, 101, negative differential pins 112, 122, 132, 142, 172, 182, 192, 102 and the first positive differential high-speed pin 151, the first negative differential high-speed pin 152, the second positive differential The high-speed pin 161 and the second negative differential high-speed pin 162 are arranged side by side along the direction D2 through the metal isolation layer M; Between the differential pins 112, 122, 132, 142, 172, 182, 192, 102 and a plurality of control signal pins, the metal isolation layer M is arranged in parallel along the direction D2; the power signal pins 31, 32 are connected to the power supply The signal pins 33 and 34 are arranged in parallel along the direction D2 through the metal isolation layer M. In some embodiments, the metal isolation layer M can be an iron sheet, and can provide a signal ground. Based on this, the metal isolation layer M can prevent the pins on both sides from interfering with each other, and provide a good reference ground plane to enhance the signal quality and impedance matching characteristics, and double-row parallel pins can also reduce the size of the signal transmission device And improve the convenience of production.

In some embodiments, please refer to FIG. 1 , FIG. 2 and FIG. 3 , all pins of the signal transmission device may be formed by winding a core wire (line) and arranged in the same linear direction. For example, as shown in Figure 3, the wire G1 can be a twisted pair with a shielded ground pin, the wire G2 can be a twisted pair without a shielded ground pin, and the wire G3 can be a thin single-core wire and The wire G4 can be a thick single-core wire, and all the pins of the signal transmission device can be bundled into wire G1 , wire G2 , wire G3 , and wire G4 respectively and arranged in the same linear direction. In some other embodiments, as shown in Figure 4, the wires G1-G4 can also be a bundle of winding wires wrapped in a ring shape, that is, the wires G1, G2, G3, and G4 may not be arranged on the same straight line direction.

In some embodiments, the signal transmission device includes a casing. The signal transmission device can be designed as one of a male connector or a female connector, the male connector and the female connector correspond to each other, and the signal transmission device as a male connector can be connected with the signal transmission device as a female connector. Please refer to Fig. 5A to Fig. 5D, Fig. 5A and Fig. 5B are respectively the embodiments of the female connector and the male connector, Fig. 5C is a schematic side view of one side SA of the signal transmission device in Fig. 5A, Fig. 5D is the signal transmission in Fig. 5B Schematic side view of one side SB of the device. As shown in Figure 5C and Figure 5D, the A end and the A' end are designed as beveled angles, and the B end and B' end are also designed as beveled angles. A-end to A' end and B-end to B'-end are interconnected, and the chamfered corners act as a fool-proof mechanism to prevent incorrect coupling of male and female connectors. In some other embodiments, the housing includes a chamfered angle and a right angle, and the chamfered angle and the right angle are respectively located on two sides of the housing. Please refer to FIG. 6A and FIG. 6B. FIG. 6A is another schematic diagram of a signal transmission device as a female connector, and FIG. 6B is another schematic diagram of a signal transmission device as a male connector. As shown in Figure 6A and Figure 6B, the C-end and C'end are designed as right angles, and the D-end and D'end are designed as beveled angles. Therefore, the two signal transmission devices that are respectively used as female connectors and male connectors can The C' end and the D end are connected to the D' end. In some other embodiments, please refer to FIG. 7A and FIG. 7B. FIG. 7A is another schematic diagram of a signal transmission device serving as a female connector, and FIG. 7B is another schematic diagram of a signal transmission device serving as a male connector. As shown in Figure 7A and Figure 7B, the E end and E' end are designed as beveled angles, and the F end and F' end are designed as right angles. The E' end and the F end are connected to the F' end. Based on this, the signal transmission device can provide a combination of signal transmission devices on different products according to different beveled angles of the connectors and separate the connectors of the signal transmission device to prevent the possibility of misconnection between the male connector and the female connector.

In some embodiments, please refer to FIG. 8 , which illustrates a transmission line and an electronic device N suitable for the transmission line. The transmission line includes signal transmission devices P, Q and a connection part L. The signal transmission devices P and Q are arranged at both ends of the transmission line, and the connection part L is connected between the signal transmission device P and the signal transmission device Q. The electronic device N includes a signal transmission device R corresponding to the signal transmission devices P and Q of the transmission line. Since the signal transmission devices P, Q, and R are respectively designed as one of a male connector or a female connector, the male connector can be connected with the female connector, therefore, the signal transmission device P or the signal transmission device Q can be connected with the electronic device N connected to the signal transmission device R, and the electronic device N can be a notebook computer, a mobile phone, a tablet, a monitor or other audio-visual related devices. For example, when the signal transmission device Q as a male connector is connected to the signal transmission device R as a female connector, and the signal transmission device P as a female connector is connected to the signal transmission device as a male connector of another electronic device, Another electronic device can send a signal from the signal transmission device P of the transmission line to the electronic device N through the connection part L, and then to the electronic device N via the signal transmission device Q and the signal transmission device R.

In some embodiments, the total number of pins is 52, as shown in Figure 2 (from top to bottom and from left to right) with the insulating layer 1 not being designed as a pin form, the 1st, 4th, 7th , 10, 13, 16, 19, 22, 25, 33, 49, 50 pins are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21、23、24引脚分别为P3_RTK1_P、P3_RTK1_M、P3_RTK0_P、P3_RTK0_M、P2_RTK1_P、P2_RTK1_M、P2_RTK0_P、P2_RTK0_M、P1_RTK1_P、P1_RTK1_M、P1_RTK0_P、P1_RTK0_M、P0_RTK1_P、P0_RTK1_M、P0_RTK0_P、P0_RTK0_M；第26、27引脚为HV_POWER； Pins 51 and 52 are UHV_POWER; pins 28-32 and 34-48 are USB_DM/REFCLK_M_PCIE, USB_DP/REFCLK_P_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSRX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSON, USB_SSTX_P/DEPCIE_PLTEG, APCIE_SDOP /PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, ARC/SPDIF, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO. Among them, the outer side of the first pin and the 28th pin is the panel (Panel) end.

In some embodiments, the total number of pins is 52, as shown in Fig. 9 (from top to bottom and from left to right) with the insulating layer 1 not being designed as a pin form. , 10, 13, 16, 19, 22, 25, 33, 49, 50 pins are GND; pins 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21、23、24引脚分别为P0_RTK0_M、P0_RTK0_P、P0_RTK1_M、P0_RTK1_P、P1_RTK0_M、P1_RTK0_P、P1_RTK1_M、P1_RTK1_P、P2_RTK0_M、P2_RTK0_P、P2_RTK1_M、P2_RTK1_P、P3_RTK0_M、P3_RTK0_P、P3_RTK1_M、P3_RTK1_P；第26、27引脚为HV_POWER； Pins 51 and 52 are UHV_POWER; pins 28-32 and 34-48 are USB_DP/REFCLK_P_PCIE, USB_DM/REFCLK_M_PCIE, SYSTEM_MAIN_POWER_EN, USB_SSTX_P/PCIE_HSIP, USB_SSTX_M/PCIE_HSIN, USB_SSRX_P/PCIE_HSOP, USB_SSRX_M/ADPCIE_HSTEU, HOSD /PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, ARC/SPDIF, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO. Wherein, the outer side of the first pin and the 28th pin is a system-on-a-chip (SOC) terminal.

In some embodiments, the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 31-35th pins can be unused according to the design of FIG. The total quantity is 35. That is, as shown in Figure 1, pins 1, 4, 7, 10, 13, 32, and 33 are GND; pins 2, 3, 5, 6, 8, 9, 11, and 12 are P1_RTK1_P, P1_RTK1_M, P1_RTK0_P, P1_RTK0_M, P0_RTK1_P, P0_RTK1_M, P0_RTK0_P, P0_RTK0_M; pins 14 and 15 are HV_POWER; pins 34 and 35 are UHV_POWER; pins 16-31 are USB_DM/REFCLK_M_PCIE, USB_DP/REFCLEINWER, USB_DP/EMFCLEINWER, STP HOT_PLUG_DETECT, SDA/PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, ARC/SPDIF, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO. Among them, the outer side of the 16th pin is the panel (Panel) end.

In some embodiments, the 1st, 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 9th, 10th, 11th, 12th, 31-35th pins can be unused according to the design of FIG. The total quantity is 35. That is, as shown in Figure 10, pins 1, 4, 7, 10, 13, 32, and 33 are GND; pins 2, 3, 5, 6, 8, 9, 11, and 12 are P0_RTK0_M, P0_RTK0_P, P0_RTK1_M, P0_RTK1_P, P1_RTK0_M, P1_RTK0_P, P1_RTK1_M, P1_RTK1_P; pins 14 and 15 are HV_POWER; pins 34 and 35 are UHV_POWER; pins 16-31 are USB_DP/REFCLK_P_PCIE, USB_DM/REFCLEINWER, USB_DM/EMFCLK_M HOT_PLUG_DETECT, SDA/PCIE_PERST_N, AUDIO_SYNC_CLK, SCL/PCIE_WAKE_N, ARC/SPDIF, SPI_DI, SPI_CS, SPI_CLK, REALONE_SCL, REALONE_SDA, SPI_WP_PWM, SPI_HOLD_PWM, SPI_DO. Wherein, the outer side of the 16th pin is a system-on-a-chip (SOC) end.

In some embodiments, the number of core wires mentioned above can be adjusted according to different applications and embodiments. Taking the number of pins as 52 and all pins are used as an example, the signal transmission device can be formed by winding 50 core wires. Taking the number of pins as 52 and using 35 pins as an example, the signal transmission device can be formed by winding 33 core wires. Users can choose different differential pins and control signal winding combinations according to the types of specifications to be supported, so as to realize the purpose of data transmission.

To sum up, according to an embodiment of the signal transmission device of the present disclosure, the same pair of differential signal pins is arranged between two ground pins, which can avoid signal crosstalk and obtain better impedance matching characteristics. Furthermore, the ground pin is arranged at the edge of the pin accommodation space, which can prevent the differential signal from being interfered by the noise outside the signal transmission device, and reduce the energy transmitted by the differential signal to the outside of the signal transmission device in the form of electromagnetic waves, so as to reduce the Electromagnetic Interference (EMI) to achieve better electromagnetic compatibility (electromagneticcompatibility; EMC) and electrostatic protection (Electro-Static discharge; ESD). Therefore, the signal transmission device improves the transmission quality, and the transmission line can transmit signals to the electronic device more efficiently. Moreover, the signal transmission device can support a variety of existing transmission specifications, such as USB specification, PCIe specification, Display Port specification and HDMI specification, so as to achieve a single signal transmission device to transmit a larger data transmission volume through multiplexing, and the user does not need to A variety of transmission lines supporting different specifications are prepared to improve the convenience of use.

Although the present disclosure has been disclosed as above with the embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present disclosure. Therefore, the present disclosure The scope of protection shall prevail as defined by the claims.

Claims (9)

1. A signal transmission apparatus capable of transmitting a plurality of data streams, comprising:

a first positive differential pin of the positive differential pins is used for transmitting a positive signal component of a first differential signal, and a second positive differential pin of the positive differential pins is used for transmitting a positive signal component of a second differential signal;

a first negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a first differential signal, and a second negative differential pin of the plurality of negative differential pins is used for transmitting a negative signal component of a second differential signal;

a plurality of ground pins;

a plurality of power signal pins; and

a plurality of control signal pins;

wherein, this first positive differential pin and this first negative differential pin are located one side of a first ground pin in a plurality of ground pins, and this second positive differential pin and this second negative differential pin are located the opposite side of this first ground pin, and wherein, a plurality of positive differential pins and a plurality of negative differential pin transmission high-speed data signal, this signal transmission device still contains:

a positive differential low-speed pin for transmitting a positive signal component of a low-speed differential signal; and

and the negative differential low-speed pin is used for transmitting a negative signal component of the low-speed differential signal.

2. The signal transmission device as claimed in claim 1, wherein the second positive differential pin and the second negative differential pin are further located between the first ground pin and a second ground pin of the plurality of ground pins.

3. The signal transmission device according to claim 2, wherein the first positive differential pin and the first negative differential pin are further located between the first ground pin and a third ground pin of the plurality of ground pins.

4. The signal transmission device as claimed in claim 1, wherein a first positive differential high-speed pin of the plurality of positive differential pins is configured to transmit a positive signal component of a fifth differential signal, a first negative differential high-speed pin of the plurality of negative differential pins is configured to transmit a negative signal component of the fifth differential signal, a second positive differential high-speed pin of the plurality of positive differential pins is configured to transmit a positive signal component of a sixth differential signal, and a second negative differential high-speed pin of the plurality of negative differential pins is configured to transmit a negative signal component of the sixth differential signal;

the first positive differential high-speed pin and the first negative differential high-speed pin are located on one side of a tenth grounding pin of the grounding pins, and the second positive differential high-speed pin and the second negative differential high-speed pin are located on the other side of the tenth grounding pin.

5. The signal transmission device according to claim 4, wherein the plurality of control signal pins includes a system main power pin, the system main power pin being located between the positive differential low-speed pin, the negative differential low-speed pin and the first positive differential high-speed pin, the first negative differential high-speed pin, the second positive differential high-speed pin, the second negative differential high-speed pin.

6. The signal transmitting device as claimed in claim 3, wherein the power signal pins are a plurality of low voltage power pins and a plurality of high voltage power pins, the low voltage power pins are used for transmitting low voltage power signals, the high voltage power pins are used for transmitting high voltage power signals, and the third ground pin is located between the low voltage power pins and the first positive differential pin and the first negative differential pin.

7. The signal transmission apparatus of claim 6, further comprising:

a metal isolation layer;

the plurality of positive differential pins, the plurality of negative differential pins and the plurality of low-voltage power supply pins are positioned on one side of the metal isolation layer, the positive differential low-speed pins, the negative differential low-speed pins, the plurality of high-voltage power supply pins and the plurality of control signal pins are positioned on the other side of the metal isolation layer, and the plurality of positive differential pins, the plurality of negative differential pins, the plurality of low-voltage power supply pins and the plurality of control signal pins are arranged in parallel through the metal isolation layer.

8. The signal transmitting device as claimed in claim 7, wherein the first positive differential pin, the first negative differential pin, the second positive differential pin and the second negative differential pin are arranged in parallel with the first positive differential high-speed pin, the first negative differential high-speed pin, the second positive differential high-speed pin and the second negative differential high-speed pin through the metal isolation layer.

9. The signal transmitting device according to claim 1, further comprising a housing for accommodating the positive differential pins, the negative differential pins, the ground pins, the power signal pins, and the control signal pins, wherein the housing comprises a diagonal angle and a straight angle, and the diagonal angle and the straight angle are respectively located at two sides of the housing.

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