CN113257662A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN113257662A CN113257662A CN202110792961.0A CN202110792961A CN113257662A CN 113257662 A CN113257662 A CN 113257662A CN 202110792961 A CN202110792961 A CN 202110792961A CN 113257662 A CN113257662 A CN 113257662A
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Abstract
本发明实施例提供了一种半导体器件及其制作方法，该方法包括：在衬底上依次沉积第一掩膜层和第二掩膜层，对第一掩膜层和第二掩膜层进行刻蚀，形成暴露出衬底的凹槽，在凹槽暴露出的衬底以及第二掩膜层上形成金属层，并去除第一掩膜层、第二掩膜层以及第二掩膜层上的金属层，保留凹槽暴露出的衬底上的金属层。由于第一掩膜层和第二掩膜层是采用沉积工艺制作在衬底上的薄膜层，而并不是光刻胶层，因此，即便后续形成金属层的沉积工艺温度过高，也不会对第一掩膜层和第二掩膜层产生影响，即采用沉积工艺形成的第一掩膜层和第二掩膜层对金属层沉积温度要求不高，从而可以降低金属层的沉积难度。
Embodiments of the present invention provide a semiconductor device and a method for fabricating the same. The method includes: sequentially depositing a first mask layer and a second mask layer on a substrate; etching, forming a groove exposing the substrate, forming a metal layer on the substrate exposed by the groove and the second mask layer, and removing the first mask layer, the second mask layer and the second mask layer on the metal layer, leaving the grooves to expose the metal layer on the substrate. Since the first mask layer and the second mask layer are thin film layers fabricated on the substrate by deposition process, not photoresist layers, even if the subsequent deposition process temperature for forming the metal layer is too high, they will not It affects the first mask layer and the second mask layer, that is, the first mask layer and the second mask layer formed by the deposition process do not have high requirements on the deposition temperature of the metal layer, so that the deposition difficulty of the metal layer can be reduced.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductor integrated circuits, in particular to a semiconductor device and a manufacturing method thereof.
Background
The metal lift-off process is an important process in the field of electronics mechanical systems and integrated circuit processing. The basic flow of the metal stripping process is as follows: a patterned prior art photoresist mask 11 is formed on a prior art substrate 10 as shown in fig. 1, then a prior art metal layer 12 is simultaneously deposited on the prior art substrate 10 and the prior art photoresist mask 11 as shown in fig. 2, and then the prior art metal layer 12 of the prior art photoresist mask 11 and its surface is stripped using conventional photoresist stripping techniques as shown in fig. 3, leaving the prior art metal layer 12 on the prior art substrate 10, thereby forming a patterned prior art metal layer 12 on the prior art substrate 10. However, with this metal lift-off process, it is necessary to ensure that the deposition temperature of the prior art metal layer 12 is not too high, resulting in greater difficulty in depositing the prior art metal layer 12.
Disclosure of Invention
In view of this, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same, so as to solve the problem that the deposition temperature of a metal layer manufactured by the conventional metal lift-off process cannot be too high.
In order to solve the above problems, embodiments of the present invention provide the following technical solutions:
a method for manufacturing a semiconductor device includes:
providing a substrate;
depositing a first mask layer and a second mask layer on the substrate in sequence;
etching the first mask layer and the second mask layer to form a groove exposing the substrate, wherein the width of the groove at the second mask layer is smaller than that of the groove at the first mask layer;
forming a metal layer on the substrate exposed by the groove and the second mask layer;
and removing the first mask layer, the second mask layer and the metal layer on the second mask layer, and reserving the metal layer on the substrate exposed by the groove.
Optionally, under the same etching condition, the etching rate of the second mask layer is less than or equal to the etching rate of the first mask layer, so that the width of the groove at the second mask layer is less than the width of the groove at the first mask layer.
Optionally, the thickness of the first mask layer is greater than the thickness of the metal layer.
Optionally, the etching the first mask layer and the second mask layer includes:
forming a mask on the second mask layer, wherein the mask is provided with an opening for exposing the second mask layer of the area to be etched;
etching part of the mask layer of the area to be etched;
and etching the residual mask layer of the area to be etched to form a groove exposing the substrate.
Optionally, the etching the part of the mask layer of the region to be etched includes:
etching part of the mask layer of the area to be etched by adopting a dry etching process;
etching the residual mask layer of the area to be etched comprises the following steps:
and etching the residual mask layer of the area to be etched by adopting a wet etching process.
Optionally, the removing the first mask layer, the second mask layer, and the metal layer on the second mask layer includes:
and etching the first mask layer and the second mask layer by adopting a wet etching process so as to remove the first mask layer, the second mask layer and the metal layer on the second mask layer.
Optionally, after forming a metal layer on the substrate exposed by the groove and the second mask layer, the method further includes:
and processing the surface of the metal layer by adopting a frequency correction process.
Optionally, the first mask layer and the second mask layer are made of different materials; or, the first mask layer and the second mask layer are made of the same material, but the thicknesses of the first mask layer and the second mask layer are different.
Optionally, the first mask layer and the second mask layer are silicon dioxide layers with different densities.
A semiconductor device fabricated using the method of any one of the above.
The semiconductor device and the manufacturing method thereof provided by the embodiment of the invention have the advantages that the first mask layer and the second mask layer are sequentially deposited on the substrate, then the first mask layer and the second mask layer are etched to form the groove exposing the substrate, then the metal layers are formed on the substrate and the second mask layer exposed by the groove, the metal layers on the first mask layer, the second mask layer and the second mask layer are removed, and the metal layer on the substrate exposed by the groove is reserved, namely, the patterned metal layer is formed on the substrate. Because the first mask layer and the second mask layer are thin film layers made on the substrate by adopting a deposition process, but not photoresist layers, the first mask layer and the second mask layer cannot be influenced even if the temperature of the deposition process for forming a metal layer subsequently is too high, namely, the first mask layer and the second mask layer formed by adopting the deposition process have low requirements on the deposition temperature of the metal layer, so that the deposition difficulty of the metal layer can be reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic cross-sectional view of a step in a method of forming a patterned metal layer;
FIG. 2 is a schematic cross-sectional view of another step in a conventional method for forming a patterned metal layer;
FIG. 3 is a schematic cross-sectional view of a further step in a method of forming a patterned metal layer;
FIG. 4 illustrates a flow chart of a method of fabricating a semiconductor device provided by one embodiment of the present invention;
fig. 5 is a schematic cross-sectional structure diagram illustrating a first step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 6 is a schematic cross-sectional structure diagram illustrating a second step in the method for manufacturing a semiconductor device according to the embodiment of the invention;
fig. 7 is a schematic cross-sectional structure diagram illustrating a third step in the method for manufacturing a semiconductor device according to the embodiment of the invention;
fig. 8 is a schematic cross-sectional view illustrating a sub-step in a third step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 9 is a schematic cross-sectional view illustrating an embodiment of another sub-step of the third step in the method for manufacturing a semiconductor device according to the embodiment of the present invention;
fig. 10 is a schematic cross-sectional view illustrating an embodiment of a further substep of a third step in a method for fabricating a semiconductor device according to an embodiment of the present invention;
fig. 11 is a schematic cross-sectional view illustrating one embodiment of a further substep of a third step in a method for fabricating a semiconductor device according to an embodiment of the present invention;
fig. 12 is a schematic cross-sectional structure diagram illustrating a fourth step in the method for manufacturing a semiconductor device according to the embodiment of the invention;
fig. 13 is a schematic cross-sectional structure diagram illustrating a fifth step in the method for manufacturing a semiconductor device according to the embodiment of the invention.
List of reference numerals
10 a prior art substrate; 11 a prior art photoresist mask; 12 a prior art metal layer; 20 a substrate; 21 a first mask layer; 22 a second mask layer; 23, grooves; 24, masking; 240 opening; 25 a metal layer; the width at the first mask layer 21 of L1; l2 width at the second mask layer 22.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, as shown in fig. 4, the method includes:
s101: providing a substrate;
as shown in fig. 5, in some embodiments of the present invention, the substrate 20 may be a semiconductor substrate, such as a silicon substrate, a silicon germanium substrate, etc., but in other embodiments of the present invention, the substrate 20 may also be a non-semiconductor substrate, such as a glass substrate, etc. Furthermore, in some embodiments of the present invention, the substrate 20 may not have any film layer thereon, but in other embodiments of the present invention, the substrate 20 may have other film layers thereon, such as a buffer layer, etc., i.e., any substrate on which a patterned metal layer is required to be formed, is within the scope of the present invention.
S102: depositing a first mask layer and a second mask layer on a substrate in sequence;
as shown in fig. 6, a first mask layer 21 and a second mask layer 22 are sequentially deposited on a substrate 20, i.e., the first mask layer 21 is deposited on the substrate 20, and then the second mask layer 22 is deposited on the first mask layer 21. It should be noted that the first mask layer 21 and the second mask layer 22 are both thin films formed by a deposition process.
S103: etching the first mask layer and the second mask layer to form a groove exposing the substrate, wherein the width of the groove at the second mask layer is smaller than that of the groove at the first mask layer;
after the first mask layer 21 and the second mask layer 22 are formed, the first mask layer 21 and the second mask layer 22 are etched to form a groove 23 exposing the substrate 20. As shown in fig. 7, the width L2 of the groove 23 at the second mask layer 22 is less than the width L1 of the groove 23 at the first mask layer 21.
In the embodiment of the present invention, the process of etching the first mask layer 21 and the second mask layer 22 includes: as shown in fig. 8, a mask 24 is formed on the second mask layer 22, the mask 24 having an opening 240, the opening 240 exposing the second mask layer 22 in the region to be etched. The mask 24 may be a photoresist mask, etc.; then, the first mask layer 21 and the second mask layer 22 are etched by using a dry etching process and/or a wet etching process.
In some embodiments of the present invention, under the same etching conditions, the etching rate of the second mask layer 22 is less than or equal to the etching rate of the first mask layer 21, so that the width L2 of the groove 23 at the second mask layer 22 is less than the width L1 of the groove 23 at the first mask layer 21.
If the etching rate of the second mask layer 22 is equal to the etching rate of the first mask layer 21 under the same etching condition, the thickness of the second mask layer 22 is greater than that of the first mask layer 21; if the etching rate of the second mask layer 22 is less than the etching rate of the first mask layer 21 under the same etching condition, the thickness of the second mask layer 22 is greater than or equal to the thickness of the first mask layer 21, and certainly, in some cases, the thickness of the second mask layer 22 may also be slightly less than the thickness of the first mask layer 21, which is not described herein again.
For example, when the wet etching process is used to etch the first mask layer 21 and the second mask layer 22, if the thickness of the second mask layer 22 is equal to the thickness of the first mask layer 21 and the etching rate of the second mask layer 22 is less than the etching rate of the first mask layer 21, the etching degree of the second mask layer 22 is less than the etching degree of the first mask layer 21, so that the width L2 of the groove 23 at the second mask layer 22 is less than the width L1 of the groove 23 at the first mask layer 21.
In some embodiments of the present invention, the materials of the first mask layer 21 and the second mask layer 22 are different, so that the etching rate of the second mask layer 22 is less than or equal to the etching rate of the first mask layer 21 under the same etching condition. Of course, in other embodiments of the present invention, the materials of the first mask layer 21 and the second mask layer 22 may be the same, but the densities of the first mask layer 21 and the second mask layer 22 are different, so that the etching rate of the second mask layer 22 is less than or equal to the etching rate of the first mask layer 21 under the same etching conditions.
The material with different densities may be silicon dioxide, Low Temperature Oxidation (LTO), phosphorus-doped silicon dioxide (PSG), or the like. That is, the material of the first mask layer 21 may be silicon dioxide doped with phosphorus, and the material of the second mask layer 22 may be low temperature silicon dioxide.
In some embodiments of the present invention, after forming the mask 24 on the second mask layer 22, a portion of the mask layer in the region to be etched needs to be etched first, and then the remaining mask layer in the region to be etched needs to be etched, so as to form the groove 23 exposing the substrate 20. In a specific embodiment, a dry etching process may be used to etch a part of the mask layer in the region to be etched, and then a wet etching process may be used to etch the remaining mask layer in the region to be etched. Of course, the present invention is not limited to this, and in other embodiments, a wet etching process may be used to etch a part of the mask layer in the region to be etched first, and then a dry etching process is used to etch the remaining mask layer in the region to be etched, which is not described herein again.
Wherein the portion of the mask layer includes at least a portion of the second mask layer 22. The etching of the partial mask layer of the area to be etched comprises the following steps: as shown in fig. 9, a part of the second mask layer 22 of the region to be etched is etched, as shown in fig. 10, all of the second mask layer 22 of the region to be etched is etched, and as shown in fig. 11, all of the second mask layer 22 and a part of the first mask layer 21 of the region to be etched are etched.
For example, in some embodiments of the present invention, under the limitation of the mask material or the mask process, the thickness of the second mask layer 22 is greater than the thickness of the first mask layer 21, and at this time, if only one etching process, such as a wet etching process, is used, the etching time is long, so in some embodiments of the present invention, a dry etching process is used to etch part of the mask layer, and then a wet etching process is used to etch the remaining mask layer, so as to accelerate the process.
Or, when the mask layer of the region to be etched is etched by using the dry etching process, in order to avoid damage to the substrate 20 caused by the dry etching process, a part of the mask layer is etched, a part of the mask layer is reserved, and then the remaining mask layer is etched by using the wet etching process.
S104: forming a metal layer on the substrate exposed by the groove and the second mask layer;
after the first mask layer 21 and the second mask layer 22 are etched to form the recess 23, the mask 24 on the second mask layer 22 is removed. It should be noted that, when the first mask layer 21 and the second mask layer 22 are etched by using a dry etching process and a wet etching process, the mask 24 may be retained while the remaining mask layer in the region to be etched is etched by using the wet etching process, and may be removed after the wet etching, or the mask 24 may be removed first and then the wet etching is performed. As shown in fig. 12, a metal layer 25 is deposited on the substrate 20 exposed by the recess 23 and the second mask layer 22, and the material of the metal layer 25 is determined by the semiconductor device to be formed, and may be copper, silver, aluminum, or the like.
Since the width L2 of the groove 23 at the second mask layer 22 is smaller than the width L1 of the groove 23 at the first mask layer 21, a certain gap exists between the metal layer 25 formed on the substrate 20 exposed by the groove 23 and the first mask layer 21, and the metal layer 25 at the position cannot be affected when the first mask layer 21 is etched and removed subsequently.
It should be noted that the width L2 of the recess 23 at the second mask layer 22 is determined by the width of the metal layer 25, and the width of the metal layer 25 is determined by the requirements of the device to be fabricated or the metal deposition process.
In some embodiments of the present invention, the thickness of the first mask layer 21 is greater than the thickness of the metal layer 25, so that the thicknesses of the regions of the metal layer 25 are the same. The thickness of the metal layer 25 is determined by the device requirements. If the thickness of the first mask layer 21 is smaller than the thickness of the metal layer 25, the thickness of the metal layer 25 is reduced at the boundary between the first mask layer 21 and the second mask layer 22, so that the uniformity of the thickness of the metal layer 25 is poor, and the yield of the semiconductor device is affected.
S105: and removing the first mask layer, the second mask layer and the metal layer on the second mask layer, and reserving the metal layer on the substrate exposed by the groove.
Thereafter, as shown in fig. 13, the first mask layer 21 and the second mask layer 22 are etched, and the metal layer 25 on the second mask layer 22 is stripped while the first mask layer 21 and the second mask layer 22 are removed, so that the metal layer 25 on the substrate 20 exposed by the groove 23 is remained.
It should be noted that, a wet etching process may be used to etch the first mask layer 21 and the second mask layer 22 around the groove 23, and after the first mask layer 21 and the second mask layer 22 are etched away, the metal layer 25 on the second mask layer 22 is stripped from the substrate 20. When the wet etching process is used to etch or corrode the first mask layer 21 and the second mask layer 22, it is necessary to ensure that the etching solution has little or no corrosion to the metal layer 25, so as to prevent the etching solution from corroding the metal layer 25 remaining on the substrate 20.
In some embodiments of the present invention, after depositing the metal layer 25 on the substrate 20 exposed by the recess 23 and the second mask layer 22, the method further includes:
the surface of the metal layer 25 is treated by a frequency trimming process.
Because the film thicknesses of the metal layers 25 in different areas are greatly different after the metal layer 25 is deposited, in some embodiments of the invention, a frequency correction process can be adopted to perform function calculation, and plasmas with different intensities are adopted to correct and smooth the uneven films, so that the uniformity of the films of the metal layers 25 can be improved, and the yield of semiconductor devices can be improved.
It should be noted that if the metal layer shown in fig. 2 is placed in a cavity for plasma treatment, the photoresist will contaminate the cavity and the metal layer that has just grown, and therefore, the metal layer patterning method shown in fig. 1 to 3 cannot be used to treat the surface of the metal layer 25 by using a frequency correction process. The first mask layer 21 and the second mask layer 22 in the present invention are not photoresists, but films formed by a deposition process, and thus, when placed in a cavity for plasma processing, no contamination is caused.
The embodiment of the invention also provides a semiconductor device, as shown in fig. 13, which is manufactured by adopting any one of the above embodiments. Optionally, the semiconductor device in the embodiment of the present invention is a wafer level package structure, however, the present invention is not limited thereto, and in other embodiments, the semiconductor device may also be a PCB or the like, that is, a semiconductor device that needs to form a patterned metal layer is within the scope of the present invention.
According to the semiconductor device and the manufacturing method thereof provided by the embodiment of the invention, the first mask layer and the second mask layer are the thin film layers manufactured on the substrate by adopting the deposition process, but not the photoresist layer, so that the first mask layer and the second mask layer cannot be influenced even if the temperature of the deposition process for forming the metal layer subsequently is too high, namely the first mask layer and the second mask layer formed by adopting the deposition process have low requirements on the deposition temperature of the metal layer, and the deposition difficulty of the metal layer can be reduced. In addition, the first mask layer and the second mask layer are thin film layers which are manufactured on the substrate by adopting a deposition process and are not photoresist layers, so that the surface of the metal layer is processed by adopting a frequency correction process, the cavity and the thin film are not influenced, the surface of the metal layer can be processed by adopting the frequency correction process, and the yield of the semiconductor device is improved.
Although the embodiments of the present invention have been disclosed, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
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| CN115881518A (en) * | 2022-11-10 | 2023-03-31 | 清华大学 | Preparation method of passivation film for semiconductor device, semiconductor device and GCT device |
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| CN117672821A (en) * | 2022-08-25 | 2024-03-08 | 苏州晶湛半导体有限公司 | Semiconductor structure and manufacturing method thereof |
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| CN113257662B (en) | 2021-09-24 |
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