JP2000114133A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine pattern by using a silylation process and to form S on a surface of a silylation part.
It is desired to provide a method for manufacturing a semiconductor device, which can remove an iO _x layer without hindrance. A patterning layer (23) on a base substrate (20).
A resist layer 24 is formed thereon, and then a predetermined portion of the resist layer 24 is exposed.
The unexposed portion in 4 is silylated. Subsequently, the exposed portion of the resist layer 24 is removed by dry development,
A laminated pattern 30 corresponding to the silylated portion is obtained. Next, the resist pattern 32 is formed by removing the SiO _x layer 29 formed on the surface layer from the laminated pattern 30. Thereafter, the layer 23 to be patterned is etched using the resist pattern 32 as a mask.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a step of performing etching using a silylation process.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor device such as a semiconductor integrated circuit, for example, when a design circuit is transferred to a substrate, a lithography technique using light is used. Exposure light sources used for the lithography technique are mainly g-line (wavelength: 463 nm), i-line (wavelength: 365 nm) of a mercury lamp, KrF
There are excimer lasers (wavelength: 248 nm), and in the future, ArF excimer lasers (wavelength: 193 nm) and X
It is said that lines are used.

In such a lithography technique, the minimum dimension of a pattern that can be exposed and transferred is about the exposure wavelength. In addition, in order to perform exposure transfer, a defocus margin is required to cope with a step in the surface layer of the substrate or aberration of a lens of the exposure apparatus, but when the pattern is miniaturized to about the exposure wavelength, the pattern formation becomes difficult. On the other hand, the allowable defocus amount, that is, the depth of focus is rapidly reduced. Further, when the pattern is miniaturized, the contrast of the pattern optical image decreases, and the margin for fluctuation in the exposure amount (effective exposure amount including the reflected light from the underlying substrate), that is, the exposure margin decreases. Therefore, as the miniaturization of semiconductor integrated circuits and the like progresses, exposure sources having shorter wavelengths are being used.

However, in order to use an exposure light source having a shorter wavelength, a large amount of capital investment is required to newly introduce an exposure apparatus having a shorter exposure wavelength. Also, more than that,
In the short wavelength region after the ArF excimer laser, devices and materials such as an exposure light source, a glass material and a resist used for an exposure device are currently in the development stage, and there is no device having performance that can withstand production at present.

Therefore, using the existing exposure apparatus as it is,
It has been necessary to form a pattern having a wavelength equal to or shorter than the exposure wavelength while securing the depth of focus by some method. As one of the techniques to meet such a demand, there is a silylation process for resolving only the resist surface layer. Hereinafter, an example of a positive silylation process will be described as the silylation process.

In this positive silylation process, first, as shown in FIG. 3A, a layer 2 to be patterned is formed on a base substrate 1, and further a layer for the silylation process is formed on the layer 2 to be patterned. A resist is applied to form a resist layer 3. Next, as shown in FIG.
, A desired pattern, in this example, a circuit pattern, is exposed and transferred onto the resist layer 3. Then, in the exposed portion of the resist layer 3, molecules in the resist cause a crosslinking reaction to form an exposed portion 5.

Next, as shown in FIG. 3C, the surface layer of the base substrate 1, that is, the resist
Exposure to Then, the uncrosslinked portion, that is, the surface portion of the unexposed portion is selectively silylated, whereby the silylated portion 7 is formed in a portion other than the exposed portion 5.

Next, anisotropic etching with O ₂ plasma, that is, dry development is performed. When dry development is performed in this manner, in the silylation portion 7, silicon reacts with oxygen on its surface as shown in FIG.
An iO _x layer 8 is formed, which functions as a mask.
Therefore, the etching (dry development) does not proceed in the portion where the silylated portion 7 is formed, and only the exposed portion 5 is selectively removed, whereby the SiO _x layer 8 and the silylated portion 7 and the position immediately below it are located. A laminated pattern 9 made of a resist is formed.

[0009] Then, by the lamination pattern 9 as a mask to etch the target patterning layer 2 as shown in FIG. 3 (e), further SiO _x layer 8 is removed by fluorine plasma, followed O ₂ plasma in bulk By ashing and removing the resist, a desired pattern 10 is obtained as shown in FIG.

According to the patterning method using this silylation process, since only the surface layer of the resist layer 3 is resolved, a fine pattern can be formed. In addition, since a resist having a high light absorptivity can be used, reflected light from the underlying substrate 1 can be suppressed, and therefore, the standing wave effect can be reduced, thereby obtaining high pattern dimensional accuracy. it can.

[0011]

By the way, after the underlying substrate 1 is etched using the laminated pattern 9 formed by such a silylation process as a mask, as shown in FIG. An element made of SiO ₂ or the like,
For example, a gate oxide film 11 made of SiO ₂ or an element isolation region 12 made of a buried oxide film may be exposed.

Then, the elements made of SiO ₂ or the like such as the gate oxide film 11 and the element isolation region 12 have no etching selectivity with respect to the SiO _x layer 8 on the surface of the silylated portion 7. _{When the x-} layer 8 is removed by ashing with, for example, fluorine-based plasma, the gate oxide film 11 and the element isolation region 12 are also ashed as shown in FIG. "Edging" occurs, and in the element isolation region 12, "erosion" occurs on the upper portion thereof, and the element isolation region 12 is partially shaved and removed. If the gate oxide film 11 and the element isolation region 12 are also partially removed in this way, the device characteristics of the obtained semiconductor device deteriorate.

The present invention has been made in view of the above circumstances, and an object of the present invention is to enable a fine pattern to be formed by using a silylation process, and to further form an SiO _x layer formed on the surface of a silylation portion. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which can perform removal of a semiconductor without any trouble.

[0014]

According to a method of manufacturing a semiconductor device of the present invention, a resist layer is formed on a layer to be patterned on a base substrate, and then a predetermined portion of the resist layer is exposed. The unexposed portion of the resist layer after the process is silylated, and then the exposed portion of the resist layer is removed by dry development to form a laminated pattern corresponding to the silylated portion. The method of solving the above problem is to remove the SiO _x layer formed on the substrate and form a resist pattern, and then to etch the layer to be patterned using the resist pattern as a mask.

According to this manufacturing method, since the SiO _x layer is removed from the layered pattern before the layer to be patterned is etched, the resist pattern after the etching is removed by ashing using O ₂ plasma or a resist removing liquid. It is possible to use a normal method such as that described above. Therefore, even if an element having a poor selectivity with respect to the SiO _x layer is exposed on the base substrate after etching, the S
Since the iO _x layer has already been removed, the resist pattern can be peeled off without any problem as described above.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is a method which is preferably employed particularly in the manufacture of a semiconductor device such as an integrated semiconductor circuit in which fine integration has been advanced, and which uses a resist pattern formed by a silylation process as a mask. Prior to etching the layer to be patterned, the SiO _x layer formed on the surface layer of the pattern made of the resist is removed.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to an embodiment. (Embodiment 1) This embodiment is an example in which the present invention is applied to the formation of a gate pattern. First, as shown in FIG. 1A, an element isolation region 21 made of SiO ₂ is formed on a silicon substrate 20 serving as a base substrate by a known element isolation technique.
Was formed, and a gate oxide film 22 having a thickness of about 2 nm was further formed. Next, polysilicon was deposited by a CVD method to form a polysilicon layer (layer to be patterned) 23 having a thickness of about 150 nm. Subsequently, a resist mainly containing polyvinyl phenol for the silylation process was applied to a thickness of about 700 nm by a spin coating method to obtain a resist layer 24.

Next, the silicon substrate 20 is heated at 100.degree.
Pre-bake for 0 second, and then, using an exposure apparatus (not shown), as shown in FIG.
The resist layer 24 was exposed to light through a mask M having the gate pattern described above, and the gate pattern was transferred onto the resist layer 24. Here, an ArF excimer laser is used as an exposure light source, and an exposure wavelength is 193n as an exposure apparatus.
A 1/4 projection exposure apparatus with a reduction rate of m was used. When the exposure and transfer were performed in this manner, the exposed portions of the resist layer 24 were photocrosslinked and became exposed portions 25.

Next, as shown in FIG.
The surface layer of the silicon substrate 20, that is, the resist layer 24 is exposed to the silylation agent vapor 26 adjusted to the vapor pressure of 10 Torr at the temperature of 80 s for 80 seconds. Then, the resist layer 2
4 No photocrosslinking of the surface has occurred, so
However, the portion corresponding to the target gate pattern, that is, the portion corresponding to the target gate pattern was silylated to form the silylated portion 27. In addition,
In this example, dimethylsilyldimethylamine (DMSDM) was used as a silylating agent.
A) was used.

Next, as shown in FIG. 1 (d), at a temperature of 10.degree.
The resist layer 24 was subjected to anisotropic etching, that is, dry development, using O ₂ -SO ₂ plasma 28 of mTorr. Regarding the etching conditions, the flow rate of O ₂ was set to 160
The flow rate of sccm, SO ₂ was 30 sccm, the TCP power was 500 W, and the bias power was 100 W.

[0021] In this way the dry development, in the silylation unit 27, by silicon and oxygen at the surface as shown to react in FIG. 1 (d), having a thickness of about 30nm of SiO _x layer 29 Is formed. And this SiO
_{Since the x} layer 29 functions as a mask, etching (dry development) is performed at a portion where the silylated portion 27 is formed.
Does not proceed, and only the exposed portion 25 is selectively removed, whereby the laminated pattern 30 composed of the SiO _x layer 29 and the silylation portion 27 and the resist located immediately below the same becomes a pattern having a gate length of 130 nm. It is formed.

After the lamination pattern 30 is formed in this way, the TCP plasma etching apparatus used for forming the lamination pattern 30 is continuously used as it is, and the C ₂ F ₆ plasma 31 is used as shown in FIG. The SiO _x layer 29 on the surface of the laminated pattern 30 was etched and completely removed to form a resist pattern 32. Regarding the etching conditions, the flow rate of C ₂ F ₆ was 10 sccm, the TCP power was 150 W, and the bias power was 5 W.

Next, as shown in FIG. 2B, using an ECR plasma etching apparatus, a resist pattern 32 is formed.
As a mask, the polysilicon layer (patterned layer) 23 was etched using Cl ₂ —O ₂ plasma as the first step, and the gate oxide film 22 was etched using HBr—O ₂ plasma as the second step. . Regarding the etching conditions, the substrate temperature was 20 ° C., the pressure was 0.5 Pa,
Cl ₂ flow rate 15 sccm, O ₂ flow rate 5 scc
m, the HBr flow rate was 95 sccm, and the biased RF power was 25 W.

Thereafter, the resist pattern 32 is ashed with O ₂ plasma and further post-processed with an H ₂ SO ₄ / H ₂ O ₂ solution to form a polysilicon having a gate length of 130 nm as shown in FIG. A gate pattern 33 and a gate oxide film 22a are obtained. At this time, O ₂
Ashing by plasma and post-treatment with a H ₂ SO ₄ / H ₂ O ₂ solution have almost no action to erode SiO ₂ forming the gate oxide film 22 a and the element isolation region 21. The gate oxide film 22a and the element isolation region 21 could be maintained in a good state with almost no damage.

(Embodiment 2) This embodiment is also an example in which the present invention is applied to the formation of a gate pattern, as in the above (Embodiment 1). First, the laminated pattern shown in FIG. 1D was manufactured in the same manner as in (Embodiment 1). Next, using an ECR plasma etching apparatus, FIG.
As shown in (a), the SiO _x layer 29 on the surface of the laminated pattern 30 was etched using the C ₂ F ₆ plasma 31 and completely removed to form a resist pattern 32. Regarding the etching conditions, the flow rate of C ₂ F ₆ was set to 1
0 sccm and the bias power were 5 W.

Next, as shown in FIG. 2B, using the ECR plasma etching apparatus in the same manner as in (Embodiment 1), the first
The polysilicon layer (layer to be patterned) 23 is etched using Cl ₂ —O ₂ plasma as a step,
Gate oxide film 2 using HBr-O ₂ plasma as a step
2 was etched. The etching conditions were the same as in (Embodiment 1).

Thereafter, the resist pattern 32 is ashed with O ₂ plasma and further post-processed with an H ₂ SO ₄ / H ₂ O ₂ solution, thereby forming a poly-metal having a gate length of 130 nm as shown in FIG. A gate pattern 33 made of silicon and a gate oxide film 22a were obtained. Also in this example, the gate oxide film 22a and the element isolation region 21 could be maintained in a good state with almost no damage.

(Embodiment 3) This embodiment is also an example in which the present invention is applied to the formation of a gate pattern in the same manner as in (Embodiment 1). First, the laminated pattern shown in FIG. 1D was manufactured in the same manner as in (Embodiment 1). Next, using a spin processor, the silicon substrate 20 is immersed in a 0.5% hydrofluoric acid solution for 10 minutes, and the SiO _x layer 29 on the surface of the laminated pattern 30 is etched to completely remove it. A resist pattern 32 was formed.

Thereafter, the polysilicon layer 23 was etched in the same manner as in (Embodiment 1) to obtain a gate pattern 33 and a gate oxide film 22a. Also in this example, the gate oxide film 22a and the element isolation region 21 could be maintained in a good state with almost no damage.

[0030]

The method of manufacturing a semiconductor device of the present invention as described above, according to the present invention, since a method of removing the SiO _x layer from the lamination pattern before etching to be patterned layer, the peeling of the resist pattern after etching An ordinary method using ashing with O ₂ plasma, a resist stripper, or the like can be used. Therefore, even if SiO
_Even if an element that cannot have a selective ratio with the _x layer is exposed on the base substrate after the etching, the resist pattern is stripped without any trouble as described above because the SiO _x layer has already been removed. be able to.

Therefore, according to the present invention, a fine pattern can be formed by a silylation process without damaging each element on a base substrate, and therefore, it is possible to cope with the manufacture of an integrated semiconductor circuit in which fine integration is advanced. can do. Further, when the vapor phase etching method is used to remove the SiO _x layer, a dry developing apparatus or an apparatus for etching a layer to be patterned can be used as it is, and therefore, cost reduction and contamination control can be achieved. .

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views of a main part for describing an embodiment of a method of manufacturing a semiconductor device according to the present invention in the order of steps.

2 (a) to 2 (c) are views for explaining one embodiment of a method for manufacturing a semiconductor device according to the present invention, and FIG.
FIG. 9 is a side sectional view of a main part for sequentially describing steps subsequent to the step shown in (d).

FIGS. 3A to 3F are cross-sectional views of a main part for explaining an example of a conventional method of manufacturing a semiconductor device in the order of steps.

FIG. 4 is a cross-sectional side view of a main part for describing a problem in an example of the method of manufacturing the conventional semiconductor device shown in FIG.

[Explanation of symbols]

Reference Signs List 20: silicon substrate (base substrate), 23: polysilicon layer (layer to be patterned), 24: resist layer, 25: exposed portion, 26: silylating agent vapor, 27: silylation portion, 29
... SiO _x layer, 30 ... laminated pattern, 32 ... resist pattern, 33 ... gate pattern

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/302 HF term (Reference) 2H096 AA25 BA11 CA02 CA14 DA01 EA05 GA39 5F004 BA14 BA20 BB04 CA04 DA00 DA02 DA04 DA26 DB02 DB03 DB26 EA04 EA26 5F046 AA05 BA04 CA04 JA04 LB01 MA12

Claims (4)

[Claims] 1. A step of forming a resist layer on a layer to be patterned on an undersubstrate, a step of exposing a predetermined portion of the resist layer, and a step of silylating an unexposed portion of the resist layer after the exposing step. Removing the resist layer at the exposed location by dry development to obtain a laminated pattern corresponding to the silylated portion; and forming SiO _x on the surface layer portion from the laminated pattern.
A method for manufacturing a semiconductor device, comprising: a step of forming a resist pattern by removing a layer; and a step of etching the layer to be patterned using the resist pattern as a mask. 2. The step of forming a resist pattern by removing the SiO _x layer is performed after the step of performing the dry development, and the apparatus for performing the dry development removes the SiO _x layer with a plasma of a fluorine-based gas. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed. The method according to claim 3 wherein the step of forming a resist pattern by removing the SiO _x layer, prior to the step of etching to be patterned layer by this be patterned layer etching apparatus, the SiO _x layer with a plasma of fluorine gas 2. The method according to claim 1, wherein the removing is performed. 4. The method according to claim 1, wherein the step of removing the SiO _x layer to form a resist pattern is performed by removing the SiO _x layer with a hydrofluoric acid aqueous solution.