CN109638135A - Luminescence chip and its manufacturing method and current expansion method - Google Patents
Luminescence chip and its manufacturing method and current expansion method Download PDFInfo
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- CN109638135A CN109638135A CN201910006183.0A CN201910006183A CN109638135A CN 109638135 A CN109638135 A CN 109638135A CN 201910006183 A CN201910006183 A CN 201910006183A CN 109638135 A CN109638135 A CN 109638135A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/831—Electrodes characterised by their shape
- H10H20/8316—Multi-layer electrodes comprising at least one discontinuous layer
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/83—Electrodes
- H10H20/831—Electrodes characterised by their shape
- H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/032—Manufacture or treatment of electrodes
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Abstract
本发明公开了一发光芯片及其制造方法和电流扩展方法，其中所述发光芯片包括依次层叠的一衬底、一N型半导体层、一发光层、一P型半导体层、一透明导电层以及一钝化保护层，所述发光芯片进一步包括层叠于所述钝化保护层的一N型电极和一P型电极，其中所述N型电极被电连接于所述N型半导体层，所述P型电极被电连接于所述P型半导体层和所述透明导电层，其中自所述N型电极注入的电流能够在所述N型电极的N型电极焊盘的附近被注入所述N型半导体层，自所述P型电极注入的电流能够在所述P型电极的P型电极焊盘的附近被进一步注入透明导电层，通过这样的方式，电流能够被均匀地分布，从而有利于提高发光效率和提升整体亮度。
The invention discloses a light-emitting chip, a manufacturing method and a current spreading method thereof, wherein the light-emitting chip comprises a substrate, an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, a transparent conductive layer and a passivation protection layer, the light-emitting chip further includes an N-type electrode and a P-type electrode stacked on the passivation protection layer, wherein the N-type electrode is electrically connected to the N-type semiconductor layer, the A P-type electrode is electrically connected to the P-type semiconductor layer and the transparent conductive layer, wherein the current injected from the N-type electrode can be injected into the N-type electrode in the vicinity of the N-type electrode pad of the N-type electrode type semiconductor layer, the current injected from the P-type electrode can be further injected into the transparent conductive layer in the vicinity of the P-type electrode pad of the P-type electrode. In this way, the current can be uniformly distributed, which is beneficial to Improve luminous efficiency and enhance overall brightness.
Description
Technical field
The present invention relates to semiconductor fields, in particular to a luminescence chip and its manufacturing method and current expansion method.
Background technique
Light emitting diode (Light Emmitting Diode, LED) is as the ring of new generation for replacing incandescent lamp and fluorescent lamp
Light source is protected, compared with conventional illumination sources, has that high-efficient, low energy consumption, the service life is long, pollution-free, small in size, rich in color etc. all
More advantages are widely used in the fields such as illumination, display and backlight.The prior art, which exists, incorporates passivation protection layer and electric current
The semiconductor chip of the light emitting diode on barrier layer, wherein the P metal electrode of semiconductor chip directly connects with p type semiconductor layer
Touching and N metal electrode are directly contacted with n type semiconductor layer, to infuse in subsequent permission electric current from N metal electrode and P metal electrode
Enter semiconductor chip, this structure of semiconductor chip causes to there is many defects.Specifically, semiconductor chip
P metal electrode and p type semiconductor layer can not form Ohmic contact, cause electric current near the p-type pad of P metal electrode that cannot be had
Effect ground injects and the brightness of semiconductor chip is caused to reduce, although and the N-type pad of N metal electrode is contacted with n type semiconductor layer
Well, but since the N-type bonding pad area of N metal electrode is bigger, electric current is caused excessively to concentrate on the N-type weldering of N metal electrode
Disk position, so cause current-crowding effect occur and the brightness that reduces semiconductor chip.
Summary of the invention
It is an object of the present invention to provide a luminescence chip and its manufacturing methods and current expansion method, wherein from institute
The electric current of a N-type electrode and P-type electrode injection for stating luminescence chip can be evenly distributed in the luminescence chip, thus
Promote the brightness of the luminescence chip.
It is an object of the present invention to provide a luminescence chip and its manufacturing methods and current expansion method, wherein described
It is partially electronically conductive near one N-type electrode pad of one N-type electrode of luminescence chip, to avoid the electric current injected from the N-type electrode
There is the bad phenomenon of crowding effect near the N-type electrode pad；Wherein the one of a P-type electrode of the luminescence chip
It is partially electronically conductive near P-type electrode pad, to improve the efficiency from the P-type electrode Injection Current, in this way, from institute
The electric current for stating N-type electrode and P-type electrode injection can be evenly distributed in the luminescence chip.
It is an object of the present invention to provide a luminescence chip and its manufacturing methods and current expansion method, wherein in institute
The lower part for stating the N-type electrode pad of N-type electrode is arranged a passivation protection layer and is arranged near the N-type electrode pad
The short pin of an at least N-type electrode, is partly led by the N-type that the short pin of the N-type electrode injects a current into the semiconductor chip
There is the bad phenomenon of crowding effect in the N-type electrode pad to avoid the electric current injected from the N-type electrode in body layer.
It is an object of the present invention to provide a luminescence chip and its manufacturing methods and current expansion method, wherein in institute
The passivation protection layer is arranged in the lower part for stating the N-type electrode pad of N-type electrode, so that the surface of the N-type electrode pad
It is smooth, to promote the reliability of encapsulation bonding wire.
It is an object of the present invention to provide a luminescence chip and its manufacturing methods and current expansion method, wherein in institute
It states and an at least P-type electrode short pin is set near the P-type electrode pad of P-type electrode, pass through the short pin of the P-type electrode
A transparency conducting layer is injected a current into, to improve the efficiency from the P-type electrode Injection Current.
One aspect under this invention, the present invention provide a luminescence chip comprising the substrate that stacks gradually, a N-type
Semiconductor layer, a luminescent layer, a p type semiconductor layer, a transparency conducting layer and a passivation protection layer, wherein the luminescence chip
Further comprise:
One N-type electrode comprising:
One N-type electrode pad is laminated in the passivation protection layer in the second end of the luminescence chip；
The short pin of an at least N-type electrode, extend the N-type electrode pad and pass through the passivation protection layer after
The n type semiconductor layer is electrically connected near the N-type electrode pad；And
The long pin of an at least N-type electrode, prolongs from the N-type electrode pad to the first end direction of the luminescence chip
It stretches and is electrically connected to the n type semiconductor layer after passing through the passivation protection layer；With
One P-type electrode comprising:
One P-type electrode pad is laminated in the passivation protection layer in the first end of the luminescence chip and is passing through
The p type semiconductor layer is electrically connected to after the passivation protection layer；
The short pin of an at least P-type electrode, extend the P-type electrode pad and pass through the passivation protection layer after
The transparency conducting layer is electrically connected near the P-type electrode pad；And
The long pin of an at least P-type electrode prolongs from the second end direction of luminescence chip described in the P-type electrode pad type
It stretches and is electrically connected to the transparency conducting layer after passing through the passivation protection layer.
According to one embodiment of present invention, the extending direction of the short pin of the N-type electrode of the N-type electrode and described
The extending direction of the long pin of N-type electrode is opposite.
According to one embodiment of present invention, the extending direction of the short pin of the P-type electrode of the P-type electrode and described
The extending direction of the long pin of P-type electrode is identical.
According to one embodiment of present invention, the N-type electrode includes a long pin of N-type electrode, and the N
The long pin of type electrode is laminated in the middle part of the passivation protection layer, wherein the P-type electrode includes that two P-type electrode length are drawn
Foot, and the long pin of the P-type electrode is laminated in the edge of the passivation protection layer.
According to one embodiment of present invention, the N-type electrode includes two long pins of N-type electrode, and the N
The long pin of type electrode is laminated in the edge of the passivation protection layer, wherein the P-type electrode includes that the P-type electrode length is drawn
Foot, and the long pin of the P-type electrode is laminated in the middle part of the passivation protection layer.
According to one embodiment of present invention, the N-type electrode includes two long pins of N-type electrode, and the N
The long pin of type electrode is laminated in the middle part of the passivation protection layer, wherein the P-type electrode includes that three P-type electrode length are drawn
Foot, and a long pin of P-type electrode in three long pins of P-type electrode is laminated in the passivation protection layer
Portion, other two long pin of P-type electrode are laminated in the edge of the passivation protection layer, and in two P-type electrodes
The long pin of N-type electrode is maintained between long pin.
According to one embodiment of present invention, the N-type electrode includes three long pins of N-type electrode, and three
A long pin of N-type electrode in the long pin of N-type electrode is laminated in the middle part of the passivation protection layer, other two
The long pin of N-type electrode is laminated in the edge of the passivation protection layer, wherein the P-type electrode includes two p-type electricity
Extremely long pin, and two long pins of P-type electrode are laminated in the middle part of the passivation protection layer, and in two N
The long pin of P-type electrode is maintained between the long pin of type electrode.
Other side under this invention, the present invention further provides a luminescence chips comprising:
One N-type electrode；
One P-type electrode；
One transparency conducting layer；
One extension unit a comprising substrate, a n type semiconductor layer, a luminescent layer and the p-type stacked gradually is partly led
Body layer, wherein the transparency conducting layer is laminated in the p type semiconductor layer；And
One passivation protection layer is laminated in the transparency conducting layer, wherein the passivation protection layer has an at least column N-type
The short pin channel of long pin channel, at least a N-type, a p-type pad channel, the long pin channel of an at least column p-type and an at least P
The short pin channel of type, wherein each of column long pin channel of N-type long pin channel is in a manner of being spaced apart from each other
Extend from the second end of the luminescence chip to first end direction, each short pin channel of N-type is respectively formed in institute
The second end of luminescence chip is stated, p-type pad channel is formed in the first end of the luminescence chip, a column p-type
Each of the long pin channel long pin channel of the p-type in a manner of being spaced apart from each other from the first end of the luminescence chip to
The second end direction extends, and each short pin channel of p-type is respectively formed in the first end of the luminescence chip, wherein institute
It states N-type electrode and is laminated in the passivation protection layer, and a part of the N-type electrode is passing through each long pin of N-type
It is electrically connected to the n type semiconductor layer behind channel and the short pin channel of each N-type, wherein the P-type electrode is laminated in
The passivation protection layer, and a part of the P-type electrode is electrically connected to the P after passing through p-type pad channel
Type semiconductor layer and institute is being electrically connected to after passing through each long pin channel of p-type and the short pin channel of each p-type
State transparency conducting layer.
According to one embodiment of present invention, the passivation protection layer has the long pin channel of a column N-type and two column
The long pin channel of p-type, a column long pin channel of N-type is at the middle part of the passivation protection layer from the luminescence chip
The second end extends to first end direction, the long pin channel of p-type described in each column respectively the edge of the passivation protection layer from
The first end of the luminescence chip extends to the second end direction.
According to one embodiment of present invention, the passivation protection layer has the long pin channel of the two column N-types and a column
The long pin channel of p-type, the long pin channel of N-type described in each column is respectively at the edge of the passivation protection layer from the luminous core
The second end of piece extends to first end direction, a column long pin channel of p-type the middle part of the passivation protection layer from
The first end of the luminescence chip extends to the second end direction.
According to one embodiment of present invention, the passivation protection layer has the long pin channel of the two column N-types and three column
The long pin channel of p-type, the long pin channel of N-type described in each column is respectively at the middle part of the passivation protection layer from the luminous core
The second end of piece extends to first end direction, the column long pin channel of p-type in the three column long pin channels of p-type
Extend at the middle part of the passivation protection layer from the first end of the luminescence chip to the second end direction, in addition described in two column
The long pin channel of p-type is respectively at the edge of the passivation protection layer from the first end of the luminescence chip to the second end direction
Extend, wherein maintaining the long pin channel of the column N-type between the two column long pin channels of p-type.
According to one embodiment of present invention, the passivation protection layer has the long pin channel of the three column N-types and two column
The long pin channel of p-type, the three column long pin channels of N-type arranged in the long pin channels of N-type are protected in the passivation
The middle part of sheath extends from the second end of the luminescence chip to first end direction, in addition the two column long pin channel point
Do not extend at the edge of the passivation protection layer from the second end of the luminescence chip to first end direction, P described in each column
The long pin channel of type is respectively at the middle part of the passivation protection layer from the first end of the luminescence chip to the second end direction
Extend, wherein maintaining the long pin channel of the column p-type between the two column long pin channels of N-type.
According to one embodiment of present invention, the N-type electrode includes:
One N-type electrode pad, is laminated in the passivation protection layer；
The short pin of an at least N-type electrode extends the N-type electrode pad and is passing through the every of the passivation protection layer
The n type semiconductor layer is electrically connected near the N-type electrode pad behind a short pin channel of the N-type；And
The long pin of an at least N-type electrode extends the N-type electrode pad and is passing through the every of the passivation protection layer
The n type semiconductor layer is electrically connected to behind a long pin channel of the N-type.
According to one embodiment of present invention, the P-type electrode includes:
One P-type electrode pad is laminated in the passivation protection layer and welds in the p-type for passing through the passivation protection layer
The p type semiconductor layer is electrically connected to behind disk channel；
The short pin of an at least P-type electrode extends the P-type electrode pad and is passing through the every of the passivation protection layer
The transparency conducting layer is electrically connected near the P-type electrode pad behind a short pin channel of the p-type；And
The long pin of an at least P-type electrode extends the P-type electrode pad and is passing through the every of the passivation protection layer
The transparency conducting layer is electrically connected to behind a long pin channel of the p-type.
Other side under this invention, the present invention further provides the current expansion method of a luminescence chip, wherein institute
Current expansion method is stated to include the following steps:
(a) electric current injected from a N-type electrode pad is guided to be injected a N-type half near the N-type electrode pad
Conductor layer；With
(b) it guides electric current inject from a P-type electrode pad to be injected one near the P-type electrode pad transparent to lead
Electric layer.
According to one embodiment of present invention, in the step (a), further guidance is infused from the N-type electrode pad
The electric current entered is injected the n type semiconductor layer at the middle part of the n type semiconductor layer, and in the step (b), further
The electric current injected from the P-type electrode pad is guided to be injected the transparency conducting layer at the middle part of the transparency conducting layer.
According to one embodiment of present invention, in the step (a), a passivation protection layer is formed in the N-type electrode
Between pad and the n type semiconductor layer, to prevent to be directly injected into the N-type half from the electric current that the N-type electrode pad injects
Conductor layer.
Other side under this invention, the present invention further provides the manufacturing methods of a luminescence chip, wherein the system
The method of making includes the following steps:
(i) one N-type electrode of stacking is in a passivation protection layer, wherein a N-type electrode pad of the N-type electrode is in the hair
The second end of optical chip is laminated in the passivation protection layer, and the N-type electrode extends the N-type electrode pad at least
The short pin of one N-type electrode is electrically connected to a N-type half after passing through the passivation protection layer near the N-type electrode pad
The long pin of an at least N-type electrode for extending the N-type electrode pad of conductor layer, the N-type electrode is passing through the passivation
The n type semiconductor layer is electrically connected to after protective layer；With
(ii) one P-type electrode of stacking is in the passivation protection layer, wherein a P-type electrode pad of the P-type electrode is in institute
The first end for stating luminescence chip passes through the passivation protection layer and is electrically connected to a p type semiconductor layer, the P-type electrode
The short pin of an at least P-type electrode of the P-type electrode pad is extended after passing through the passivation protection layer in the P-type electrode
A transparency conducting layer, at least P for extending the P-type electrode pad of the P-type electrode are electrically connected near pad
The long pin of type electrode is electrically connected to the transparency conducting layer after passing through the passivation protection layer.
According to one embodiment of present invention, before the step (i), the manufacturing method further comprises step:
An insulated substrate is laminated in a transparency conducting layer；
Etch the insulated substrate, with formed the passivation protection layer and be formed simultaneously the long pin channel of an at least column N-type,
The short pin channel of an at least N-type, a p-type pad channel, the long pin channel of an at least column p-type and the short pin channel of an at least p-type
In the passivation protection layer, thus in the step (i), the N-type electrode is passing through the long pin channel of the N-type and described
The n type semiconductor layer is electrically connected to behind the short pin channel of N-type, and in the step (ii), the P-type electrode is being passed through
It is electrically connected to the p type semiconductor layer behind p-type pad channel and is passing through the long pin channel of the p-type and the P
Type is electrically connected to the transparency conducting layer behind short pin channel.
Detailed description of the invention
Figure 1A is the schematic cross-sectional view of one of manufacturing step of a luminescence chip of a preferred embodiment under this invention.
Figure 1B is the vertical view signal of one of manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure.
Fig. 2A is the two section view signal of the manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure.
Fig. 2 B is the two vertical view signal of the manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure.
Fig. 3 A is the three section view signal of the manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure.
Fig. 3 B is the three vertical view signal of the manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure.
Fig. 4 A is the four section view signal of the manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure, it illustrates the section view states of the luminescence chip.
Fig. 4 B is the four vertical view signal of the manufacturing step of the luminescence chip of above-mentioned preferred embodiment under this invention
Figure, it illustrates the overlooking states of the luminescence chip.
Fig. 5 A is the section view of a variant embodiment of the luminescence chip of above-mentioned preferred embodiment under this invention
Schematic diagram.
Fig. 5 B is the vertical view of the above-mentioned variant embodiment of the luminescence chip of above-mentioned preferred embodiment under this invention
Schematic diagram.
Fig. 6 A is cuing open for another variant embodiment of the luminescence chip of above-mentioned preferred embodiment under this invention
Depending on schematic diagram.
Fig. 6 B is the vertical view of the above-mentioned variant embodiment of the luminescence chip of above-mentioned preferred embodiment under this invention
Schematic diagram.
Fig. 7 A is cuing open for another variant embodiment of the luminescence chip of above-mentioned preferred embodiment under this invention
Depending on schematic diagram.
Fig. 7 B is the vertical view of the above-mentioned variant embodiment of the luminescence chip of above-mentioned preferred embodiment under this invention
Schematic diagram.
Specific embodiment
It is described below for disclosing the present invention so that those skilled in the art can be realized the present invention.It is excellent in being described below
Embodiment is selected to be only used as illustrating, it may occur to persons skilled in the art that other obvious modifications.It defines in the following description
Basic principle of the invention can be applied to other embodiments, deformation scheme, improvement project, equivalent program and do not carry on the back
Other technologies scheme from the spirit and scope of the present invention.
It will be understood by those skilled in the art that in exposure of the invention, term " longitudinal direction ", " transverse direction ", "upper",
The orientation of the instructions such as "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside" or position are closed
System is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present invention and simplification of the description, without referring to
Show or imply that signified device or element must have a particular orientation, be constructed and operated in a specific orientation, therefore above-mentioned art
Language is not considered as limiting the invention.
It is understood that term " one " is interpreted as " at least one " or " one or more ", i.e., in one embodiment,
The quantity of one element can be one, and in a further embodiment, the quantity of the element can be it is multiple, term " one " is no
It can be interpreted as the limitation to quantity.
With reference to the attached drawing 1A to Fig. 4 B of Figure of description of the invention, a luminous core of a preferred embodiment under this invention
Piece and its manufacturing process are disclosed for and are set forth in following description, wherein the luminescence chip includes an extension unit
10, a transparency conducting layer 20, a passivation protection layer 30, a N-type electrode 40 and a P-type electrode 50.
The extension unit 10 includes a substrate 11, a n type semiconductor layer 12, a luminescent layer 13 and a P-type semiconductor
Layer 14, wherein the n type semiconductor layer 12 is laminated in the substrate 11, the luminescent layer 13 is laminated in the n type semiconductor layer
12, the p type semiconductor layer 14 is laminated in the luminescent layer 13, so that the substrate 11, the n type semiconductor layer 12, described
Luminescent layer 13 and the p type semiconductor layer 14 stack gradually.The transparency conducting layer 20 is laminated in the institute of the extension unit 10
P type semiconductor layer 14 is stated, the passivation protection layer 30 is laminated in the transparency conducting layer 20, the N-type electrode 40 and the p-type
Electrode 50 is respectively laminated on the passivation protection layer 30, and the N-type electrode 40 is electrically connected to the extension unit 10
The n type semiconductor layer 12, the P-type electrode 50 are electrically connected to 14 He of the p type semiconductor layer of the extension unit 10
The transparency conducting layer 20.
For example, growing the N-type half from the substrate 11 in a preferable examples of the luminescence chip of the invention
Conductor layer 12, so that the n type semiconductor layer 12 is laminated in the substrate 11；The hair is grown from the n type semiconductor layer 12
Photosphere 13, so that the luminescent layer 13 is laminated in the n type semiconductor layer 12；The p-type is grown from the luminescent layer 13 partly to lead
Body layer 14, so that the p type semiconductor layer 14 is laminated in the luminescent layer 13, so that the substrate 11, the N-type are partly led
Body layer 12, the luminescent layer 13 and the p type semiconductor layer 14 stack gradually.
It is noted that the type of the substrate 11 of the extension unit 10 can be but not limited to sapphire lining
Bottom, silicon substrate, silicon carbide substrates etc..The n type semiconductor layer 12 and the p type semiconductor layer 14 can be but not limited to nitrogenize
Gallium layer.The luminescent layer 13 can be but not limited to quantum well layer.
With continued reference to attached drawing 1A and Figure 1B, the extension unit 10 has at least exposed portion 15 of semiconductor, wherein described
Semiconductor bare portion 15 extends to the n type semiconductor layer 12 through the luminescent layer 13 from the p type semiconductor layer 14, to allow
A part of surface of the n type semiconductor layer 12 is exposed to the semiconductor bare portion 15.
In a preferable examples of the luminescence chip of the invention, by the P for etching the extension unit 10
Type semiconductor layer 14 and the mode of the luminescent layer 13 are capable of forming from the p type semiconductor layer 14 to be extended through the luminescent layer 13
The extremely semiconductor bare portion 15 of the n type semiconductor layer 12, and a part of surface violence of the n type semiconductor layer 12
In the semiconductor bare portion 15.
In another preferable examples of the luminescence chip of the invention, by etching described in the extension unit 10
The mode of p type semiconductor layer 14, the luminescent layer 13 and the n type semiconductor layer 12 is capable of forming from the p type semiconductor layer
14 extend to the semiconductor bare portion 15 of the n type semiconductor layer 12, and the N-type semiconductor through the luminescent layer 13
A part of surface violence of layer 12 is in the semiconductor bare portion 15.That is, this in the luminescence chip specifically shows
In example, with reference to attached drawing 1A, a part of thickness of the n type semiconductor layer 12 is removed, thus pair of the n type semiconductor layer 12
The thickness of the part in semiconductor bare portion 15 described in Ying Yu corresponds to the luminescent layer less than the n type semiconductor layer 12
The thickness of 13 part.
Further, the extension unit 10 has the exposed portion 16 in an edge, wherein the exposed portion in the edge 16 is described
The edge of extension unit 10 extends to institute through the luminescent layer 13 and the n type semiconductor layer 12 from the p type semiconductor layer 14
Substrate 11 is stated, with the edge of the exposure n type semiconductor layer 12 in the exposed portion 16 in the edge.For example, described in of the invention
In one preferable examples of luminescence chip, by the p type semiconductor layer 14, the luminescent layer that etch the extension unit 10
13 and the mode of the n type semiconductor layer 12 be capable of forming from the p type semiconductor layer 14 through the luminescent layer 13 and the N-type
Semiconductor layer 12 extends to the exposed portion 16 in the edge of the substrate 11.
It is noted that the exposed portion 16 in the semiconductor bare portion 15 of the extension unit 10 and the edge can be with
It is formed simultaneously, can also be formed according to sequencing, the luminescence chip of the invention is unrestricted in this regard.In addition, erosion
The concrete technology that carving method forms the exposed portion 16 in the edge forms the concrete technology one in the semiconductor bare portion 15 with etching
It causes, for example, the P-type semiconductor of the extension unit 10 can be etched by dry method etch technology or wet etching process
Layer 14, the luminescent layer 13 and the n type semiconductor layer 12 are to form the exposed portion in the semiconductor bare portion 15 and the edge
16。
Further, with continued reference to attached drawing 1A and Figure 1B, the semiconductor bare portion 15 of the extension unit 10 has
The exposed portion 151 of one N-type pad, the exposed portion 152 of the long pin of a N-type and the exposed portion 153 of the short pin of an at least N-type, the wherein institute
The second end 102 that the exposed portion 151 of N-type pad is formed in the luminescence chip is stated, the exposed portion 152 of the long pin of N-type exists
Prolong from the exposed portion 151 of the N-type pad to 101 direction of a first end of the luminescence chip at the middle part of the extension unit 10
It stretches, each exposed portion 153 of the short pin of N-type is respectively from the exposed portion 151 of the N-type pad to described in a manner of being spaced apart from each other
The edge direction of the second end 102 of luminescence chip extends.In the short transverse of the luminescence chip, the extension unit
The exposed portion 151 of the N-type pad in the 10 semiconductor bare portion 15, the exposed portion 152 of the long pin of the N-type and each described
The exposed portion 153 of the short pin of N-type extends to the n type semiconductor layer through the luminescent layer 13 from the p type semiconductor layer 14 respectively
12, it is naked in the exposed portion 151 of the N-type pad, the long pin of the N-type with a part of surface of the exposure n type semiconductor layer 12
Dew portion 152 and each exposed portion 153 of the short pin of the N-type.
With reference to attached drawing 2A and Fig. 2 B, the transparency conducting layer 20 is laminated in the P-type semiconductor of the extension unit 10
Layer 14, wherein the transparency conducting layer 20 has a first passage 21 and a second channel 22, wherein the transparency conducting layer 20
The first passage 21 be formed in the first end 101 of the luminescence chip, and the first passage 21 corresponds to
The p type semiconductor layer 14 of the extension unit 10, with the exposure p type semiconductor layer 14 in the transparency conducting layer 20
The first passage 21, wherein the semiconductor bare portion 15 of the extension unit 10 corresponds to and be connected to described transparent lead
The second channel 22 of electric layer 20.Preferably, the shape of the second channel 22 of the transparency conducting layer 20 and described outer
The shape for prolonging the semiconductor bare portion 15 of unit 10 is consistent.It is highly preferred that described the second of the transparency conducting layer 20 is logical
The size in road 22 slightly larger than the semiconductor bare portion 15 of the extension unit 10 size, with reference to attached drawing 2A and Fig. 2 B, from
And a part of surface of the p type semiconductor layer 14 of the extension unit 10 is made to be exposed to the transparency conducting layer 20
The second channel 22.
In a specific example of the luminescence chip of the invention, the material of the transparency conducting layer 20 has high saturating
The characteristic of bright, high conductivity and low contact resistance, for example, forming the material of the transparency conducting layer 20 can be selected from but not limited to
NiAu alloy, tin indium oxide, indium zinc oxide, zirconium oxide, chromium oxide.
Specifically, the transparency conducting layer 20 is laminated in the step of the p type semiconductor layer 14 of the extension unit 10
Suddenly include:
Firstly, an electrically conducting transparent base is laminated in the extension unit 10, so that the electrically conducting transparent base is laminated in institute
State the p type semiconductor layer 14 and the n type semiconductor layer 12 of extension unit 10.The thickness of the electrically conducting transparent base
Range is 100 angstroms -2000 angstroms (including 100 angstroms and 2000 angstroms).For example, one in the luminescence chip of the invention is preferably shown
In example, the electrically conducting transparent base can be precipitated through but not limited to the mode of sputtering or vapor deposition in the extension unit 10,
So that the electrically conducting transparent base is laminated in the p type semiconductor layer 14 and the n type semiconductor layer of the extension unit 10
12。
Secondly, identifying etching figure in the electrically conducting transparent base using the photoresist layer for being laminated in the electrically conducting transparent base
Case, and the electrically conducting transparent base is etched by modes such as dry etching or wet etchings, so that the electrically conducting transparent base
The transparency conducting layer 20 is formed, and is formed simultaneously the first passage 21 and the second channel of the transparency conducting layer 20
22。
Finally, removal photoresist layer.It is noted that removal is laminated in the photoresist layer of the transparency conducting layer 20
Mode is unrestricted in the luminescence chip of the invention.
It is noted that the shape of the first passage 21 of the transparency conducting layer 20 shown in attached drawing 2B is circle
Scheme it is merely illustrative, but the concrete shape of the first passage 21 shown in attached drawing 2B and be not construed as to of the invention
The limitation of the content and range of the luminescence chip.
With reference to attached drawing 3A and Fig. 3 B, the passivation protection layer 30 is laminated in the transparency conducting layer 20, and the passivation
The first passage 21 of the protective layer 30 further through the transparency conducting layer 20 extends to the p-type of the extension unit 10
The semiconductor bare of semiconductor layer 14, the second channel 22 through the transparency conducting layer 20 and the extension unit 10
Portion 15 extends to the n type semiconductor layer 12 of the extension unit 10 and the edge through the extension unit 10 is exposed
Portion 16 extends to the substrate 11 of the extension unit 10.
The passivation protection layer 30 has the long pin channel 31 of a column N-type, the short pin channel 32 of an at least N-type, p-type weldering
Disk channel 33 and the long pin channel 34 of two column p-types.In the one column long pin channel 31 of N-type of the passivation protection layer 30
Each long pin channel 31 of the N-type is in a manner of being spaced apart from each other at the middle part of the passivation protection layer 30 from the luminescence chip
The second end 102 extend to 101 direction of first end, and the long pin channel 31 of each N-type is right respectively
The exposed portion 152 of the long pin of the N-type of extension unit 10 described in Ying Yu, with a part of table of the exposure n type semiconductor layer 12
Face is in the long pin channel 31 of each of the passivation protection layer 30 N-type.The short pin of the N-type of the passivation protection layer 30
Channel 32 corresponds to the exposed portion 153 of the short pin of the N-type of the extension unit 10, with the exposure n type semiconductor layer 12
A part of surface is in the short pin channel 32 of the N-type of the passivation protection layer 30.The p-type of the passivation protection layer 30 is welded
Disk channel 33 is formed in the first end 101 of the luminescence chip, wherein the p-type pad of the passivation protection layer 30
Channel 33 corresponds to the first passage 21 of the transparency conducting layer 20, with the p-type of the exposure extension unit 10 half
A part of surface of conductor layer 14 is in the p-type pad channel 33 of the passivation protection layer 30.The passivation protection layer 30
Each of long pin channel 34 of p-type described in each column long pin channel 34 of the p-type is in a manner of being spaced apart from each other in the passivation
The edge of protective layer 30 extends from the first end 101 of the luminescence chip to 102 direction of the second end, and every
A long pin channel 34 of the p-type corresponds respectively to the transparency conducting layer 20, with one of the exposure transparency conducting layer 20
Divide surface in the long pin channel 34 of each of the passivation protection layer 30 p-type.
Further, with continued reference to attached drawing 3A and Fig. 3 B, the passivation protection layer 30 further has at least a p-type is short to draw
Foot channel 35, wherein the short pin channel 35 of each p-type is adjacent with p-type pad channel 33 respectively, and each P
The short pin channel 35 of type corresponds respectively to the transparency conducting layer 20, with a part of surface of the exposure transparency conducting layer 20 in
The short pin channel 35 of each of the passivation protection layer 30 p-type.
It is noted that the material for forming the passivation protection layer 30 can be the material of insulation transparent, such as but not
It is limited to silica, silicon nitride, aluminium oxide, magnesium fluoride etc..
Specifically, the passivation protection layer 30 be laminated in the step of transparency conducting layer 20 including:
Firstly, one insulated substrate of deposition is in the transparency conducting layer 20, and the insulated substrate is allowed transparent to lead through described
The first passage 21 of electric layer 20 extends to the p type semiconductor layer 14 of the extension unit 10, through the electrically conducting transparent
The second channel 22 of layer 20 and the semiconductor bare portion 15 of the extension unit 10 extend to the extension unit 10
The n type semiconductor layer 12 and the exposed portion 16 in the edge through the extension unit 10 extend to the extension unit 10
The substrate 11.The thickness of the insulated substrate is unrestricted, such as the thickness range of the insulated substrate can
To be 600 angstroms -3000 angstroms (including 600 angstroms and 3000 angstroms).It is understood that the thickness of the passivation protection layer 30 with
The thickness of the insulated substrate is identical.
Secondly, etching pattern is identified in the electrically conducting transparent base using the photoresist layer for being laminated in the insulated substrate,
The insulated substrate is etched with by modes such as dry etching or wet etchings, so that the insulated substrate forms the passivation
Protective layer 30, and be formed simultaneously the long pin channel 31 of the N-type of the passivation protection layer 30, the short pin channel 32 of the N-type,
P-type pad channel 33, the long pin channel 34 of the p-type and the short pin channel 35 of the p-type.
Finally, removal photoresist layer.It is noted that removal is laminated in the photoresist layer of the transparency conducting layer 20
Mode is unrestricted in the luminescence chip of the invention.
With reference to attached drawing 4A and Fig. 4 B, the N-type electrode 40 and the P-type electrode 50 are respectively laminated on the passivation protection layer
30, and a part of the N-type electrode 40 is passing through each of the passivation protection layer 30 long 31 He of pin channel of the N-type
The n type semiconductor layer 12 of the extension unit 10 is electrically connected to behind each short pin channel 32 of the N-type respectively, it is described
A part of P-type electrode 50 is electrically connected to described outer behind the p-type pad channel 33 for passing through the passivation protection layer 30
Prolong the p type semiconductor layer 14 of unit 10 and passes through each of the passivation protection layer 30 long pin channel 34 of the p-type
The transparency conducting layer 20 is electrically connected to behind each short pin channel 35 of p-type.
Specifically, the N-type electrode 40 includes a N-type electrode pad 41, the long pin 42 of a N-type electrode and at least one
The short pin 43 of N-type electrode, wherein the long pin 42 of the N-type electrode pad 41, the N-type electrode and each N-type electrode are short
Pin 43 is integrally formed and is electrically connected to each other, and a part of the long pin 42 of the N-type electrode is passing through passivation guarantor
The n type semiconductor layer 12 of the extension unit 10 is electrically connected to behind the long pin channel 31 of each of sheath 30 N-type,
A part with the short pin 43 of the N-type electrode is passing through each of the passivation protection layer 30 short pin channel 32 of the N-type
It is electrically connected to the n type semiconductor layer 12 of the extension unit 10 afterwards.
More specifically, the N-type electrode pad 41 of the N-type electrode 40 is laminated in the passivation protection layer 30, that is,
The N-type electrode pad 41 of the N-type electrode 40 and the n type semiconductor layer 12 of the extension unit 10 are not electrically connected
It connects, so that the electric current injected from the N-type electrode 40 be avoided directly to enter the extension unit 10 through the N-type electrode pad 41
The n type semiconductor layer 12, and then avoid current crowding effect occur in the N-type electrode pad 41 of the N-type electrode 40
It answers.In addition, the N-type electrode pad 41 of the N-type electrode 40 is laminated in the mode of the passivation protection layer 30, so that described
The surface of the N-type electrode pad 41 of N-type electrode 40 is more smooth, in this way, can guarantee to encapsulate bonding wire
Reliability.The short pin 43 of each of the N-type electrode 40 N-type electrode is respectively laminated on the passivation protection layer 30 and is wearing
It crosses behind the short pin channel 32 of each of the passivation protection layer 30 N-type and is electrically connected to the N of the extension unit 10
Type semiconductor layer 12, in this way, when electric current can be further through each N from after the N-type electrode 40 injection
The short pin 43 of type electrode injects the n type semiconductor layer 12 of the extension unit 10 near the N-type electrode pad 41,
To avoiding while current-crowding effect occurs in the N-type electrode pad 41, the N-type electrode 40 and described outer is realized
Prolong the partially electronically conductive of the n type semiconductor layer 12 of unit 10, and then is conducive to optimize current distribution.The N-type electrode 40
The long pin 42 of N-type electrode is laminated in the passivation protection layer 30, wherein the long pin 42 of the N-type electrode is protected in the passivation
The first end 101 direction of the middle part of sheath 30 from the N-type electrode pad 41 to the luminescence chip extends, and institute
A part of the long pin 42 of N-type electrode is stated in the quilt behind each of the passivation protection layer 30 long pin channel 31 of the N-type
It is electrically connected to the n type semiconductor layer 12 of the extension unit 10.
Correspondingly, the P-type electrode 50 includes a P-type electrode pad 51, the long pin 52 of two P-type electrodes and an at least P
The short pin 53 of type electrode, wherein the P-type electrode pad 51, each long pin 52 of P-type electrode and each p-type electricity
Extremely short pin 53 is integrally formed and is electrically connected to each other, and the P-type electrode pad 51 is passing through the passivation protection layer 30
P-type pad channel 33 after be electrically connected to the p type semiconductor layer 14 of the extension unit 10, each p-type
The long pin 52 of electrode is electrically connected to institute after passing through each of the passivation protection layer 30 long pin channel 52 of the p-type respectively
Transparency conducting layer 20 is stated, each short pin 53 of P-type electrode is passing through each of the passivation protection layer 30 p-type respectively
The transparency conducting layer 20 is electrically connected to behind short pin channel 35.
Specifically, the P-type electrode pad 51 of the P-type electrode 50 is laminated in the passivation protection layer 30 and is passing through
The P-type semiconductor of the extension unit 10 is electrically connected to behind the p-type pad channel 33 of the passivation protection layer 30
Layer 14, so that further the extension can be injected through the P-type electrode pad 51 from the electric current that the P-type electrode 50 is injected
The p type semiconductor layer 14 of unit 10.In addition, the P-type electrode pad 51 of the P-type electrode 50 is through the passivation protection
The p type semiconductor layer 14 of the extension unit 10 is incorporated into behind the rounded p-type pad channel 33 of layer 30
Mode is electrically connected to the p type semiconductor layer 14, so that the surface of the P-type electrode pad 51 of the P-type electrode 50 is more
To be smooth, in this way, it can guarantee the reliability for encapsulating bonding wire.Each of the P-type electrode 50 P-type electrode
Short pin 53 is respectively laminated on the passivation protection layer 30 and is passing through each of the passivation protection layer 30 short pin of the p-type
The transparency conducting layer 20, in this way, energy are electrically connected to behind channel 35 near the P-type electrode pad 51
It is enough to improve the current injection efficiency that the electric current of the luminescence chip is injected from the P-type electrode 50, so that it is uniform to be conducive to electric current
Distribution.The long pin 52 of each of the P-type electrode 50 P-type electrode is respectively laminated on the passivation protection layer 30, wherein often
A long pin 52 of the P-type electrode is respectively at the edge of the passivation protection layer 30 from the P-type electrode pad 51 to the hair
102 direction of the second end of optical chip extends, and a part of the long pin 52 of each P-type electrode is across described
Each of passivation protection layer 30 p-type is electrically connected to the transparency conducting layer 20 behind long pin channel 34.
In a preferable examples of the luminescence chip of the invention, the N-type electrode 40 and the P-type electrode 50 can
To be formed simultaneously, that is, the N-type electrode 40 and the P-type electrode 50 can be laminated by same procedure and protected in the passivation
Sheath 30.Optionally, the N-type electrode 40 and the P-type electrode 50 are formed according to sequencing.In addition, forming the N-type electricity
The material of pole 40 and the P-type electrode 50 is unrestricted in the luminescence chip of the invention, for example, Cr, Ni, Al, Ti, Pt,
The high conductivity materials such as Au can be used for making the N-type electrode 40 and the P-type electrode 50.
It is noted that the position of the N-type electrode pad 41 of the N-type electrode 40 corresponds to the extension unit
The position in the 10 exposed portion 151 of the N-type pad；The position of the long pin 42 of the N-type electrode of the N-type electrode 40 and quantity
Correspond respectively to position and the columns in the long pin channel 31 of the N-type of the passivation protection layer 30, the passivation protection layer 30
The long pin channel 31 of the N-type position and columns correspond to the extension unit 10 the exposed portion 152 of the long pin of the N-type
Position and quantity；The position of the short pin 43 of the N-type electrode of the N-type electrode 40 and quantity correspond respectively to the passivation
The position in the short pin channel 32 of the N-type of protective layer 30 and quantity, the short pin channel of the N-type of the passivation protection layer 30
32 position and quantity correspond to position and the quantity in the exposed portion 153 of the short pin of the N-type of the extension unit 10.Accordingly
Ground, the position of the P-type electrode pad 51 of the P-type electrode 50 correspond to the p-type pad of the passivation protection layer 30
The position of the position in channel 33, the p-type pad channel 33 of the passivation protection layer 30 corresponds to the transparency conducting layer 20
The first passage 21 position；The position of the long pin 52 of the P-type electrode of the P-type electrode 50 and quantity correspond to institute
State position and the columns in the long pin channel 34 of the p-type of passivation protection layer 30；The P-type electrode of the P-type electrode 50 is short
The position of pin 53 and quantity correspond to position and the quantity in the short pin channel 35 of the p-type of the passivation protection layer 30.
Attached drawing 5A and Fig. 5 B show a variant embodiment of the luminescence chip, shown in attached drawing 1A to Fig. 4 B
It is described outer in this preferable examples of the luminescence chip shown in attached drawing 5A to Fig. 5 B unlike the luminescence chip
Prolong the semiconductor bare portion 15 tool of unit 10 there are two the exposed portion 152 of the long pin of the N-type, wherein each N-type is long
The exposed portion 152 of pin is respectively at the edge of the extension unit 10 from the exposed portion 151 of the N-type pad to the luminescence chip
101 direction of first end extends.The passivation protection layer 30 has described in the long pin channel 31 of the two column N-types and a column
The long pin channel 34 of p-type, wherein the long pin channel of each of long pin channel 31 of N-type described in each column N-type 31 is with mutual
The mode at interval is at the edge of the passivation protection layer 30 from the second end 102 of the luminescence chip to the first end
101 direction of portion extends, and one arranges each of described long pin channel 34 of p-type long pin channel 34 of the p-type to be spaced apart from each other
Mode extends from the first end 101 of the luminescence chip to 102 direction of the second end.The N-type electrode 40 is wrapped
Two long pins 42 of N-type electrode are included, each long pin 42 of N-type electrode is respectively to be laminated in the passivation protection layer 30
The first end 101 direction of the mode from the N-type electrode pad 41 to the luminescence chip at edge extend, and it is every
A long pin 42 of the N-type electrode is respectively logical across each of the long pin channel 31 of N-type described in each column long pin of the N-type
The n type semiconductor layer 12 is electrically connected to behind road 31.The P-type electrode 50 includes a long pin 52 of P-type electrode, institute
The long pin 52 of P-type electrode is stated in a manner of being laminated in the middle part of the passivation protection layer 30 from the P-type electrode pad 51 to institute
102 direction of the second end for stating luminescence chip extends, and the long pin 52 of the P-type electrode is passing through a column p-type
Each of long pin channel 34 is electrically connected to the transparency conducting layer 20 behind the long pin channel 34 of the p-type.
Attached drawing 6A and Fig. 6 B show a variant embodiment of the luminescence chip, shown in attached drawing 1A to Fig. 4 B
Unlike the luminescence chip, in this preferable examples of the luminescence chip shown in attached drawing 6A to Fig. 6 B, the N-type
Electrode 40 includes two long pins 42 of N-type electrode, wherein the long pin 42 of each N-type electrode is described to be laminated in respectively
The first end 101 side of the mode at the middle part of passivation protection layer 30 from the N-type electrode pad 41 to the luminescence chip
To extension.The P-type electrode 50 includes three long pins 52 of P-type electrode, wherein in three long pins 52 of P-type electrode
A long pin 52 of P-type electrode in a manner of being laminated in the middle part of the passivation protection layer 30 from the P-type electrode weld
Disk 51 to 102 direction of the second end of the luminescence chip extend, other two described long pin 52 of P-type electrode respectively with
It is laminated in described second of the mode at the edge of the passivation protection layer 30 from the P-type electrode pad 51 to the luminescence chip
102 direction of end extends.Preferably, the N-type electrode is maintained between the long pin 52 of the P-type electrode described in any two
Long pin 42.
Attached drawing 7A and Fig. 7 B show a variant embodiment of the luminescence chip, shown in attached drawing 1A to Fig. 4 B
Unlike the luminescence chip, in this preferable examples of the luminescence chip shown in attached drawing 7A to Fig. 7 B, the p-type
Electrode 50 includes two long pins 52 of P-type electrode, wherein the long pin 52 of each P-type electrode is described to be laminated in respectively
The second end 102 side of the mode at the middle part of passivation protection layer 30 from the P-type electrode pad 51 to the luminescence chip
To extension.The N-type electrode 40 includes three long pins 42 of N-type electrode, wherein in three long pins 42 of N-type electrode
A long pin 42 of N-type electrode in a manner of being laminated in the middle part of the passivation protection layer 30 from the N-type electrode weld
Disk 41 to 101 direction of the first end of the luminescence chip extend, other two described long pin 42 of N-type electrode respectively with
It is laminated in described first of the mode at the edge of the passivation protection layer 30 from the N-type electrode pad 41 to the luminescence chip
101 direction of end extends.Preferably, the P-type electrode is maintained between the long pin 42 of the N-type electrode described in any two
Long pin 52.
Other side under this invention, the present invention further provides the manufacturing methods of the luminescence chip, wherein described
Manufacturing method includes the following steps:
(i) N-type electrode 40 is laminated in the passivation protection layer 30, wherein the N-type electrode of the N-type electrode 40
Pad 41 is laminated in the passivation protection layer 30 in the second end 102 of the luminescence chip, and the N-type electrode 40 is prolonged
Stretch at least one described short pin 43 of N-type electrode of the N-type electrode pad 41 after passing through the passivation protection layer 30
The n type semiconductor layer 12 is electrically connected near the N-type electrode pad 41, the N-type electrode 40 extends the N
The long pin 42 of at least one of type electrode pad 41 N-type electrode is electrically connected to institute after passing through the passivation protection layer 30
State n type semiconductor layer 12；With
(ii) P-type electrode 50 is laminated in the passivation protection layer 30, wherein the p-type electricity of the P-type electrode 50
Pole pad 51 passes through the passivation protection layer 30 in the first end 101 of the luminescence chip and is electrically connected to the P
Type semiconductor layer 14, the P-type electrode is short draws at least one of the P-type electrode pad 51 of extending of the P-type electrode 50
Foot 53 is electrically connected to the transparency conducting layer near the P-type electrode pad 51 after passing through the passivation protection layer 30
20, at least one described long pin 52 of P-type electrode for extending the P-type electrode pad 51 of the P-type electrode 50 is passing through
The transparency conducting layer 20 is electrically connected to after the passivation protection layer 30.
Other side under this invention, the present invention further provides the current expansion methods of the luminescence chip, wherein
The current expansion method includes the following steps:
(a) electric current injected from the N-type electrode pad 41 is guided to be injected institute near the N-type electrode pad 41
State n type semiconductor layer 12；(b) guide the electric current injected from the P-type electrode pad 51 in the attached of the P-type electrode pad 51
The transparency conducting layer 20 closely is injected, in this way, can be avoided the electric current from the N-type electrode 40 injection in institute
The bad phenomenon that current-crowding effect occurs in N-type electrode pad 41 is stated to occur and improve what electric current was injected from the P-type electrode 50
Efficiency, to be conducive to be evenly distributed electric current, to improve the luminous efficiency and overall brightness of the luminescence chip.
It is worth noting that, " stacking " involved in the present invention can be direct stacking, it is also possible to be laminated indirectly.
For example, the n type semiconductor layer 12 of the extension unit 10, which is laminated in the substrate 11, can refer to the n type semiconductor layer
12 are directly laminated in the substrate 11, that is, the n type semiconductor layer 12 is directly grown from the surface of the substrate 11, so that
The n type semiconductor layer 12 is laminated in the substrate 11；The n type semiconductor layer 12 of the extension unit 10 is laminated in described
Substrate 11 may also mean that the n type semiconductor layer 12 is laminated in the substrate 11 indirectly, that is, in the substrate 11 and described
Other layers, such as, but not limited to buffer layer are also provided between n type semiconductor layer 12, that is, first in the substrate 11
Then surface grown buffer layer grows the n type semiconductor layer 12 on the surface of buffer layer again, so that the N-type semiconductor
Layer 12 is laminated in the substrate 11.
It is worth noting that, showing the substrate 11 of the semiconductor chip, institute in Figure of description of the invention
State n type semiconductor layer 12, the luminescent layer 13, the p type semiconductor layer 14, the transparency conducting layer 20, the passivation protection
The thickness of layer 30, the N-type electrode 40 and the P-type electrode 50 is merely illustrative, is not offered as the substrate 11, the N-type
Semiconductor layer 12, the luminescent layer 13, the p type semiconductor layer 14, the transparency conducting layer 20, the passivation protection layer 30,
The actual thickness of the N-type electrode 40 and the P-type electrode 50.Also, it is the substrate 11, the n type semiconductor layer 12, described
Luminescent layer 13, the p type semiconductor layer 14, the transparency conducting layer 20, the passivation protection layer 30,40 and of the N-type electrode
Actual proportions relationship between the P-type electrode 50 is also unlike shown in the accompanying drawings.
It will be appreciated by those skilled in the art that above embodiments are only for example, wherein the feature of different embodiments
It can be combined with each other, with the reality that the content disclosed according to the present invention is readily conceivable that but is not explicitly pointed out in the accompanying drawings
Apply mode.
It should be understood by those skilled in the art that foregoing description and the embodiment of the present invention shown in the drawings are only used as illustrating
And it is not intended to limit the present invention.The purpose of the present invention has been fully and effectively achieved.Function and structural principle of the invention exists
It shows and illustrates in embodiment, under without departing from the principle, embodiments of the present invention can have any deformation or modification.
Claims (18)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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