CN109461468B - Data stability detection method - Google Patents
Data stability detection method Download PDFInfo
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- CN109461468B CN109461468B CN201811355317.1A CN201811355317A CN109461468B CN 109461468 B CN109461468 B CN 109461468B CN 201811355317 A CN201811355317 A CN 201811355317A CN 109461468 B CN109461468 B CN 109461468B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
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Abstract
The embodiment of the application discloses a data stability detection method and related equipment, which are used for saving the processing time of data stability detection in a memory and improving the user experience. The method in the embodiment of the application comprises the following steps: in the embodiment, data to be stored is acquired; transmitting the data to be stored to the memory; sending a read status instruction to the memory; receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction; and determining the storage state of the data in the memory according to the state value. Therefore, the storage state of the data in the memory is determined according to the state value, and compared with the comparison and verification in the prior art that all data are read in the ECC verification process, the processing time of data stability detection in the memory is saved, and the user experience is improved.
Description
Technical Field
The present application relates to the field of communications, and in particular, to a data stability detection method.
Background
The Nand-flash memory is one of flash memories, and a nonlinear macro-unit mode is adopted in the Nand-flash memory, so that a cheap and effective solution is provided for realizing a solid-state large-capacity memory. The Nand-flash memory has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied in the industry, for example, embedded products comprise a digital camera, an MP3 walkman memory card, a small-sized U-disk and the like.
With the rapid development of storage technology and the popularization and application of large data, large-capacity NandFlash is more and more popular, and particularly, 3D TLC NandFlash is most widely applied. Generally, a large-capacity U disk, EMMC, SSD uses 3D TLC NandFlash as a storage medium, so that higher requirements are made on the stability of the stored data of the Flash. The NAND type flash memory performs an erase operation in units of blocks. The writing operation of the flash memory must be performed in a blank area, and if the target area has data, the data must be written after being erased, so the erasing operation is the basic operation of the flash memory.
In the prior art, the current data stability detection algorithm for the NandFlash Memory is performed by reading out programmed data to perform ECC (error correction Code) check, and the result of ECC check can only be known after all data DMA (Direct Memory Access) in the NandFlash Memory is obtained.
However, in the detection method, ECC verification needs to read all data for comparison and verification, which results in a large increase of detection time, and has a great influence on the write speed of the usb disk, EMMC, and SSD, which not only reduces user experience, but also causes a timeout if the verification time is too long in some devices requiring a high data write speed, thereby causing a compatibility problem.
Disclosure of Invention
The embodiment of the application provides a data stability detection method and related equipment, which are used for saving the processing time of data stability detection in a memory and improving the user experience.
A first aspect of an embodiment of the present application provides a data stability detection method, including:
acquiring data to be stored;
transmitting the data to be stored to the memory;
sending a read status instruction to the memory;
receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction;
and determining the storage state of the data in the memory according to the state value.
Optionally, before sending the read status instruction to the memory, the method further comprises:
sending a programming instruction to the memory to acquire an RB signal;
and when the RB signal is determined to be changed from the low level to the high level, sending a read state instruction to the memory is executed.
Optionally, the transmitting the data to be stored to the memory includes:
controlling the memory to enter a programming mode;
and DMA (direct memory access) the data to be stored to the memory.
Optionally, before transmitting the data to be backed up to the memory, the method further includes:
and backing up and storing the data to be stored.
Optionally, the data to be stored includes a first data block and a second data block; after determining the storage state of the data in the memory according to the state value, the method further comprises:
if the storage status indicates that the first data block is correct and the second data block is not written, transmitting the second data block to the memory;
sending a target read status instruction to the memory;
receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
and determining the storage state of the second data block in the memory according to the target state value.
A second aspect of the embodiments of the present application provides a data stability detection system, including:
the device comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for acquiring data to be stored;
the first transmission unit is used for transmitting the data to be stored to the memory;
a first sending unit, configured to send a read status instruction to the memory;
the first receiving unit is used for receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction;
and the first determining unit is used for determining the storage state of the data in the memory according to the state value.
Optionally, the system further comprises:
the second sending unit is used for sending a programming instruction to the memory and acquiring an RB signal;
and the execution unit is used for executing sending a read state instruction to the memory when the RB signal is determined to be changed from the low level to the high level.
Optionally, the transmission unit is specifically configured to:
controlling the memory to enter a programming mode;
and DMA (direct memory access) the data to be stored to the memory.
Optionally, the system further comprises:
and the backup unit is used for backing up and storing the data to be stored.
Optionally, the data to be stored includes a first data block and a second data block; the system further comprises:
a second transmission unit, configured to transmit the second data block to the memory if the storage status indicates that the first data block is correct and the second data block is not written in;
a third sending unit, configured to send a target read status instruction to the memory;
the second receiving unit is used for receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
and the second determining unit is used for determining the storage state of the second data block in the memory according to the target state value.
A third aspect of embodiments of the present application provides a computer apparatus, including:
a processor, a memory, an input-output device, and a bus;
the processor, the memory and the input and output equipment are respectively connected with the bus;
the processor is configured to perform the method according to the foregoing embodiments.
A fourth aspect of embodiments of the present application provides a computer-readable storage medium having stored thereon a computer program: which when executed by a processor implements the steps of the method according to the previous embodiment.
According to the technical scheme, the embodiment of the application has the following advantages: in the embodiment, data to be stored is acquired; transmitting the data to be stored to the memory; sending a read status instruction to the memory; receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction; and determining the storage state of the data in the memory according to the state value. Therefore, the storage state of the data in the memory is determined according to the state value, and compared with the comparison and verification in the prior art that all data are read in the ECC verification process, the processing time of data stability detection in the memory is saved, and the user experience is improved.
Drawings
Fig. 1 is a schematic diagram illustrating an embodiment of a data stability detection method according to an embodiment of the present application;
FIG. 2 is another schematic diagram of an embodiment of a data stability detection method according to the present application;
FIG. 3 is another schematic diagram of an embodiment of a data stability detection method according to the present application;
FIG. 4 is another schematic diagram of an embodiment of a data stability detection method according to the present application;
FIG. 5 is another schematic diagram of an embodiment of a data stability detection method according to the present application;
FIG. 6 is a diagram illustrating an embodiment of a data stability detection system according to an embodiment of the present application;
fig. 7 is a schematic diagram of a computer device according to an embodiment of the present application.
Detailed Description
The embodiment of the application provides a data stability detection method and related equipment, which are used for saving the processing time of data stability detection in a memory and improving the user experience.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
For convenience of understanding, a specific flow in the embodiment of the present application is described below, and referring to fig. 1, an embodiment of a data stability detection method in the embodiment of the present application includes:
101. acquiring data to be stored;
in this embodiment, the terminal acquires the data to be stored, that is, confirms the data to be stored that needs to be transmitted to the data storage.
Specifically, the embodiment can be applied to the processing of the NandFlash data memory, that is, the NandFlash data memory is connected with a terminal and used for detecting the stability of data in the memory. The terminal may be a personal computer, a notebook, a server, or a mobile phone terminal, and is not limited specifically herein. The NandFlash data memory may be a 3D TLC NandFlash data memory, a QLC NandFlash data memory, or other forms of NandFlash data memory, which is not limited herein.
102. Transmitting the data to be stored to the memory;
in this embodiment, the terminal transmits the data to be stored obtained in step 101 to the memory.
Specifically, the transmission may be performed in various manners, such as in the form of SPI (Serial Peripheral Interface), DMA (Direct memory access), or other manners, which are not limited herein.
103. Sending a read status instruction to the memory;
in this embodiment, the terminal sends a read status instruction to the memory.
Specifically, the read status instruction may be a one-byte instruction (e.g., 0x70), and after the instruction is issued, the memory generates a one-byte status value according to the instruction.
104. Receiving the state value sent by the memory;
in this embodiment, the terminal receives the state value sent by the memory, where the state value is generated by the memory according to the read state instruction.
105. And determining the storage state of the data in the memory according to the state value.
In this embodiment, the state value is a state value of one byte generated by the memory according to the instruction in step 103, where each state value has a different meaning, and therefore, the terminal finds the state value indicating the storage state from the state values. And determining the storage state of the data in the memory according to the state value. Compared with the prior art that the data is read completely and then compared and verified, the embodiment can save the processing time to a greater extent.
In the embodiment, data to be stored is acquired; transmitting the data to be stored to the memory; sending a read status instruction to the memory; receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction; and determining the storage state of the data in the memory according to the state value. Therefore, the storage state of the data in the memory is determined according to the state value, and compared with the comparison and verification in the prior art that all data are read in the ECC verification process, the processing time of data stability detection in the memory is saved, and the user experience is improved.
In this embodiment, based on the embodiment shown in fig. 1, before the step 103 sends the read status instruction to the memory, it may be specifically determined whether to complete data writing to determine whether to execute the step 103, that is, whether to execute sending the read status instruction to the memory. Referring to fig. 2, based on the embodiment shown in fig. 1, before step 103, another embodiment of a data stability detection method in the embodiment of the present application includes:
201. sending a programming instruction to the memory to acquire an RB signal;
in this embodiment, specifically, in the process of transmitting the data to be stored to the memory in step 102, the corresponding data page to be transmitted is determined, and then a programming instruction is sent to the corresponding data page in the memory to acquire the RB signal.
202. And when the RB signal is determined to be changed from the low level to the high level, sending a read state instruction to the memory is executed.
In this embodiment, when it is determined that the RB signal obtained in step 201 changes from low level to high level, that is, it is determined that the corresponding data page in step 201 has been programmed, a read status command is sent to the memory. That is, when the RB signal is confirmed to be high, step 103 is performed again to avoid a data transmission error.
In this embodiment of the application, based on the embodiment described in fig. 1 or fig. 2, there may be a plurality of ways to transfer the data to be stored to the memory in step 102, and the DMA transfer way is described below. Referring to fig. 3, based on the embodiment shown in fig. 1 or fig. 2, in a specific implementation manner of step 102, another embodiment of a data stability detection method in the embodiment of the present application includes:
301. controlling the memory to enter a programming mode;
in this embodiment, when data is transferred to the memory in the DMA format, the memory needs to be controlled to enter the programming mode first, and the subsequent steps are executed after the data is initialized. The program may be an SLC program mode, a TLC program mode, or another program mode, and is not limited herein, and in a specific implementation process of the scheme, the switching may be performed by a preset standard command.
302. And DMA (direct memory access) the data to be stored to the memory.
In this embodiment, the terminal DMA-stores the data to be stored into the memory.
In particular, a DMA transfer copies data from one address space to another. When the CPU initiates this transfer, the transfer itself is performed and completed by the DMA controller. A typical example is to move a block of external memory to a faster memory area inside the chip. Such operations do not stall the processor's work, but instead can be rescheduled to handle other work, thus greatly increasing I/O speed since the DMA module avoids data transfers between the Northbridge and the CPU.
In this embodiment of the application, based on the embodiment described in fig. 1, fig. 2, or fig. 3, specifically, before the data to be backed up is transmitted to the memory in step 102, the data to be stored may also be backed up, so as to ensure safe storage of the data. Referring to fig. 4, based on the embodiment described in fig. 1, fig. 2 or fig. 3, another embodiment of a data stability detection method in the embodiment of the present application includes, at step 102:
401. and backing up and storing the data to be stored.
In this embodiment, the terminal performs backup storage on the data to be stored acquired and confirmed in step 101.
Specifically, the backup process is performed to save the original data, and in this embodiment, the original data is discarded after the memory has been accepted, so that the backup storage of the data to be stored may be performed first before step 102 to retrieve the data later.
In this embodiment of the present application, in the embodiments of fig. 1 to fig. 4, the data to be stored may include a first data block and a second data block, and specifically, after determining the storage state of the data in the memory according to the state value after step 105, the integrity of data transmission may be further implemented for the first data block and the second data block. Referring to fig. 5, based on the embodiments of fig. 1 to 4, after step 105, another embodiment of a data stability detection method in the embodiment of the present application includes:
501. if the storage status indicates that the first data block is correct and the second data block is not written, transmitting the second data block to the memory;
in this embodiment, if the storage status indicates that the first data block is correct and the second data block is not written, the terminal transmits the second data block to the memory.
Specifically, the data to be stored may exist in various forms in the memory, and when the number of data is large, the data may be stored by a plurality of data blocks. In this embodiment, for example, a first data block and a second data block may be included, so that after the storage status is obtained in step 105, when the storage status indicates that the first data block is correct and the second data block is not written, the second data block may be transferred to the memory.
502. Sending a target read status instruction to the memory;
503. receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
504. and determining the storage state of the second data block in the memory according to the target state value.
In this embodiment, steps 502 to 504 are similar to steps 103 to 105, and are not described herein again.
In addition, if there is a lot of data to be stored, the second data block in this embodiment may include a plurality of data blocks, that is, storage detection (i.e., loop operation) of the plurality of data blocks may be performed in the manner of this embodiment, and a specific implementation process is similar to this embodiment.
While the embodiments of the present application have been described above in terms of method steps, the embodiments of the present application are described below in terms of virtual devices, and referring to fig. 6, in an embodiment of the present application, an embodiment of a data stability detection system includes:
an obtaining unit 601, configured to obtain data to be stored;
a first transmission unit 602, configured to transmit the data to be stored to the memory;
a first sending unit 603, configured to send a read status instruction to the memory;
a first receiving unit 604, configured to receive a state value sent by the memory, where the state value is generated by the memory according to the read state instruction;
a first determining unit 605, configured to determine a storage state of the data in the memory according to the state value.
In this embodiment, the obtaining unit 601 is configured to obtain data to be stored; a first transmission unit 602, configured to transmit the data to be stored to the memory; a first sending unit 603, configured to send a read status instruction to the memory; a first receiving unit 604, configured to receive a state value sent by the memory, where the state value is generated by the memory according to the read state instruction; a first determining unit 605, configured to determine a storage state of the data in the memory according to the state value. Therefore, the storage state of the data in the memory is determined according to the state value, and compared with the comparison and verification in the prior art that all data are read in the ECC verification process, the processing time of data stability detection in the memory is saved, and the user experience is improved.
As a preferred scheme, the system further comprises:
the second sending unit is used for sending a programming instruction to the memory and acquiring an RB signal;
and the execution unit is used for executing sending a read state instruction to the memory when the RB signal is determined to be changed from the low level to the high level.
As a preferred scheme, the transmission unit is specifically configured to:
controlling the memory to enter a programming mode;
and DMA (direct memory access) the data to be stored to the memory.
As a preferred scheme, the system further comprises:
and the backup unit is used for backing up and storing the data to be stored.
As a preferred scheme, the data to be stored comprises a first data block and a second data block; the system further comprises:
a second transmission unit, configured to transmit the second data block to the memory if the storage status indicates that the first data block is correct and the second data block is not written in;
a third sending unit, configured to send a target read status instruction to the memory;
the second receiving unit is used for receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
and the second determining unit is used for determining the storage state of the second data block in the memory according to the target state value.
Referring to fig. 7, a computer device in an embodiment of the present application is described below from the perspective of a physical device, where an embodiment of the computer device in the embodiment of the present application includes:
the computing device 700 may have a relatively large difference due to different configurations or performances, and may include one or more Central Processing Units (CPUs) 701 (e.g., one or more processors) and a memory 705, where the memory 705 stores one or more applications or data.
The memory 705 may be volatile storage or persistent storage, among others. The program stored in the memory 705 may include one or more modules, each of which may include a sequence of instructions operating on a server. Still further, the central processor 701 may be configured to communicate with the memory 705, and to execute a series of instruction operations in the memory 705 on the smart terminal 700.
The computer device 700 may also include one or more power supplies 702, one or more wired or wireless network interfaces 703, one or more input-output interfaces 704, and/or one or more operating systems, such as Windows Server, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM, and the like.
The processor 701 is specifically configured to perform the following steps:
acquiring data to be stored;
transmitting the data to be stored to the memory;
sending a read status instruction to the memory;
receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction;
and determining the storage state of the data in the memory according to the state value.
As a preferred solution, before sending the read status instruction to the memory, the method further includes:
sending a programming instruction to the memory to acquire an RB signal;
and when the RB signal is determined to be changed from the low level to the high level, sending a read state instruction to the memory is executed.
As a preferred scheme, the transmitting the data to be stored to the memory comprises:
controlling the memory to enter a programming mode;
and DMA (direct memory access) the data to be stored to the memory.
As a preferred solution, before transmitting the data to be backed up to the memory, the method further includes:
and backing up and storing the data to be stored.
As a preferred scheme, the data to be stored comprises a first data block and a second data block; after determining the storage state of the data in the memory according to the state value, the method further comprises:
if the storage status indicates that the first data block is correct and the second data block is not written, transmitting the second data block to the memory;
sending a target read status instruction to the memory;
receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
and determining the storage state of the second data block in the memory according to the target state value.
It should be understood that, in the various embodiments of the present application, the sequence numbers of the above steps do not mean the execution sequence, and the execution sequence of the steps should be determined by their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.
Claims (7)
1. A data stability detection method is characterized by comprising the following steps:
acquiring data to be stored;
transmitting the data to be stored to a memory;
sending a read status instruction to the memory;
receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction;
determining the storage state of the data in the memory according to the state value;
transmitting the data to be stored to a memory comprises:
controlling the memory to enter a programming mode;
DMA the data to be stored to the memory;
the data to be stored comprises a first data block and a second data block; after determining the storage state of the data in the memory according to the state value, the method further comprises:
if the storage status indicates that the first data block is correct and the second data block is not written, transmitting the second data block to the memory;
sending a target read status instruction to the memory;
receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
and determining the storage state of the second data block in the memory according to the target state value.
2. The method of claim 1, wherein prior to sending a read status instruction to the memory, the method further comprises:
sending a programming instruction to the memory to acquire an RB signal;
and when the RB signal is determined to be changed from the low level to the high level, sending a read state instruction to the memory is executed.
3. The method according to any one of claims 1 to 2, wherein prior to transferring the data to be stored to memory, the method further comprises:
and backing up and storing the data to be stored.
4. A data stability detection system, comprising:
the device comprises an acquisition unit, a storage unit and a processing unit, wherein the acquisition unit is used for acquiring data to be stored;
the first transmission unit is used for transmitting the data to be stored to a memory;
a first sending unit, configured to send a read status instruction to the memory;
the first receiving unit is used for receiving a state value sent by the memory, wherein the state value is generated by the memory according to the read state instruction;
the first determining unit is used for determining the storage state of the data in the memory according to the state value;
when the first transmission unit transmits the data to be stored to the memory, the first transmission unit is specifically configured to:
controlling the memory to enter a programming mode;
DMA the data to be stored to the memory;
the data to be stored comprises a first data block and a second data block; the system further comprises:
a second transmission unit, configured to transmit the second data block to the memory if the storage status indicates that the first data block is correct and the second data block is not written in;
a third sending unit, configured to send a target read status instruction to the memory;
the second receiving unit is used for receiving a target state value sent by the memory, wherein the target state value is generated by the memory according to the target reading state instruction;
and the second determining unit is used for determining the storage state of the second data block in the memory according to the target state value.
5. The system of claim 4, further comprising:
the second sending unit is used for sending a programming instruction to the memory and acquiring an RB signal;
and the execution unit is used for executing sending a read state instruction to the memory when the RB signal is determined to be changed from the low level to the high level.
6. A computer device, comprising:
a processor, a memory, an input-output device, and a bus;
the processor, the memory and the input and output equipment are respectively connected with the bus;
the processor is configured to perform the method of any one of claims 1 to 3.
7. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program realizing the steps of the method according to any one of claims 1 to 3 when executed by a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811355317.1A CN109461468B (en) | 2018-11-14 | 2018-11-14 | Data stability detection method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811355317.1A CN109461468B (en) | 2018-11-14 | 2018-11-14 | Data stability detection method |
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| Publication Number | Publication Date |
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| CN109461468A CN109461468A (en) | 2019-03-12 |
| CN109461468B true CN109461468B (en) | 2021-05-11 |
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