CN104617005B - The measuring method of channel region strain - Google Patents

Abstract

A method for measuring strain in a channel region, comprising: providing a plurality of device regions; forming a transistor to be tested of the same conductivity type in each device region, and the transistor to be tested includes an ion implantation region located in a semiconductor substrate and an adjacent In the channel region between the two ion implantation regions, the structure of the ion implantation region of the transistor to be tested in different device regions is different; the ultraviolet light spot is used to irradiate each device region in turn, and the ion implantation of the transistor to be tested in each device region is obtained. The total Raman spectrum returned by the region and the channel region; according to the different total Raman spectra returned by the transistor to be tested in different device regions, the Raman spectrum of the channel region is separated, and the strain amount of the channel region is obtained. The channel region strain measured by the method is real and accurate, and the whole method is simple and feasible, saves cost, does not damage the transistor, has a large spectral range, and the frequency shift is not limited by the frequency of the light source, and has a wide application range.

Description

Measurement method of strain in channel region

technical field

The invention relates to the field of semiconductor technology, in particular to a method for measuring strain in a channel region.

Background technique

With the rapid development of nanofabrication technology, the feature size of transistors has entered the nanoscale. Improving the performance of current mainstream silicon CMOS devices by scaling down is subject to more and more physical and technological limitations. In order to enable integrated circuit technology to continue the development speed revealed by Moore's Law, new materials, new structures and new properties compatible with silicon technology must be developed. In recent years, strained silicon (Strained Si) technology has attracted much attention due to its excellent performance in improving the performance of CMOS devices. For example, the hole mobility of PMOS and the electron mobility of NMOS can be improved respectively by introducing appropriate compressive stress and tensile stress in the channel. Typical PMOS strained silicon devices can introduce channel compressive stress through epitaxial SiGe source and drain, and use the source-drain and channel lattice constant mismatch to control the strain, thereby improving hole mobility; while for NMOS strained silicon devices, it can be achieved by The deposited SiN film introduces channel tensile stress, and the high intrinsic stress of the SiN film is used to control the strain, thereby improving electron mobility. Therefore, it is of great scientific significance and practical value to study the control of stress and strain in semiconductor nanodevices through the optimal design of process, material and structural parameters.

In order to prevent the generation of gate leakage current, a transistor with a high-K dielectric layer and a metal gate structure (HKMG) has been proposed. In this type of transistor, the channel region is located under the metal gate. How to measure the strain of the channel region of this type of transistor , is a technical problem encountered in this field.

Accurate measurement of local microstress and strain in (ultra)deep submicron semiconductor structures usually must rely on complex microstructural analysis and measurement methods. As a part of the strain distribution of nano-semiconductor devices, channel region strain is very difficult to measure experimentally, both technically and in terms of cost. On the one hand, the process requirements for making such devices are very high and the investment is expensive, and it is unlikely that the finished devices will be destructively measured one by one; Superb microstructure analysis and measurement methods.

A technique that can be applied to channel region strain measurement is Convergent Beam Electron Difraction (CBED). Spotlight electron diffraction has high spatial resolution (spatial resolution as high as 5nm to 10nm) and strain measurement accuracy, and is currently more widely used in strain measurement of nanometer-sized CMOS devices, but this method is destructive to the sample (must be tested The sample is carefully thinned until the measurement area is electron-transparent, which is suitable for transmission electron microscopy analysis), and the transmission electron microscope (TEM) equipped with spotlight electron diffraction function is quite expensive, and the operation and analysis are also relatively complicated. It is very difficult to keep the original channel strain state unaffected by thinning during the preparation of electron microscope specimens. Therefore, the reliability of the final measurement results is controversial.

Another technique that can be applied to strain measurement in the channel region is Micro-Raman Scattering (Micro-Raman Scattering) technique. Raman scattered light reflects the information of the vibration energy level of the material lattice, so it can reflect the information of the material element composition, lattice quality, molecular structure and other aspects. The microscopic basis of measuring strain by Raman spectroscopy is that the Raman frequency shift reflects the change in the distance between atoms, that is, it reflects the information of strain. However, although the existing Raman scattering is non-destructive, its spatial resolution is only 0.2 μm to 1 μm, which cannot be applied to the strain measurement of submicron, especially ultra-deep submicron devices.

For this reason, a new method for measuring channel region strain is needed to solve the problem that existing methods cannot accurately measure channel region strain.

Contents of the invention

The problem to be solved by the present invention is to provide a method for measuring the strain in the channel region to accurately measure the strain in the channel region.

In order to solve the above problems, the present invention provides a method for measuring channel strain, including:

providing a semiconductor substrate comprising a plurality of device regions;

A transistor to be tested of the same conductivity type is formed in each device region, and the transistor to be tested includes an ion implantation region located in the semiconductor substrate and a channel region located between two adjacent ion implantation regions, and the transistor to be tested in different device regions The structure of the ion implantation area is different;

Irradiate each device region sequentially with ultraviolet light spots, and obtain the total silicon-silicon bond Raman spectrum returned by the ion implantation region and the channel region of the transistor to be tested in each device region;

According to the different total silicon-silicon bond Raman spectra returned by the transistor to be tested in different device regions, the silicon-silicon bond Raman spectrum of the channel region is separated, and the strain amount of the channel region is obtained.

Optionally, the channel region is located in a silicon substrate, the ion implantation region is made of silicon germanium, and the total Raman spectrum is a total silicon-silicon bond Raman spectrum.

Optionally, the device region includes a first region, a second region, a third region and a fourth region, the transistor to be tested is a PMOS transistor, and the ion implantation region is made of sigma-shaped silicon germanium, wherein:

The PMOS transistor located in the first region returns a first total silicon-silicon bond Raman spectrum, and metal silicide is formed on the surface of the ion implantation region, and ion implantation is performed inside;

The PMOS transistor located in the second region returns a second total silicon-silicon bond Raman spectrum, no metal silicide is formed on the surface of the ion implantation region, and ion implantation is performed inside;

The PMOS transistor located in the third region returns a third total silicon-silicon bond Raman spectrum, and metal silicide is formed on the surface of the ion implantation region, and ion implantation is not performed inside;

The PMOS transistor located in the fourth region returns a fourth total silicon-silicon bond Raman spectrum, no metal silicide is formed on the surface of the ion implantation region, and no ion implantation is performed inside.

Optionally, the area of the first region, the second region, the third region and the fourth region ranges from 5 μm ² to 50 μm ² , and the area of the ultraviolet light spot is that of the first region, the second region, the fourth region 30% to 80% of the third area or the fourth area.

Optionally, the device region includes a fifth region, a sixth region, a seventh region and an eighth region connected in sequence, the transistor to be tested is a PMOS transistor, and the ion implantation region is made of sigma-shaped silicon germanium ,in:

In the PMOS transistor located in the fifth region, a metal silicide is formed on the surface of the ion implantation region, and ion implantation is performed inside;

In the PMOS transistor located in the sixth region, the surface of the ion implantation region gradually transitions from metal silicide formed to no metal silicide formed, and ion implantation is performed inside;

In the PMOS transistor located in the seventh region, a metal silicide is formed on the surface of the ion implantation region, and the interior gradually transitions from ion implantation to non-ion implantation;

In the PMOS transistor located in the eighth region, no metal silicide is formed on the surface of the ion implantation region, and no ion implantation is performed inside;

When the ultraviolet light spot is used to irradiate the transistor to be tested, the ultraviolet light spot scans and irradiates the fifth area, the sixth area, the seventh area and the eighth area sequentially or in reverse order, and the returned series of different Raman spectroscopy of total silicon-silicon bonds.

Optionally, the PMOS transistors located in the fifth region, the sixth region, the seventh region and the eighth region are formed by controlling the mask for ion implantation and the mask for forming the metal silicide.

Optionally, the area of the fifth region, the sixth region, the seventh region and the eighth region ranges from 5 μm ² to 50 μm ² , and the area of the ultraviolet light spot is the fifth region, the sixth region, the seventh region 30%-80% of the seventh region or the eighth region, the width of the channel region is greater than or equal to the width of the ultraviolet light spot.

Optionally, the wavelength range of the ultraviolet light in the ultraviolet light spot is 350nm-400nm.

Optionally, there is a trench above the channel region of the transistor to be tested, and the bottom of the trench has at least one of a gate oxide layer and a high-K dielectric layer above the channel region, and the ultraviolet The light spot reaches the channel region through the groove.

Optionally, the sidewall of the trench has offset spacers and sidewalls, and the transistor to be tested further includes a stress mask layer, and the stress mask layer is located between the ion implantation region and the dielectric layer between the side walls and the medium layer.

Optionally, the metal silicide is a metal silicide of nickel, the thickness of the metal silicide ranges from 1 nm to 15 nm, and the ions implanted in the ion implantation region include phosphorus ions, arsenic ions, boron ions and gallium ions One or more of the ions, the ion concentration ranges from 10 ¹⁷ cm ^-3 to 10 ²⁰ cm ^-3 .

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the technical solution of the present invention, the transistor to be measured is firstly provided. The transistor is in the process of manufacture, and no metal gate is formed. At this time, the transistor is irradiated with a spot of ultraviolet light, and returned to the transistor by channel region and ion implantation. The total Raman spectrum returned by the region, according to the different total Raman spectra returned by different transistors, the Raman spectrum returned by the channel region is separated, and then the Raman spectrum returned by the channel region and the strained channel region returned to zero Compare and analyze the Raman spectrum of the method to obtain the strain in the channel region. The strain in the channel region measured by the method is true and accurate, and the whole method is simple and feasible, saves cost, has no damage to the transistor, has a large spectral range, and does not shift frequency. Limited by the frequency of the light source, it has a wide range of applications.

Description of drawings

FIG. 1 is a schematic diagram of a PMOS transistor in a first region according to Embodiment 1 of the present invention;

2 is a schematic diagram of a PMOS transistor in a second region according to Embodiment 1 of the present invention;

3 is a schematic diagram of a PMOS transistor in a third region according to Embodiment 1 of the present invention;

4 is a schematic diagram of a PMOS transistor in a fourth region according to Embodiment 1 of the present invention;

5 is a schematic diagram of masks used in the metal silicide fabrication process and ion implantation process in the first region, the second region, the third region and the fourth region according to Embodiment 1 of the present invention;

6 is a schematic top view of PMOS transistors in the first region, the second region, the third region and the fourth region according to Embodiment 1 of the present invention;

Fig. 7 is a schematic diagram of the total silicon-silicon bond Raman spectra returned in the first region, the second region, the third region and the fourth region according to the embodiment of the present invention;

FIG. 8 is a schematic diagram of a PMOS transistor in the fifth region of Embodiment 2 of the present invention;

FIG. 9 is a schematic diagram of a PMOS transistor in the sixth region of the second embodiment of the present invention;

FIG. 10 is a schematic diagram of a PMOS transistor in the seventh region of Embodiment 2 of the present invention;

FIG. 11 is a schematic diagram of a PMOS transistor in the eighth region of the second embodiment of the present invention;

12 is a schematic diagram of the masks used in the fifth, sixth, seventh and eighth regions in the metal silicide fabrication process and ion implantation process in the second embodiment of the present invention;

13 is a schematic diagram of the fifth region, the sixth region, the seventh region and the eighth region in the metal silicide fabrication process and the ion implantation process in the second embodiment of the present invention.

detailed description

Micro-Raman scattering technology is divided into static micro-Raman scattering (Static Micro-Raman Scattering) technology and scanning micro-Raman scattering technology (Scanning Micro-Raman Scattering). The spot area used by the static micro-Raman scattering technique cannot be smaller than 1 μm ² , so the static Raman scattering technique cannot be directly used to measure the strain in the channel region. Theoretically, the scanning micro-Raman scattering technique can achieve higher spatial resolution through the scanning differential signals returned at different scanning moments, but in fact, for submicron, especially ultra-deep submicron devices, the corresponding scanning differential signal It is too weak to measure the strain in the channel region. In addition, no matter what kind of Raman scattering technology is used, for a transistor with a high-K dielectric layer and a metal gate structure, since the channel region is located under the metal gate, the metal gate will prevent light from reaching the channel region, so it is difficult to Strain in the channel region is measured using existing methods.

To this end, the present invention provides a method for measuring the strain of the channel region, providing a transistor to be tested, and in the transistor, the fabrication is not completely completed, but stays before the formation of the metal gate, and at this time there is only a high K The dielectric layer and the gate oxide layer, and the high-K dielectric layer and the gate oxide layer do not affect the ultraviolet light to pass through the channel region, therefore, the ultraviolet light spot can irradiate the channel region of the transistor to be tested through the groove, and obtain the ions The total Raman spectrum returned by the injection region and the channel region, and then analyzed according to the different total Raman spectra returned by the transistor to be tested in different device regions to obtain the Raman spectrum returned by the channel region, and the channel region The Raman spectrum returned by the region is compared and analyzed with the Raman spectrum returned by the channel region whose strain is zero, to obtain the strain of the channel region.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Embodiment 1 of the present invention provides a method for measuring strain in a channel region.

First, multiple device regions are provided.

In this embodiment, the device area includes a first area, a second area, a third area, and a fourth area, and the transistor to be tested is a PMOS transistor in the manufacturing process, that is, the transistor to be tested is a transistor that has not been completely fabricated. . Since what is to be measured in this embodiment is a PMOS transistor with a high-K dielectric layer and a metal gate structure, if the PMOS transistor is fabricated, the metal gate will shield the corresponding light from reaching the channel region, resulting in the inability to control the channel region. The consequences of measuring the strain, and using this incomplete transistor to ensure accurate measurement results.

In this embodiment, the PMOS transistor is at the moment when the dummy gate is removed to form a trench, because the dummy gate is usually polysilicon, and polysilicon has a complex crystal plane and grain boundary structure, which will adversely affect the ultraviolet light reaching the channel region. Therefore, in this embodiment, the dummy gate of the polysilicon is removed to form a trench, and subsequent ultraviolet light can pass through the trench to reach the channel region.

In this embodiment, the PMOS transistors are respectively located in the first region, the second region, the third region and the fourth region, and the structures of the ion implantation regions of the PMOS transistors in different device regions are different.

Please refer to FIG. 1 , the PMOS transistor located in the first region includes an ion implantation region (not marked) and a channel region 111 (the region enclosed by the dotted line box in FIG. 1 ) located in the semiconductor substrate 100 , located in the semiconductor substrate 100 The upper interlayer dielectric layer 101 is located in the trench 110 in the interlayer dielectric layer 101. The trench 110 corresponds to the top of the channel region 111. The bottom of the trench 110 has a gate oxide layer 112 on the channel region 111 and a high-K The dielectric layer 113 , the sidewall of the trench 110 has an offset spacer 114 and a sidewall 115 , and the surface of the sidewall 115 and the surface of the ion implantation region are covered by the stress mask layer 116 . Sigma silicon germanium 117 is fabricated in the ion implantation region.

In this embodiment, in the PMOS transistor located in the first region, a metal silicide 119 is formed on the surface of the ion implantation region, and ion implantation is performed inside to form an ion re-implantation region 118 .

Please refer to FIG. 2 , the PMOS transistor located in the second region includes an ion implantation region (not labeled) located in the semiconductor substrate 200 and a channel region 211 (the region enclosed by the dotted line box in FIG. 2 ), located in the semiconductor substrate 200 The upper interlayer dielectric layer 201 is located in the trench 210 in the interlayer dielectric layer 201. The trench 210 corresponds to the top of the channel region 211. The bottom of the trench 210 has a gate oxide layer 212 on the channel region 211 and a high K The dielectric layer 213 , the sidewall of the trench 210 has an offset spacer 214 and a sidewall 215 , and the surface of the sidewall 215 and the surface of the ion implantation region are covered by the stress mask layer 216 . Sigma silicon germanium 217 is fabricated in the ion implantation region.

In this embodiment, in the PMOS transistor located in the second region, metal silicide is not formed on the surface of the ion implantation region, but ion implantation is performed inside, forming the ion re-implantation region 218 .

Please refer to FIG. 3 , the PMOS transistor located in the third region includes an ion implantation region (not marked) and a channel region 311 (the region enclosed by the dotted line box in FIG. 3 ) located in the semiconductor substrate 300 The upper interlayer dielectric layer 301 is located in the trench 310 in the interlayer dielectric layer 301. The trench 310 corresponds to the top of the channel region 311. The bottom of the trench 310 has a gate oxide layer 312 on the channel region 311 and a high K The dielectric layer 313 , the sidewall of the trench 310 has an offset spacer 314 and a sidewall 315 , and the surface of the sidewall 315 and the surface of the ion implantation region are covered by a stress mask layer 316 . Sigma silicon germanium 317 is formed in the ion implantation region.

In this embodiment, in the PMOS transistor located in the third region, the metal silicide 318 is formed on the surface of the ion implantation region, but no ion implantation is performed inside.

Please refer to FIG. 4 , the PMOS transistor located in the fourth region includes an ion implantation region (not labeled) located in the semiconductor substrate 400 and a channel region 411 (the region enclosed by the dotted line box in FIG. 4 ), located in the semiconductor substrate 400 The upper interlayer dielectric layer 401 is located in the trench 410 in the interlayer dielectric layer 401. The trench 410 corresponds to the top of the channel region 411. The bottom of the trench 410 has a gate dielectric layer 412 on the channel region 411 and a high K The dielectric layer 413 , the sidewall of the trench 410 has an offset spacer 414 and a sidewall 415 , and the surface of the sidewall 415 and the surface of the ion implantation region are covered by a stress mask layer 416 . Sigma silicon germanium 417 is fabricated in the ion implantation region.

In this embodiment, in the PMOS transistor located in the fourth region, no metal silicide is formed on the surface of the ion implantation region, and no ion implantation is performed inside.

In this embodiment, the semiconductor substrate 100, the semiconductor substrate 200, the semiconductor substrate 300, and the semiconductor substrate 400 are all silicon substrates, so each channel region is located in the silicon substrate. The Raman spectrum returned by the region is the silicon-silicon bond Raman spectrum, and, after ultraviolet light irradiation, the ion implantation region also returns the silicon-silicon bond Raman spectrum, and the two silicon-silicon bond Raman spectrum peaks are very close. The prior art The levels cannot be distinguished, so the actual silicon-bond Raman spectrum received during measurement is the total silicon-silicon bond Raman spectrum obtained by superimposing the above two silicon-bond Raman spectra.

In this embodiment, in the above four regions, the material of each stress mask layer may be silicon nitride, the material of each interlayer dielectric layer may be silicon dioxide, and the material of each gate dielectric layer may also be silicon dioxide, The material of each high-K dielectric layer can be hafnium dioxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconia, zirconia silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, One of yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate.

In this embodiment, the above-mentioned first area, second area, third area and fourth area are arranged together in order. It should be noted that, in other embodiments of the present invention, the above-mentioned first region, second region, third region and fourth region may also be respectively located in different wafers or in different positions of the wafer. The PMOS transistors in the fabrication process located in the first region, the second region, the third region and the fourth region are respectively fabricated.

In this embodiment, after the above-mentioned first area, second area, third area and fourth area are arranged in a row in sequence, the The PMOS transistor in the region, that is, in the four regions, the corresponding ion implantation region, channel region, interlayer dielectric layer, trench, gate oxide layer, high-K dielectric layer, offset spacer, side Fabrication of walls, stress mask layers and silicon germanium.

A specific process may be that a semiconductor substrate is provided, and the semiconductor substrate has a first region, a second region, a third region and a fourth region arranged in a row. Form a dummy gate on the semiconductor substrate in the four regions, form an offset spacer on the side of the dummy gate, and use the offset spacer as a mask to cover both sides of the dummy gate The semiconductor substrate is lightly doped. Then, sidewalls are formed on the surface of the offset spacer, and the semiconductor substrate on both sides of the dummy gate is heavily doped by using the sidewalls as a mask, so as to form ion implantation regions. Thereafter, grooves are formed in the ion implantation region, and the grooves are filled with silicon germanium to form sigma-shaped silicon germanium. After that, a stress mask layer is formed to cover the surface of the entire structure, and an interlayer dielectric layer is formed on the stress mask layer, and the dummy gate is used as a stop layer to control the interlayer dielectric layer and the stress The mask layer is subjected to chemical mechanical planarization (CMP) until the surface of the above structure is flush with the surface of the dummy gate. Then the dummy gate is removed to form a trench, and a gate dielectric layer and a high-K dielectric layer are sequentially formed at the bottom of the trench.

In the above process, after forming the sigma-shaped silicon germanium and before forming the stress mask layer, ion implantation in the sigma-shaped silicon germanium and the process of forming metal silicide on the surface of the ion implantation region can be performed. Since the first region, the second region, the third region and the fourth region are arranged in a row in sequence, the above two process steps can be respectively performed using two layers of masks.

Referring to FIG. 5 , when metal silicide is formed on the surface of the ion implantation region, the mask M11 corresponds to the first region, the mask M12 corresponds to the second region, the mask M13 corresponds to the third region, and the mask M14 corresponds to the fourth region. The mask M11 and the mask M13 are blank masks, so in the PMOS transistors in the first region and the third region, metal silicide is formed on the surface of the ion implantation region. The mask M12 and the mask M14 are shadow masks, therefore, in the PMOS transistors in the second region and the fourth region, no metal silicide is formed on the surface of the ion implantation region.

Please continue to refer to FIG. 5 , when performing ion implantation in the ion implantation area, the mask M15 corresponds to the first area, the mask M16 corresponds to the second area, the mask M17 corresponds to the third area, and the mask M18 corresponds to the fourth area. The mask M15 and the mask M16 are blank masks, therefore, in the PMOS transistors in the first region and the second region, ion implantation is performed inside the ion implantation region to form an ion re-implantation region. The mask M17 and the mask M18 are shadow masks. Therefore, in the PMOS transistors in the third region and the fourth region, ion implantation is not performed inside the ion implantation region, and an ion re-implantation region is not formed.

In this embodiment, the (nickel) metal silicide located on the surface of the ion implantation area may have a thickness ranging from 1 nm to 15 nm, and the implanted ions in the ion implantation area may include phosphorus ions, arsenic ions, One or more of boron ions and gallium ions, the concentration range of the ions may be 10 ¹⁷ cm ^-3 to 10 ²⁰ cm ^-3 .

Please refer to FIG. 6. In the PMOS transistor in the process of fabrication provided by this embodiment, if one of the ion implantation regions 2 (representing the ion implantation regions in FIGS. 1 to 4 above) is used as the source region, then the The nearest ion implantation region 2 is the drain region. The channel region 1 (representing the above-mentioned channel region 111 , channel region 211 , channel region 311 and channel region 411 in FIGS. 1 to 4 ) is located between adjacent ion implantation regions 2 .

In this embodiment, the channel region 1 and the ion implantation region 2 extend to a greater extent in the direction along the width W of the channel region 2, that is, the width W of the channel region 2 is relatively large. In fact, the width of the channel region 1 W is greater than or equal to the width of the ultraviolet light spot, so as to ensure that in the area irradiated by the entire ultraviolet light spot, there is only one transistor in the direction of the width W of the channel region, in other words, in the area irradiated by the ultraviolet light spot, all The ion implantation region 2 and the channel region 1 are neither interrupted nor contain other regions, so as to ensure that the measured strain of the channel region is more accurate.

Please refer to FIG. 7 , the transistor to be tested is irradiated with a spot of ultraviolet light, and the total silicon-silicon bond Raman spectrum returned by the ion implantation region and the channel region is obtained. The PMOS transistor located in the first region returns to the first total silicon-silicon bond Raman spectrum 10 after being irradiated by the ultraviolet light spot. The PMOS transistor located in the second region returns to the second total silicon-silicon bond Raman spectrum 20 after being irradiated by the ultraviolet light spot. The PMOS transistor located in the third region returns the third total silicon-silicon bond Raman spectrum 30 after being irradiated by the ultraviolet light spot. The PMOS transistor located in the fourth region returns the fourth total silicon-silicon bond Raman spectrum 40 after being irradiated by the ultraviolet light spot.

In this embodiment, it can be known from the above analysis that the four regions are located in the silicon substrate, therefore, the actual silicon-silicon bond Raman spectrum returned by the channel region and the ion implantation region is the total silicon-silicon bond Raman spectrum. It should be noted that, after the above four areas are irradiated with ultraviolet light spots, in addition to returning four total silicon-silicon bond Raman spectra, they will also return other information such as four germanium-silicon bond Raman spectra, but this An embodiment does not require the information to be analyzed, so it is not shown.

In this embodiment, the areas of the first region, the second region, the third region and the fourth region range from 5 μm ² to 50 μm ² . In order to make the measurement result accurate, it is necessary to make the area of the ultraviolet light spot be in the same order of magnitude as the areas of the above four regions. Therefore, the area of the above four areas should be moderate. If the area of the above four areas is too large, the area of the subsequent ultraviolet light spot will be too large, causing the returned silicon-silicon bond Raman spectrum to be easily disturbed, and the measurement result is not easy to be accurate. If The areas of the above four areas are too small, resulting in too small areas of ultraviolet light spots and too low light intensity, which also result in inaccurate measurement results. In order to provide the required measurement area and make the measurement result accurate, the area range of the above four regions is set to be 5 μm ² to 50 μm ² .

In this embodiment, the area of the ultraviolet light spot is 30%-80% of the first area, the second area, the third area or the fourth area. Since the area of the ultraviolet light spot is at the micron level, its shape can only be circular usually. Therefore, in order to prevent the ultraviolet light spot from irradiating areas other than the above four areas, the area of the ultraviolet light spot is set as the first area , 30% to 80% of the second area, the third area or the fourth area, so as to ensure that the ultraviolet light spot can completely fall in the above four areas.

In this embodiment, the wavelength range of the ultraviolet light in the ultraviolet light spot is 350nm-400nm. In this embodiment, the ultraviolet light spot needs to pass through the high-K dielectric layer and the gate dielectric layer to reach the channel region. Therefore, it is necessary to select ultraviolet light of a specific wavelength to ensure that the light reaches the channel region, thereby ensuring that the ultraviolet light is irradiated to the channel region. After each channel region, a silicon-silicon bond Raman spectrum with better signal intensity can be returned.

In this embodiment, the first total silicon-silicon bond Raman spectrum 10 is actually formed by two silicon-silicon bond Raman spectra, and the first silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum 11 returned by the channel region 111 , the second silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum returned from the ion-implanted region12. Although the silicon-silicon bond Raman spectrum 11 is the original Raman spectrum returned by the silicon-silicon bond in the channel region 111, and the silicon-silicon bond Raman spectrum 12 is the original Raman spectrum returned by the silicon-silicon bond in the ion implantation region, but due to the silicon-silicon bond The peak positions of the Raman spectrum 11 and the silicon-silicon bond Raman spectrum 12 are very close, and the state of the art cannot distinguish these two Raman spectra. Therefore, in Figure 7, the silicon-silicon bond Raman spectrum 11 and the silicon-silicon bond The Raman spectrum 12 is indicated by a dotted line, while the actual Si-bond Raman spectrum returned by the first region is the first total Si-bond Raman spectrum 10 formed by superimposing these two Raman spectra, represented in Figure 7 by The solid line indicates.

Due to the ion implantation region of the PMOS transistor located in the first region, an ion re-implantation region 118 is formed in the sigma-shaped silicon germanium 117, and a metal silicide 119 is formed in the ion implantation region, and the ion re-implantation region 118 and the metal silicide All the substances 119 will absorb ultraviolet light, therefore, the peak value of the Raman spectrum 12 of the silicon-silicon bond returned by the ion implantation region is lower, resulting in a lower peak value of the Raman spectrum 10 of the first total silicon-silicon bond.

In this embodiment, the second total silicon-silicon bond Raman spectrum 20 is also formed by two silicon-silicon bond Raman spectra, and the first silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum 21 returned by the channel region 211 , the second silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum returned from the ion-implanted region 22 . Similarly, the silicon-silicon bond Raman spectrum 21 is the original Raman spectrum returned by the silicon-silicon bond in the channel region 211, and the silicon-silicon bond Raman spectrum 22 is the original Raman spectrum returned by the silicon-silicon bond in the ion implantation region, but due to the silicon The peak positions of silicon-bond Raman spectrum 21 and silicon-bond Raman spectrum 22 are very close, and the state of the art cannot distinguish these two Raman spectra. Therefore, in Figure 7, silicon-silicon bond Raman spectrum 21 and silicon The silicon-bond Raman spectrum 22 is indicated by a dotted line, while the actual silicon-bond Raman spectrum returned by the first region is the first total silicon-bond Raman spectrum 20 which is the superposition of these two Raman spectra, in Figure 7 Indicated by a solid line.

Because in the ion implantation region of the PMOS transistor located in the second region, the ion re-implantation region 218 is formed in the sigma-shaped silicon germanium 217, but no metal silicide is formed, therefore, the attenuation factor of the PMOS transistor in the second region is the same as that of the first region. The attenuation factor (commonly expressed as K) of the PMOS transistors in the first region is different, that is, because no metal silicide is formed in the second region, the intensity of the returned ultraviolet light is higher, so that the silicon-silicon bond Raman spectrum returned by the ion implantation region 22 The peak is higher than the peak of the silicon-bond Raman spectrum 12, resulting in a second total silicon-bond Raman spectrum 10 returned by the second region relative to the first total silicon-bond Raman spectrum 10 returned by the first region. Slightly elevated.

In this embodiment, the third total silicon-silicon bond Raman spectrum 30 is also formed by two silicon-silicon bond Raman spectra, and the first silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum 31 returned by the channel region 311 , the second silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum returned from the ion-implanted region32. Similarly, the silicon-silicon bond Raman spectrum 31 is the original Raman spectrum returned by the silicon-silicon bond in the channel region 311, and the silicon-silicon bond Raman spectrum 32 is the original Raman spectrum returned by the silicon-silicon bond in the ion implantation region, but due to the silicon The peak positions of the silicon-bond Raman spectrum 31 and the silicon-bond Raman spectrum 32 are very close, and the prior art level cannot distinguish these two Raman spectra. Therefore, in FIG. 7, the silicon-silicon bond Raman spectrum 31 and the silicon The silicon-bond Raman spectrum 32 is represented by a dotted line, while the actual silicon-bond Raman spectrum returned by the first region is the first total silicon-bond Raman spectrum 30 formed by the superposition of these two Raman spectra, shown in Figure 7 Indicated by a solid line.

Since metal silicide is formed on the sigma-shaped silicon germanium 317 in the ion implantation region of the PMOS transistor located in the third region, but the sigma-shaped silicon germanium 317 is not implanted with ions, therefore, the attenuation factor of the PMOS transistor in the third region It is also different from the attenuation factor of the PMOS transistor in the first region, that is, because the third region does not implant ions, the intensity of the returned ultraviolet light is higher, so that the peak value of the silicon-silicon bond Raman spectrum 32 returned by the ion-implanted region is higher than that of silicon-silicon. The peak value of the bond Raman spectrum 12 is high, therefore, relative to the first total silicon bond Raman spectrum 10 returned by the first region, the peak value of the third total silicon bond Raman spectrum 30 returned by the third region is also slightly increased high.

In this embodiment, the fourth total silicon-silicon bond Raman spectrum 40 is also formed by two silicon-silicon bond Raman spectra, and the first silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum 41 returned by the channel region 411 , the second silicon-silicon bond Raman spectrum is the silicon-silicon bond Raman spectrum returned from the ion-implanted region 42 . Similarly, the silicon-silicon bond Raman spectrum 41 is the original Raman spectrum returned by the silicon-silicon bond in the channel region 411, and the silicon-silicon bond Raman spectrum 42 is the original Raman spectrum returned by the silicon-silicon bond in the ion implantation region, but due to the silicon The peak positions of silicon bond Raman spectrum 41 and silicon bond Raman spectrum 42 are very close, and the prior art level cannot distinguish these two Raman spectra. Therefore, in Fig. 7, silicon bond Raman spectrum 41 and silicon bond Raman spectrum 41 are The silicon-bond Raman spectrum 42 is represented by a dotted line, while the actual silicon-bond Raman spectrum returned by the first region is the first total silicon-bond Raman spectrum 40 formed by the superposition of these two Raman spectra, shown in Figure 7 Indicated by a solid line.

Since the sigma-shaped silicon germanium 417 is neither formed of metal silicide nor implanted with ions in the ion implantation region of the PMOS transistor located in the fourth region, the attenuation factor of the PMOS transistor in the fourth region is also the same as that of the first region. The attenuation factors of PMOS transistors are different, that is, because the third region has neither metal silicide nor implanted ions, the intensity of the returned ultraviolet light is higher, so that the peak value of the silicon-silicon bond Raman spectrum 42 returned by the ion-implanted region is higher than that of silicon The peak value of the silicon bond Raman spectrum 12 is high, so compared with the first total silicon bond Raman spectrum 10 returned by the first region, the peak value of the fourth total silicon bond Raman spectrum 40 returned by the fourth region is further increased .

In this embodiment, among the four regions, each ion implantation region has a stress mask layer and an interlayer dielectric layer correspondingly. Since the material of the interlayer dielectric layer is silicon dioxide, it is basically equivalent to a transparent material for the ultraviolet light in the specific wavelength range used in this implementation, so the interlayer dielectric layer has basically no effect on the ultraviolet light spot reaching the ion implantation region . The material of the stress mask layer is silicon nitride. On the one hand, its thickness is small, and on the other hand, it also does not substantially affect the ultraviolet light. Therefore, its influence on the ultraviolet light spots can also be ignored. Among the four regions, there is a high-K dielectric layer above each channel region. Due to its small thickness, the influence on ultraviolet light in a specific wavelength range is negligible, so it does not affect the ultraviolet light reaching the channel region.

Please continue to refer to Figure 7. After obtaining different total silicon-silicon bond Raman spectra, the silicon-silicon bond Raman spectra returned by the channel region are obtained according to the different total silicon-silicon bond Raman spectra returned by different transistors to be tested. That is, according to the first total silicon-silicon bond Raman spectrum 10, the second total silicon-silicon bond Raman spectrum 20, the third total silicon-silicon bond Raman spectrum 30 and the fourth total silicon-silicon bond Raman spectrum 40, the channel region is obtained Returns the Raman spectrum of silicon-silicon bonds.

Specifically, the silicon in the channel region in the state will cause the movement and deformation of the Raman spectrum. Raman scattering is a kind of inelastic scattering. When the ultraviolet light with frequency ω _i and the frequency ω _j in the measurement region Phonon interaction results in energy transfer, and the frequency of ultraviolet light scattered from the channel region is ω _s , which is:

ω _s = ω _i ± ω _j

The frequency ω _i -ω _j is called the first-order Stokes (Stokes) Raman scattering, and the frequency ω _i +ω _j is called the first-order anti-Stokes. Generally, only the strongest first-order Raman scattering is studied.

Raman scattering is performed on the same material mold layer before and after strain, the first-order Stokes Raman scattering and the first-order anti-Stokes obtained by the two Raman scatterings will change, or the two times before and after Frequency ω _i -ω _j and frequency ω _i +ω _j will change. And this frequency change is called Raman frequency shift, and Raman frequency shift is the position shift of two silicon bond Raman spectra, which can also be understood as peak position shift. The Raman frequency shift reflects the change of the distance between atoms, that is, the change of bond length and bond angle, which reflects the information of strain.

From the above analysis, it can be seen that the first total silicon bond Raman spectrum 10, the second total silicon bond Raman spectrum 20, In the third total silicon-silicon bond Raman spectrum 30 and the fourth total silicon-silicon bond Raman spectrum 40, the four total silicon-silicon bond Raman spectra are the silicon-silicon bond Raman spectrum returned by the channel region and the ion implantation region The returned silicon-silicon bond Raman spectra are superimposed, and the reason is that the state of the art cannot distinguish these two silicon-silicon bond Raman spectra with very close peaks. Moreover, in the four regions, the Raman spectrum of the silicon-silicon bond returned by the channel region is the same no matter the peak value or the peak position, while the Raman spectrum of the silicon-silicon bond returned by the ion implantation region in the four regions is Corresponding to four different situations.

The four different situations specifically mean that the peak value of the Raman spectrum of silicon-silicon bonds returned by the ion implantation region in the first region is the smallest, the peak value of the Raman spectrum of silicon-silicon bonds returned by the ion implantation region in the fourth region is the largest, and that of the second region and the third region The silicon-silicon bond Raman spectrum peak returned by the ion implantation region is located in the middle of the two, and the silicon-silicon bond Raman spectrum peak returned by the ion implantation region of the second region is slightly smaller than the silicon-silicon bond Raman spectrum returned by the ion implantation region of the third and third regions peak.

The reason for the above situation is that the ion implantation region of the first region has a metal silicide on the surface and an ion re-implantation region inside, the ion implantation region of the second region has no metal silicide on the surface but has an ion re-implantation region inside, and the third region There is metal silicide on the surface of the ion implantation region but no ion re-implantation region is formed inside, and no metal silicide is formed on the surface of the ion implantation region of the fourth region and no ion re-implantation region is formed inside, regardless of whether it is an ion re-implantation region or a metal All silicides will absorb ultraviolet light, resulting in a decrease in the peak of the Raman spectrum of the silicon-silicon bond. It can be concluded that, in fact, the four cases are all possible combinations of metal silicide and ion re-implantation regions.

Through the analysis and comparison of the four total silicon-silicon bond Raman spectra, it can be distinguished: 1. The influence of the metal silicide on the surface of the ion implantation area on the total silicon-silicon bond Raman spectrum; 2. The impact of the ion re-implantation area inside the ion implantation area on the total The influence of silicon-silicon bond Raman spectrum; 3. The influence of ion implantation region on the total silicon-silicon bond Raman spectrum. From these results, the Raman spectrum of the silicon-silicon bonds returned by the channel region can be separately distinguished.

Specifically, the Gaussian peak splitting method can be used to obtain the silicon-silicon bond Raman spectrum returned by the channel region. That is, the four total silicon-silicon bond Raman spectra can be regarded as four total Gaussian peaks, and each of the four total Gaussian peaks is formed by the superposition of two Gaussian peaks. Using the function C to represent the Gaussian peak, the first total Gaussian peak can be represented by C ₁₀ , and the two Gaussian peaks superimposed into the first total Gaussian peak can be represented by C ₁₁ and C ₁₂ respectively, then:

C ₁₀ =aC ₁₁ +bC ₁₂

Empathy

C ₂₀ =aC ₂₁ +bC ₂₂

C ₃₀ =aC ₃₁ +bC ₃₂

C ₄₀ =aC ₄₁ +bC ₄₂

In the above four formulas, C ₁₀ , C ₂₀ , C ₃₀ and C ₄₀ are known, and there are C ₁₁ =C ₂₁ =C ₃₁ =C ₄₁ , and for C ₁₂ , C ₂₂ , C ₃₂ and C ₄₂ , The peak positions are the same, and the only difference is the peak value. Therefore, the values of coefficient a and coefficient b can be obtained through iterative fitting of Gaussian peaks (which can be completed by corresponding computer programs), and further obtain C ₁₁ , C ₂₁ , C ₃₁ and C ₄₁ , that is, to obtain the Raman spectrum of silicon-silicon bonds returned by the channel region.

In this embodiment, after obtaining the silicon-silicon bond Raman spectrum returned by the channel region, the silicon-silicon bond Raman spectrum returned by the channel region is compared with the silicon-silicon bond Raman spectrum returned by the channel region with zero strain and analysis, the strain in the channel region is obtained.

For the silicon bond Raman spectrum returned by the channel region with zero strain, it can be measured by the same experimental method, that is, the channel region with zero strain (that is, the active region, whose area can be larger than The area of the ultraviolet light spot), and then irradiate the channel region with zero strain with the ultraviolet light spot, and obtain the silicon bond Raman spectrum returned by the channel region with zero strain.

In this embodiment, the factors affecting the strain of the channel region include geometric factors, namely the shape of silicon germanium and the distance from silicon germanium to the channel region. Another factor is the content and distribution of germanium in silicon germanium. In addition , the degree of lattice integrity (such as the presence or absence of dislocations) is also a factor. Because in the first region, the second region, the third region and the fourth region, the corresponding PMOS transistors are fabricated with structures such as sigma-shaped silicon germanium, stress mask layer, metal silicide and ion re-implantation region, therefore, The silicon-silicon bond in the channel region is squeezed and deformed, and the corresponding bond length and bond angle change, resulting in strain in the channel region, and this strain is affected by the above factors, and the peak of the Raman spectrum of the silicon-silicon bond The amount and direction of displacement represent the magnitude and type of strain (squeeze and extend). Irradiating the strained channel region with an ultraviolet light spot can obtain a silicon-silicon bond Raman spectrum different from the silicon-silicon bond Raman spectrum returned by the channel region with zero strain, through the combination of two silicon-silicon bond Raman spectra In contrast, the frequency shift (peak position change) of the Raman peak can be obtained, thereby obtaining the channel region strain.

Specifically, according to the above analysis, we can get:

σ=－500·Δω=－500·(ω _m －ω _n )

Among them, -500 is an empirical coefficient, which can be obtained by calibration or look-up table, etc., ωm is the peak position of the silicon-silicon bond Raman spectrum returned by the channel region obtained by the above process in this embodiment, and _{ωn is} the channel with zero strain The peak position of the silicon-silicon bond Raman spectrum returned by the region, and Δω is the peak position movement in units of frequency, and σ is the stress, and its unit is Mpa. Through the above relationship, the stress of the channel region can be obtained, and then according to σ=Eε, and then the channel region strain ε is obtained, where E is the elastic modulus of the channel region, which can be obtained through experiments.

The method for measuring the strain in the channel region provided in this embodiment firstly provides the transistor to be measured. The transistor is in the process of being manufactured and no metal gate is formed. At this time, the transistor is irradiated with a spot of ultraviolet light and returned to the transistor. The total silicon-silicon bond Raman spectrum returned by the channel region and the ion implantation region is separated from the silicon-silicon bond Raman spectrum returned by the channel region according to the different total silicon-silicon bond Raman spectra returned by different transistors, and then the channel region The Raman spectrum of silicon-silicon bond returned by the channel region is compared and analyzed with the Raman spectrum of silicon-silicon bond returned by the channel region with zero strain to obtain the strain of the channel region. The strain of the channel region measured by the method is true and accurate. Moreover, the whole method is simple and feasible, saves cost, does not damage the transistor, has a large spectral range, and the frequency shift is not limited by the frequency of the light source, and has a wide application range.

The measurement method of the channel region strain provided by this embodiment can distinguish the silicon-silicon bond Raman spectrum returned by the channel region from the silicon-silicon bond Raman spectrum returned by the ion implantation region, so the strain in the channel region can be measured. Individualized and accurate measurement, and the measurement method only needs to use the normal production process steps, and some of the steps are properly adjusted to obtain the required measurement structure without separate fabrication, so it has the advantages of The process is compatible, and in addition, the measurement and analysis process of the measurement method is simple, the measurement period is short, and it is easy to control.

Embodiment 2 of the present invention provides another method for measuring channel region strain.

First, multiple device regions are provided.

Transistors to be tested of the same conductivity type are formed in each device region. In this embodiment, the transistors to be tested are also PMOS transistors in the manufacturing process to ensure accurate measurement results.

In this embodiment, the PMOS transistors are respectively located in the fifth region, the sixth region, the seventh region and the eighth region, and the structures of the ion implantation regions of the PMOS transistors in different device regions are different.

Please refer to FIG. 8 , the PMOS transistor located in the fifth region includes an ion implantation region (not labeled) located in the semiconductor substrate 500 and a channel region 511 (the region enclosed by the dotted line box in FIG. 8 ), located in the semiconductor substrate 500 The upper interlayer dielectric layer 501 is located in the trench 510 in the interlayer dielectric layer 501. The trench 510 corresponds to the upper part of the channel region 511. The bottom of the trench 510 has a gate oxide layer 512 on the channel region 511 and a high-K The dielectric layer 513 , the sidewall of the trench 510 has an offset spacer 514 and a sidewall 515 , and the surface of the sidewall 515 and the surface of the ion implantation region are covered by a stress mask layer 516 . Sigma silicon germanium 517 is fabricated in the ion implantation region.

In this embodiment, in the PMOS transistor located in the fifth region, metal silicide 519 is formed on the surface of the ion implantation region, and ion implantation is performed inside, and ions are formed inside the ion implantation region (that is, in the sigma-shaped silicon germanium 517). Re-injection zone 518 .

Please refer to FIG. 9 , the PMOS transistor located in the sixth region includes an ion implantation region (not marked) and a channel region 611 (the region enclosed by the dotted line box in FIG. 6 ) located in the semiconductor substrate 600 The upper interlayer dielectric layer 601 is located in the trench 610 in the interlayer dielectric layer 601. The trench 610 corresponds to the upper part of the channel region 611. The bottom of the trench 610 has a gate oxide layer 612 on the channel region 611 and a high-K The dielectric layer 613 , the sidewall of the trench 610 has an offset spacer 614 and a sidewall 615 , and the surface of the sidewall 615 and the surface of the ion implantation region are covered by a stress mask layer 616 . Sigma silicon germanium 617 is fabricated in the ion implantation region.

Different from Embodiment 1, this embodiment is located in the PMOS transistor in the sixth region, the surface of the ion implantation region gradually transitions from the metal silicide 619 formed to no metal silicide formed, and the inside of the ion implantation region (that is, the sigma-shaped In silicon germanium 617 ), ion implantation is performed to form an ion re-implantation region 618 .

Please refer to FIG. 10 , the PMOS transistor located in the seventh region includes an ion implantation region (not labeled) and a channel region 711 (the region enclosed by the dotted line box in FIG. 10 ) located in the semiconductor substrate 700 The upper interlayer dielectric layer 701 is located in the trench 710 in the interlayer dielectric layer 701. The trench 710 corresponds to the upper part of the channel region 711. The bottom of the trench 710 has a gate oxide layer 712 on the channel region 711 and a high-K The dielectric layer 713 , the sidewall of the trench 710 has an offset spacer 714 and a sidewall 715 , and the surface of the sidewall 715 and the surface of the ion implantation region are covered by a stress mask layer 716 . Sigma silicon germanium 717 is fabricated in the ion implantation region.

The difference from Embodiment 1 is that in this embodiment, in the PMOS transistor located in the seventh region, a metal silicide 719 is formed on the surface of the ion implantation region, and the interior of the ion implantation region gradually transitions from ion implantation to non-ion implantation, so The inside of the ion implantation region (that is, in the sigma-shaped silicon germanium 717 ) gradually transitions from the ion re-implantation region 718 to the non-ion re-implantation region.

Please refer to FIG. 11 , the PMOS transistor located in the eighth region includes an ion implantation region (not marked) and a channel region 811 (the region enclosed by the dotted line box in FIG. 11 ) located in the semiconductor substrate 800 The upper interlayer dielectric layer 801 is located in the trench 810 in the interlayer dielectric layer 801. The trench 810 corresponds to the top of the channel region 811. The bottom of the trench 810 has a gate dielectric layer 812 on the channel region 811 and a high K The dielectric layer 813 , the sidewall of the trench 810 has an offset spacer 814 and a sidewall 815 , and the surface of the sidewall 815 and the surface of the ion implantation region are covered by a stress mask layer 816 . Sigma silicon germanium 817 is fabricated in the ion implantation region.

In this embodiment, in the PMOS transistor located in the eighth region, no metal silicide is formed on the surface of the ion implantation region, and no ion implantation is performed inside the ion implantation region (ie, in the sigma-shaped silicon germanium 817 ).

In this embodiment, for the materials and properties of each stress mask layer, each interlayer dielectric layer, and each gate dielectric layer in the above four regions, reference may be made to the relevant contents of Embodiment 1.

In this embodiment, the above-mentioned fifth area, sixth area, seventh area and eighth area are also arranged together in order, and the production process in the above-mentioned fifth area, sixth area, seventh area and eighth area The PMOS transistors are produced together, that is, the ion implantation region, channel region, interlayer dielectric layer, trench, gate oxide layer, high-K dielectric layer, offset spacer, side wall, stress mask layer and silicon germanium are completed at the same time production. For the specific process, refer to the corresponding content in Embodiment 1.

The difference from Embodiment 1 is that in the sixth region, the ion implantation region gradually transitions from the metal silicide 619 formed to the metal silicide-free region, and in the seventh region, the ion re-implantation region 718 is gradually formed Transitioning to the ion implantation area without the ion re-implantation area, this embodiment adopts the combination of masks as shown in FIG. 12 to form the PMOS transistors in the above four areas.

Referring to FIG. 12 , when metal silicide is formed on the surface of the ion implantation region, the mask M21 corresponds to the fifth region, the mask M22 corresponds to the sixth region, the mask M23 corresponds to the seventh region, and the mask M24 corresponds to the eighth region. The mask M21 and the mask M23 are blank masks, so in the PMOS transistors on the fifth region and the seventh region, metal silicide is formed on the surface of the ion implantation region. The masks M22 and M22 are semi-shielding masks, that is, half of the mask M22 is a blank mask, and the other half is a real mask, and the boundary line between the blank mask area and the real mask area of the mask M22 and the length of the channel region The directions are in an angle relationship of 45°, so that in the PMOS transistor on the sixth region, the surface of the ion implantation region gradually transitions from the metal silicide 619 formed to the metal silicide not formed, as shown in FIG. 9 . The mask M24 is a shadow mask, therefore, in the PMOS transistor on the eighth region, no metal silicide is formed on the surface of the ion implantation region.

It should be noted that, in other embodiments of the present invention, the included angle between the boundary line of the blank mask area and the real mask area and the length direction of the channel region may also be between 30° and 60°.

Please continue to refer to FIG. 12 , when metal silicide is formed on the surface of the ion implantation region, the mask M25 corresponds to the fifth region, the mask M26 corresponds to the sixth region, the mask M27 corresponds to the seventh region, and the mask M28 corresponds to the eighth region. The mask M25 and the mask M26 are blank masks, so in the PMOS transistors on the fifth region and the sixth region, ion implantation is performed inside the ion implantation region. The mask M27 is a semi-shielding mask, that is, half of the mask M27 is a blank mask, and the other half is a real mask, and the boundary line between the blank mask area and the real mask area in the mask M27 and the length of the channel region The directions form an included angle of 45°, so that in the PMOS transistor in the seventh region, the ion implantation region gradually transitions from the ion re-implantation region 718 to the ion implantation region without the ion re-implantation region. The mask M28 is a shadow mask, therefore, in the PMOS transistor on the eighth region, no ion implantation is performed inside the ion implantation region.

Please refer to FIG. 13 , the transistor to be tested is irradiated with an ultraviolet light spot 90 to obtain the Raman spectrum of the total silicon-silicon bonds returned from the ion implantation region and the channel region.

Different from Embodiment 1, in this embodiment, the ultraviolet light spot 90 moves in the direction shown by the hollow arrow 99 in FIG. 98 performs scanning irradiation in sequence to obtain a series of different total silicon-silicon bond Raman spectra returned from the ion implantation region and the channel region. It should be noted that, in other embodiments of the present invention, the ultraviolet spot can also be scanned and irradiated in the order of the eighth area, the seventh area, the sixth area to the fifth area.

Specifically, after the ultraviolet light spot is irradiated on the PMOS transistor in the fifth region 95 , the fifth total silicon-silicon bond Raman spectrum 91 is returned. Then the ultraviolet light spot is moved from the fifth area 95 to the sixth area 96 to obtain a plurality of gradually changing total silicon-silicon bond Raman spectra until all the ultraviolet light spots enter the sixth area 96 . Then continue to move from the sixth area 96 to the seventh area 97 . Then move from the seventh area 97 to the eighth area 98 . Scanning irradiation is maintained during the movement, and the corresponding total silicon-silicon bond Raman spectrum is continuously acquired.

One of the total silicon-silicon bond Raman spectra returned from the fifth region 95, the sixth region 96, the seventh region 97 and the eighth region 98 is shown in FIG. 13, respectively being the fifth total silicon bond returned from the fifth region 95 Silicon bond Raman spectrum 91, the sixth total silicon bond Raman spectrum 92 returned from the sixth region 96, the seventh total silicon bond Raman spectrum 93 returned from the seventh region 97 and the eighth region 98 returned The eighth total silicon bond Raman spectrum is 94, but the total silicon bond Raman spectrum returned by this example is a series of multiple total silicon bond Raman spectra. During the analysis, the required number of total silicon-silicon bond Raman spectra can be selected for analysis as required.

In this embodiment, no matter how many total silicon-silicon bond Raman spectra are returned from the fifth region 95, each total silicon-silicon bond Raman spectrum is the same, and this fifth total silicon-silicon bond Raman spectrum 91 is composed of two A silicon-silicon bond Raman spectrum is formed, the first silicon-silicon bond Raman spectrum (as shown by the dotted line in Figure 13, not marked) is the silicon-silicon bond Raman spectrum returned by the channel region 511, the second silicon-silicon bond The Raman spectrum (shown by the dotted line in Figure 13, not marked) is the Raman spectrum of silicon-silicon bonds returned from the ion implantation region.

Due to the ion implantation region of the PMOS transistor located in the sixth region 96, an ion re-implantation region 518 is formed in the sigma-shaped silicon germanium 517, and a metal silicide 519 is formed in the ion implantation region, and the ion re-implantation region 518 and the metal All silicides 519 can absorb ultraviolet light. Therefore, the peak value of the Raman spectrum of silicon-silicon bonds returned by the ion implantation region is lower, resulting in a lower peak value of the Raman spectrum 91 of the first total silicon-silicon bonds.

In this embodiment, the Raman spectrum of the total silicon-silicon bond returned from the sixth region 96 shows a trend of gradually moving and a rising peak. This is because, for each sixth total silicon-silicon Raman spectrum 92 returned from the sixth region 96, it is formed from two silicon-silicon Raman spectra, the first silicon-silicon Raman spectrum (eg Shown by the dotted line in Figure 13, not marked) is the silicon-silicon bond Raman spectrum returned by the channel region 611, and the second silicon-silicon bond Raman spectrum (shown by the dotted line in Figure 13, not marked) is the return of the ion implantation region Raman spectra of silicon-silicon bonds.

For different total silicon-silicon bond Raman spectra, the peaks and peak positions are different, because in the sixth region 96, the surface of the ion implantation region gradually transitions from the metal silicide 619 formed to the metal silicide not formed, therefore, the ion The metal silicide 618 in the injection region gradually decreases during the scanning process of the ultraviolet light spot, and the effect of the metal silicide 618 on absorbing ultraviolet light gradually weakens, so the peak value of the returned total silicon-silicon bond Raman spectrum gradually increases, and the peak position also occurs accordingly Variety.

Similarly, the total silicon-silicon bond Raman spectrum returned from the seventh region 97 and the eighth region 98 can be analyzed, and the specific analysis process can refer to the relevant content of the first embodiment, and will not be repeated here.

In this embodiment, the area of the fifth region 95, the sixth region 96, the seventh region 97 and the eighth region 98 ranges from 5 μm ² to 50 μm ² , and the area of the regions is set within this range to Provide the required measurement area to make the measurement result accurate.

In this embodiment, the area of the ultraviolet light spot is 30%-80% of the area of the fifth region 95 , the sixth region 96 , the seventh region 97 and the eighth region 98 . Since the area of the ultraviolet light spot is at the micron level, its shape can only be circular usually. Therefore, in order to prevent the ultraviolet light spot from irradiating to areas other than the above four areas, the area of the ultraviolet light spot is set as the fifth area. 95. 30% to 80% of the area of the sixth area 96, the seventh area 97 and the eighth area 98, so as to ensure that the ultraviolet light spot can completely fall in the above four areas.

In this embodiment, the wavelength range of the ultraviolet light in the ultraviolet light spot is 350nm-400nm. After the ultraviolet light in the wavelength range irradiates each channel region, it can return a silicon-silicon bond Raman spectrum with better signal intensity.

In this embodiment, after selecting the applicable total silicon-silicon bond Raman spectrum, the strain in the channel region can be analyzed and obtained according to the same principle as in Embodiment 1. The principle can refer to the corresponding content of Embodiment 1, and will not be repeated here. .

Different from Embodiment 1, in the method for measuring channel region strain provided in this embodiment, the total silicon-silicon bond Raman spectrum returned by the measurement is a series of multiple total silicon-silicon bond Raman spectra, therefore, can The silicon-silicon bond Raman spectrum returned by the channel region is obtained by analyzing multiple total silicon-silicon bond Raman spectra, so that the measured strain is more accurate. Moreover, since the fifth area 95 , the sixth area 96 , the seventh area 97 and the eighth area 98 are located in the same row, it is more convenient to irradiate the ultraviolet light spectrum, and the measurement operation process is simplified.

It should be noted that the method for measuring the strain in the channel region provided by the present invention can also be used to measure the strain in the channel region of the NMOS transistor. Specifically, since the ion implantation region of the NMOS transistor is usually made of silicon nitride to Tensile stress is provided. Therefore, according to the properties of silicon nitride, a laser with a corresponding wavelength can be selected for irradiation and the corresponding silicon-silicon bond Raman spectrum can be obtained, so as to determine the corresponding channel region strain.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (11)

1. A method for measuring channel region strain, characterized in that, comprising: Provide multiple device areas; A transistor to be tested of the same conductivity type is formed in each device region, the transistor to be tested includes an ion implantation region located in the semiconductor substrate and a channel region located between two adjacent ion implantation regions, and the transistor to be tested is not formed Metal gate, the structure of the ion implantation region of the transistor to be tested in different device regions is different; Using ultraviolet light spots to irradiate each device area in sequence, and obtain the total Raman spectrum returned by the ion implantation area and the channel area of the transistor to be tested in each device area; According to the different total Raman spectra returned by the transistor to be tested in different device regions, the Raman spectra of the channel region are separated, and the strain amount of the channel region is obtained. 2. the measuring method of channel region strain as claimed in claim 1 is characterized in that, described channel region is positioned at silicon substrate, and described ion implantation region is made with silicon germanium, and described total Raman spectrum is Raman spectroscopy of total silicon-silicon bonds. 3. The measuring method of channel region strain as claimed in claim 2, is characterized in that, described device area comprises first area, second area, the 3rd area and the 4th area, and described transistor to be tested is PMOS transistor , the ion implantation region is fabricated with sigma-shaped silicon germanium, wherein: The PMOS transistor located in the first region returns a first total silicon-silicon bond Raman spectrum, and metal silicide is formed on the surface of the ion implantation region, and ion implantation is performed inside; The PMOS transistor located in the second region returns a second total silicon-silicon bond Raman spectrum, no metal silicide is formed on the surface of the ion implantation region, and ion implantation is performed inside; The PMOS transistor located in the third region returns a third total silicon-silicon bond Raman spectrum, and metal silicide is formed on the surface of the ion implantation region, and ion implantation is not performed inside; The PMOS transistor located in the fourth region returns a fourth total silicon-silicon bond Raman spectrum, no metal silicide is formed on the surface of the ion implantation region, and no ion implantation is performed inside. 4. The method for measuring strain in the channel region according to claim 3, characterized in that, the areas of the first region, the second region, the third region and the fourth region range from 5 μm ² to 50 μm ² , and the The area of the ultraviolet light spot is 30%-80% of the first area, the second area, the third area or the fourth area. 5. The measuring method of channel region strain as claimed in claim 2, is characterized in that, described device area comprises the 5th area, the 6th area, the 7th area and the 8th area that are connected sequentially, and described to-be-measured The transistor is a PMOS transistor, and the ion implantation region is fabricated with sigma-shaped silicon germanium, wherein: In the PMOS transistor located in the fifth region, a metal silicide is formed on the surface of the ion implantation region, and ion implantation is performed inside; In the PMOS transistor located in the sixth region, the surface of the ion implantation region gradually transitions from metal silicide formed to no metal silicide formed, and ion implantation is performed inside; In the PMOS transistor located in the seventh region, a metal silicide is formed on the surface of the ion implantation region, and the interior gradually transitions from ion implantation to non-ion implantation; In the PMOS transistor located in the eighth region, no metal silicide is formed on the surface of the ion implantation region, and no ion implantation is performed inside; When the ultraviolet light spot is used to irradiate the transistor to be tested, the ultraviolet light spot scans and irradiates the fifth area, the sixth area, the seventh area and the eighth area sequentially or in reverse order, and the returned series of different Raman spectroscopy of total silicon-silicon bonds. 6. The method for measuring channel region strain as claimed in claim 5, characterized in that, by controlling the mask used for ion implantation and the mask for forming metal silicide, forming a , PMOS transistors in the seventh region and the eighth region. 7. The method for measuring strain in the channel region according to claim 5, characterized in that, the areas of the fifth region, the sixth region, the seventh region and the eighth region range from 5 μm ² to 50 μm ² , and the The area of the ultraviolet light spot is 30%-80% of the fifth region, the sixth region, the seventh region or the eighth region, and the width of the channel region is greater than or equal to the width of the ultraviolet light spot. 8 . The method for measuring strain in the channel region according to claim 1 , wherein the wavelength range of ultraviolet light in the ultraviolet light spot is 350nm˜400nm. 9. The measuring method of channel region strain as claimed in claim 1, is characterized in that, above the channel region of the transistor-to-be-tested is a groove, and the bottom of the groove has a groove positioned above the channel region. At least one layer of the gate oxide layer and the high-K dielectric layer, the ultraviolet light spot reaches the channel region through the trench. 10. The measuring method of channel region strain as claimed in claim 9, is characterized in that, the sidewall of described trench has offset spacer and sidewall, and described transistor to be tested also comprises stress mask layer, so The stress mask layer is located on the surface of the side wall and the surface of the ion implantation region. 11. The method for measuring channel region strain as claimed in claim 3 or 5, wherein the metal silicide is nickel metal silicide, and the thickness range of the metal silicide is 1 nm to 15 nm. The ions implanted in the ion implantation region include one or more of phosphorus ions, arsenic ions, boron ions and gallium ions, and the concentration of the ions ranges from 10 ¹⁷ cm ^-3 to 10 ²⁰ cm ^-3 .