CN102176420A - Three-dimensional high-density system in package (SIP) method - Google Patents

Abstract

The invention relates to a three-dimensional high-density system-level packaging method, which includes the steps of: providing a circuit arrangement wafer, forming at least one set of flip-chip packaging layers on the circuit arrangement wafer, and the step of forming the flip-chip packaging layer includes sequentially forming flip-chip packaging layers , underfill, encapsulation layer, wiring layer, at least one set of wiring encapsulation layer is formed on the flip-chip encapsulation layer, the step of forming the wiring encapsulation layer includes sequentially forming a front mounting layer, an encapsulation layer, and a wiring layer, and at the end Form the top encapsulant layer on the assembly wiring encapsulation layer, and plant balls under the circuit arrangement wafer. Compared with the prior art, the three-dimensional high-density system-in-package method claimed in the present invention can form a final packaged product that includes the overall system function rather than a single chip function, reducing the internal resistance, inductance and interference factors between chips in the system . In addition, a more complex multi-layer interconnection structure can be formed to achieve a system-in-package with a higher degree of integration.

Description

Three-dimensional high-density system-in-package method

technical field

The invention relates to semiconductor technology, in particular to a three-dimensional high-density system-in-package method.

Background technique

With the continuous development of integrated circuit technology, electronic products are increasingly developing in the direction of miniaturization, intelligence, high performance and high reliability. The integrated circuit packaging not only directly affects the performance of integrated circuits, electronic modules and even the whole machine, but also restricts the miniaturization, low cost and reliability of the entire electronic system. With the gradual reduction of the size of the integrated circuit chip and the continuous improvement of the integration level, the electronic industry has put forward higher and higher requirements for the integrated circuit packaging technology.

In the Chinese patent whose notification number is CN1747156C, a kind of packaging circuit arrangement wafer is disclosed. The packaging circuit arrangement wafer includes: a circuit arrangement wafer, and the circuit arrangement wafer includes a surface; a ball pad located on the surface of the circuit arrangement wafer; Soldering layer, the solder resist layer includes at least one opening, the opening exposes the ball pad; the packaging circuit arrangement wafer also includes a patterned metal reinforcement layer, the patterned metal reinforcement layer along The sidewall of the solder mask opening is formed on the ball pad.

The final product packaged and manufactured according to the above method has only a single chip function. However, with the trend of semiconductor products becoming thinner and smaller and the demand for product system functions constantly improving, how to further improve the integration of system-in-package has become an urgent need for those skilled in the art. solved problem.

Contents of the invention

The technical problem solved by the invention is: how to realize the high-density system-in-package with multi-layer structure.

In order to solve the above technical problems, the present invention provides a three-dimensional high-density system-in-package method, comprising the steps of: providing a circuit arrangement wafer; forming at least one set of flip-chip packaging layers on the circuit arrangement wafer, forming the flip-chip packaging layer The steps include sequentially forming a flip-chip layer, underfill, encapsulant layer, and wiring layer; forming at least one set of wiring encapsulation layers on the flip-chip encapsulation layer, and the step of forming the wiring encapsulation layer includes sequentially forming a front mount layer, encapsulation layer material layer and wiring layer; form the top sealing material layer on the final wiring package layer; plant balls under the circuit arrangement wafer.

Optionally, the specific steps of forming at least one set of flip-chip packaging layers on the wiring arrangement wafer include: mounting the functional surface of the chip and passive devices on the wiring arrangement wafer to form the first flip-chip layer; fill the gap between the chip of the first flip-mount layer and the line arrangement wafer to form an underfill; form a sealing compound layer covering the first flip-mount layer on the line arrangement wafer, so that the first flip-mount layer is covered by the The plastic encapsulant of the first encapsulant layer is covered and sealed; and the first wiring layer is formed on the first encapsulant layer.

Optionally, the step of forming the first wiring layer on the first encapsulant layer includes: forming a first micro-via in the first encapsulant layer, and then filling the first micro-via with a conductive material to form a first longitudinal Wiring; forming a first horizontal wiring connecting the first vertical wiring on the first encapsulation layer, wherein the first wiring layer is used to implement the first flip-chip packaging layer and the line arrangement wafer and other packaging layers. electrical connection.

Optionally, the specific step of forming at least one group of wiring packaging layers on the flip-chip packaging layer includes: attaching the chip and the opposite side of the functional surface of the passive device to the first flip-chip packaging layer to form a first positive-mounted packaging layer. The first flip-chip packaging layer is pasted with the first positive mounting layer to form a second sealing material layer, so that the chips of the first positive mounting layer and the pads of passive devices are exposed; in the second packaging A second wiring layer is formed on the material layer.

Optionally, the step of forming the second wiring layer on the second encapsulant layer includes: forming a second micro-via in the second encapsulant layer, and then filling the second micro-via with a conductive material to form a second longitudinal Wiring; forming a second horizontal wiring connected to the second vertical wiring on the second encapsulation layer, wherein the second vertical wiring is used to realize the electrical connection between the wiring packaging layer and other packaging layers, and the The second lateral wiring is used to realize the electrical connection between the devices in the wiring packaging layer.

Optionally, the circuit arrangement wafer is provided with upper and lower surfaces, and pads are provided on the upper and lower surfaces.

Optionally, the spacing between pads on the upper surface of the circuit arrangement wafer is smaller than the spacing between pads on the lower surface.

Optionally, the mounting layer includes chips, and the chips are single or multiple.

Optionally, the mounting layer further includes passive components, and the passive components are one or more of capacitors, resistors or inductors.

Compared with the prior art, the three-dimensional high-density system-in-package method claimed in the present invention integrates chips and passive devices and then packages them together, which can form a final packaged product that includes the overall system function instead of a single chip function ; At the same time, the multilayer packaging layer through the wiring layer realizes the high-density system interconnection of three-dimensional perspective. Compared with the existing system-in-package, the multilayer wiring structure makes full use of the thickness of the chip itself, and meets the requirements of light and thin semiconductor packaging. While meeting the short trend requirements and more complex system function integration requirements, the internal resistance, inductance and interference factors between chips are better reduced, and the structural strength and product reliability are well enhanced.

Description of drawings

1 to 3 are flowcharts of a three-dimensional high-density system-in-package method in an embodiment of the present invention;

FIG. 4 to FIG. 13 are schematic diagrams of packaging structures in the processes shown in FIG. 1 to FIG. 3 .

Detailed ways

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

Secondly, the present invention is described in detail by means of schematic diagrams. When describing the embodiments of the present invention in detail, for convenience of explanation, the schematic diagrams are only examples, which should not limit the protection scope of the present invention.

The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

Referring to FIG. 1 , it shows a schematic flow chart of an embodiment of the three-dimensional high-density system-in-package method of the present invention, and the system-in-package method includes the following steps:

S101, providing line finishing wafers;

S102, forming at least one set of flip-chip packaging layers on the circuit arrangement wafer;

S103, forming at least one set of wiring packaging layers on the flip-chip packaging layer;

S104, forming a top sealing material layer on the final wiring packaging layer;

S105, planting balls under the circuit arrangement wafer.

Each step will be further described below in conjunction with the accompanying drawings.

Execute step S101, as shown in FIG. 4 , provide a circuit arrangement wafer 101. The circuit arrangement wafer 101 is the basis for subsequent stacking of each packaging layer, and at the same time, it is also the basis for carrying subsequent layers of packaging layers. The circuit arrangement wafer 101 It includes two functional surfaces, wherein, the first surface of the circuit arrangement wafer 101 is used for stacking packaging layers, and the second surface of the circuit arrangement wafer 101 is used for ball planting (implantation of connection balls). In the embodiment, the upper surface of the wiring arrangement wafer 101 is used for stacking packaging layers, the lower surface of the wiring arrangement wafer 101 is used for ball planting, and the upper and lower surfaces of the wiring arrangement wafer 101 are both Pads for electrical connection are provided, and the pads on the upper and lower surfaces are connected through the connecting wires inside the wiring arrangement wafer 101, wherein the spacing between the pads on the upper surface of the wiring arrangement wafer 101 may be smaller than that on the lower surface The pad spacing of the upper surface is designed to meet the technical requirements of high-precision and high-integration chips on the upper surface, and the looser pad spacing on the lower surface is to adapt to the technical accuracy of the final product SMT (surface mount). Therefore, the circuit arrangement wafer here can not only carry out circuit arrangement on the subsequent packaging layer, but also serve as a precision bridge between chip manufacturing technology and component placement technology.

Wherein, the arrangement of the upper and lower lines of the line arrangement wafer 101 can realize circuit conduction through TSV (Through Hole Via) technology, which is well known to those skilled in the art, and will not be repeated here.

Execute step S102, referring to FIG. 2, which shows a schematic flow chart of an embodiment of step S102 shown in FIG. Not limited thereto, specifically, the step S102 includes the following sub-steps:

Step S1021, forming a first flip-mount layer on the circuit arrangement wafer;

Step S1022, forming an underfill between the first flip-mount layer and the line arrangement wafer;

Step S1023, forming a first encapsulant layer covering the first flip-mount layer on the circuit arrangement wafer;

Step S1024, forming a first wiring layer on the first encapsulant layer.

Step S1021 is executed to surface-mount the chips and the functional components of the passive components on the circuit arrangement wafer 101 to form the first flip-mount layer 102 . The functional surface of the first flip-mount layer 102 refers to the surface where the functional solder joints of the chip and the pads of the passive components in the first flip-mount layer 102 are located. The mounting positions of chips and passive components in the first flip-mount layer 102 are set according to the designed overall wiring scheme. The bonding pads on the upper surface of the wafer 101 are interconnected. The specific steps of flip chip mounting and mounting passive components are well known to those skilled in the art, and will not be repeated here.

In a preferred embodiment of the present invention, the first flip-mount layer 102 attached to the circuit arrangement wafer 101 and the subsequently-mentioned mount layer may include one or more identical or different chips, or Consists of one or more of the same or different passive components. Each of these chips and passive devices becomes a part of a system-in-package product, and each implements one or more individual functions in the system-level functions.

In a preferred embodiment of the present invention, the combination of chips and passive components in the first flip-mount layer 102 is designed according to system functions. Therefore, around one or a group of chips, there may be another same or different chip or a group of chips, or the same or different passive devices such as capacitors, resistors or inductors; similarly, around a passive device , may have the same or different other passive components, or one or more same or different chips.

Step S1022 is executed, as shown in FIG. 5 , filling the gap between the chips in the first flip-mount layer 102 and the wiring arrangement wafer 101 to form an underfill.

In one embodiment of the present invention, the filler forming the underfill is high molecular weight epoxy resin. This material has good fluidity, can fully fill the gap between the flip chip and the encapsulant layer, and avoid reliability problems such as internal voids in the subsequent encapsulant layer. The method for forming the filler is mainly glue dispensing, and the specific glue dispensing method is well known to those skilled in the art, and will not be repeated here.

Execute step S1023, as shown in FIG. 6 , form the first encapsulant layer 103 covering the first flip-mount layer 102 on the circuit arrangement wafer 101, so that the first flip-mount layer 102 is covered by the first sealant layer 103 The plastic encapsulant is covered and sealed. In the subsequent process, the first encapsulant layer 103 can not only protect the first positive mount layer 105, but also serve as a carrier for the subsequent process.

In one embodiment of the present invention, the material of the first encapsulant layer 103 is epoxy resin. Epoxy resin has good sealing performance and is easy to shape, so it is a better material for forming the first sealing material layer 103 . Specifically, the method of forming the first encapsulant layer 103 may adopt methods such as printing, transfer or compression. The specific steps of these methods are well known to those skilled in the art and will not be repeated here.

Step S1024 is executed, as shown in FIG. 7 , the first wiring layer 104 is formed on the first encapsulant layer 103, specifically, the first wiring layer 104 includes first vertical wiring and first horizontal wiring, and the first The wiring layer 104 is used to realize the electrical connection between the first flip-chip packaging layer and the wiring arrangement wafer 101 and other packaging layers. The step of forming the first wiring layer 104 includes:

forming a first micro-via in the first encapsulant layer, and then filling the first micro-via with a conductive material to form a first vertical wiring;

A first horizontal wiring connected to the first vertical wiring is formed on the first encapsulant layer.

Specifically, a first micro-via hole is formed on the first sealing material layer 103 by drilling, and the first micro-via hole penetrates the first sealing material layer 103 and exposes the solder in the circuit arrangement wafer 101. plate, forming a channel for interconnection with the circuit arrangement wafer 101; filling the first micro-via hole with conductive material, thereby forming the first vertical wiring, so that the first vertical wiring and the pads in the circuit arrangement wafer 101 are guided interconnection; on the first encapsulation layer 103, a first horizontal wiring connecting the first vertical wiring is formed, and the first horizontal wiring is used to realize the electrical connection between the first wiring layer 104 and the vertical wiring of the wiring layer in other encapsulation layers. connect. The conductive material may be metal, such as copper and the like.

So far, the fabrication process of forming the first flip-chip packaging layer on the circuit arrangement wafer 101 is completed.

Execute step S103, referring to FIG. 3 , which shows a schematic flow chart of an embodiment of step S103 shown in FIG. Not limited thereto, specifically, the step S103 includes the following sub-steps:

Step S1031, attaching the first front mounting layer on the first flip chip packaging layer;

Step S1032, forming a second encapsulant layer on the side of the first flip-chip packaging layer pasted with the first front-mount layer;

Step S1033, forming a second wiring layer on the second encapsulant layer;

Step S1034, stacking a second positive mount layer on the second encapsulant layer;

Step S1035, forming a third sealing material layer covering the second positive mount layer on the second sealing material layer;

Step S1036, forming a third wiring layer on the third encapsulant layer.

Step S1031 is executed, as shown in FIG. 8 , the chip and the side opposite to the functional side of the passive device are pasted on the first encapsulant layer 103 to form the first positive mount layer 105 . The functional surface of the first positive mounting layer 105 refers to the surface where the bonding pads of the chip and the bonding pads of passive devices in the first positive mounting layer 105 are located. The mounting positions of chips and passive components in the first positive mounting layer 105 are set according to the designed overall wiring scheme. The first front mount layer 105 is similar to the first flip mount layer 102, and may include one or more same or different chips, and may also include one or more same or different passive devices.

Execute step S1032, as shown in Figure 9, form the second encapsulant layer 106 on the side of the first flip-chip packaging layer with the first positive mounting layer 105, so that the chip of the first positive mounting layer 105 and the passive The pads of the device are exposed. The material for forming the second sealing material layer 106 may be the same as that for forming the first sealing material layer 103 , that is, epoxy resin is used to form the second sealing material layer 106 .

Step S1033 is executed, as shown in FIG. 10 , a second wiring layer 107 is formed on the second encapsulant layer 106, specifically, the second wiring layer 107 includes a second vertical wiring and a second horizontal wiring, and the first The vertical wiring is used to realize the electrical connection between the first wiring packaging layer and the first flip-chip packaging layer, and other packaging layers, and the second horizontal wiring is used to realize the electrical connection between devices in the first wiring packaging layer. The step of forming the second wiring layer 107 includes:

forming a second micro-via in the second encapsulant layer, and then filling the second micro-via with a conductive material to form a second vertical wiring;

A second horizontal wiring connected to the second vertical wiring is formed on the second encapsulant layer.

Specifically, a second micro-via hole is formed on the second sealing material layer 106 by drilling, and the second micro-via hole penetrates the second sealing material layer 106 and exposes the first wiring layer 104. A horizontal wiring, forming a channel for interconnection with the first flip-chip packaging layer; filling the second micro-via with conductive material, thereby forming a second vertical wiring, so that the second vertical wiring is connected with the first wiring layer 104 The first horizontal wiring conducts interconnection; the second horizontal wiring connected to the second vertical wiring is formed on the second packaging material layer 106, and the second horizontal wiring forms the first positive mounting layer on the second packaging material layer 106 The interconnections among the devices in 105, specifically, the pad surfaces of the second lateral devices are connected. The conductive material may be metal, such as copper and the like.

In practical applications, vertical wiring can be selectively formed in the encapsulant layer according to design requirements, so as to realize the electrical connection between each encapsulation layer or between the encapsulation layer and the circuit arrangement wafer 101, because the encapsulant layer has good insulation , can avoid interference between devices in each packaging layer.

So far, the fabrication process of forming the first wiring encapsulation layer on the first flip-chip encapsulation layer is completed.

Step S1034 is executed to stack the second positive mount layer 108 on the second encapsulant layer 106 . The stacking refers to placing the second positive mount layer 108 at a predetermined position on the second encapsulant layer 106 .

It should be noted that, in the stacking step, the second positive mount layer 108 is stacked on the second encapsulant layer 106 with the functional side facing up. The second positive mounting layer 108 is similar to other mounting layers, and may include one or more same or different chips, and may also include one or more same or different passive devices.

Then step S1035 is performed to form the third sealing material layer 109 covering the second positive mounting layer 108 on the second sealing material layer 106, and make the bonding pad of the chip of the second positive mounting layer 108 and the soldering pad of the passive device The disk is exposed. The material for forming the third sealing compound layer 109 may be the same as that for forming the other sealing compound layers, that is, epoxy resin is used to form the third sealing compound layer 106 .

Step S1036 is executed, as shown in FIG. 11 , a third wiring layer 110 is formed on the third encapsulant layer 109, specifically, the third wiring layer 110 includes third vertical wiring and third horizontal wiring, and the third The vertical wiring is used to realize the electrical connection between the second wiring packaging layer and other packaging layers, and the third horizontal wiring is used to realize the electrical connection between devices in the second wiring packaging layer. The step of forming the third wiring layer 110 includes:

forming a third micro-via hole in the third encapsulant layer, and then filling the third micro-via hole with a conductive material to form a third vertical wiring;

A third horizontal wiring connected to the third vertical wiring is formed on the third encapsulant layer.

The method for forming the third wiring layer 110 is similar to the method for forming the second wiring layer 107 , and will not be repeated here.

So far, the fabrication process of sequentially forming the first wiring encapsulation layer and the second wiring encapsulation layer on the first flip-chip encapsulation layer is completed, and the wiring layer is penetrated between the wiring arrangement wafer 101, the first wiring encapsulation layer and the second wiring encapsulation layer. Realized system interconnection.

In the foregoing embodiment, two sets of wiring encapsulation layers are taken as an example, but the present invention is not limited thereto, and one or more than two sets of encapsulation layers can also be formed on the flip-chip encapsulation layer, and the manufacturing process of other encapsulation layers is the same as that of the above encapsulation The process of making layers is similar and will not be repeated here.

Execute step S104, as shown in FIG. 12 , form a top sealing material layer on the final wiring packaging layer

Cover the sealing layer material on the third wiring layer 110 to form a top sealing layer 111, the top sealing layer 111 is used to protect the third wiring layer 110 from damage, the top sealing layer 111 and other sealing materials The materials and formation methods of the layers are the same.

Then step S105 is executed, as shown in FIG. 13 , ball planting is performed under the circuit arrangement wafer 101 to form connection balls 112 . Specifically, ball planting is carried out at the position corresponding to the connecting wires in the circuit arrangement wafer 101. The metal for ball planting can be metal tin, tin alloy and other metals to form the connection balls 112. The ball planting process is the same as the current There are the same technologies, so I won't repeat them here.

So far, the circuit arrangement wafer 101 and each package layer have realized the interconnection between adjacent or separated package layers, and then realized the system integration through the line arrangement inside the circuit arrangement wafer 101, and finally output the function through ball planting.

Although the present invention has been disclosed above with preferred embodiments, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (9)

1. the three-dimensional high-density system-in-a-package method is characterized in that, comprises step:

Circuit arrangement wafer is provided; At least one group of flip-chip packaged layer of formation on described circuit arrangement wafer, the step that forms described flip-chip packaged layer comprises that the dress layer is lost money instead of making money in formation successively, the bed of material, wiring layer are filled, sealed in the bottom; On the flip-chip packaged layer, form at least one group of wiring encapsulated layer, form described wiring encapsulated layer ground step and comprise that formation is successively just mounting layer, the envelope bed of material, wiring layer; On end group wiring encapsulated layer, form the top envelope bed of material; Below circuit arrangement wafer, plant ball.

2. three-dimensional high-density system-in-a-package method as claimed in claim 1 is characterized in that, the concrete steps that form at least one group of flip-chip packaged layer on circuit arrangement wafer comprise:

The function face of chip and passive device is mounted on the circuit arrangement wafer, forms first and lose money instead of making money the dress layer; Fill up gap between first chip of losing money instead of making money dress layer and circuit arrangement wafer to form the bottom filling with inserts; On circuit arrangement wafer, form the envelope bed of material that the dress layer is lost money instead of making money in covering first, make first to lose money instead of making money the dress layer by the plastic packaging material of described first envelope bed of material coating sealing; On the first envelope bed of material, form first wiring layer.

3. three-dimensional high-density system-in-a-package method as claimed in claim 2 is characterized in that, the step that forms first wiring layer on the first envelope bed of material comprises:

Form first micro through hole in the first envelope bed of material, filled conductive material in first micro through hole forms the first vertically wiring afterwards; Form to connect the described first vertically first laterally wiring of wiring on the first envelope bed of material, wherein, described first wiring layer is used to realize that the first flip-chip packaged layer puts being electrically connected between wafer and other encapsulated layers in order with circuit.

4. three-dimensional high-density system-in-a-package method as claimed in claim 1 is characterized in that, the concrete steps that form at least one group of wiring encapsulated layer on the flip-chip packaged layer comprise:

The relative one side of the function face of chip and passive device is mounted on the first flip-chip packaged layer, forms first and just mounting layer; Form the second envelope bed of material with posting first one side that is just mounting layer on the first flip-chip packaged layer, making first, just to mount the chip and the pad of passive device of layer exposed; On the second envelope bed of material, form second wiring layer.

5. three-dimensional high-density system-in-a-package method as claimed in claim 4 is characterized in that, the step that forms second wiring layer on the second envelope bed of material comprises:

Form second micro through hole in the second envelope bed of material, filled conductive material in second micro through hole forms the second vertically wiring afterwards; On the second envelope bed of material, form and connect the described second vertically second laterally wiring of wiring, wherein, described second vertically wiring be used to realize being electrically connected between place wiring encapsulated layer and other encapsulated layers, described second laterally wiring be used for realizing connect up electrical connection between the encapsulated layer device of place.

6. as the described three-dimensional high-density system-in-a-package method of any claim of claim 1～5, it is characterized in that: described circuit arrangement wafer is provided with upper and lower surface, and described upper and lower surface is provided with pad.

7. three-dimensional high-density system-in-a-package method as claimed in claim 6 is characterized in that: the solder pad space length of described circuit arrangement wafer upper surface is less than the solder pad space length of lower surface.

8. as the described three-dimensional high-density system-in-a-package method of any claim of claim 1～5, it is characterized in that: described mounting comprises chip in the layer, described chip is single or many.

9. three-dimensional high-density system-in-a-package method as claimed in claim 8 is characterized in that: the described layer that mounts comprises that also passive device, described passive device are one or more in electric capacity, resistance or the inductance.

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