Design for debug & test

This study presents a synthetic model intercomparison to investigate the importance of transport model errors for estimating the sources and sinks of CO 2 using satellite measurements. The experiments were designed for testing the potential performance of the proposed CO 2 lidar A-SCOPE, but also apply to other space borne missions that monitor total column CO 2 . The participating transport models IFS, LMDZ, TM3, and TM5 were run in forward and inverse mode using common a priori CO 2 fluxes and initial concentrations. Forward simulations of column averaged CO 2 (xCO 2 ) mixing ratios vary between the models by σ =0.5 ppm over the continents and σ =0.27 ppm over the oceans. Despite the fact that the models agree on average on the sub-ppm level, these modest differences nevertheless lead to significant discrepancies in the inverted fluxes of 0.1 PgC/yr per 10 6 km 2 over land and 0.03 PgC/yr per 10 6 km 2 over the ocean. These transport model induced flux uncertainties exceed the target requirement that was formulated for the A-SCOPE mission of 0.02 PgC/yr per 10 6 km 2 , and could also limit the overall performance of other CO 2 missions such as GOSAT. A variable, but overall encouraging agreement is found in comparison with FTS

Intelligent assist devices (IADs) are a new class of hybrid 1 devices for direct, physical, interaction with a human operator in shared workspaces. These devices -designed for the assembly line worker -can reduce ergonomics concerns that arise due to on-the-job physical and cognitive loading, while improving safety, quality and productivity. Cobots, a sub-set of IADs, implement software defined virtual guiding surfaces while providing some amplification of human power. They exemplify the central theme of this paper -that humans are critical in many assembly operations and ergonomics tools that enable them to perform their duties are necessary. This paper describes broad design principles for human-machine interaction in these industrial settings. Prototype industrial cobots designed for testing and validation are described. Efforts at commercializing these technologies for use in industrial settings are currently underway.

Recent developments in the field of MEMS indicate a clear move toward systems, rather than just individual components. Design and fabrication of these components include new methods and techniques. Does testing require new methodologies and tools ? Will we be able to include MEMS in the SoCs flow ? Position Statement S. Mir : MEMS are analog components. Embedding them in highly integrated devices means new test challenges for the analog and mixed-signal test community due to the multiple energy domains considered. Failure mechanisms and reliability are poorly understood and structured test approaches are generally missing. Functional testing of MEMS parts may be unavoidable, together with the use of expensive test equipment able to deal with signals other than electrical. Extremely high test costs together with poor reliability of MEMS blocks are major obstacles to see this type of cores in the SoCs of the near future.

In Very-Large-Scale-Integration (VLSI) designs, thorough testing is indispensable for identifying the structural defects of the chip. Timely detection and correcting serious defects are pivotal in preventing faulty chips from reaching customers and avoiding failures. In scan designs, the toggling activity is a critical factor due to the defects between lower cells and metal layers, exacerbated by diverse Process, Voltage, and Temperature (PVT) conditions. These defects significantly impact design testability, quality, and reliability, necessitating meticulous testing to ensure that chips meet the desired specifications. Effectively managing power consumption in the current VLSI landscape is crucial amid the ongoing energy crisis. Balancing the need for Low-Power (LP) with the complexity of integrating transistors onto a single silicon substrate poses significant challenges. As chip densities increase, power dissipation during testing surges, adversely affecting durability, performance, cost, and reliability. Engineers are racing to optimize test power usage, employing advanced Design for Test (DFT) techniques to incorporate efficient power management into Silicon-on-Chip (SoC) designs. Linear Feedback Shift Registers (LFSRs) are phenomenal in addressing DFT parameters like power, and performance, and for better pseudo-random pattern generation. Hence, this paper proposes a groundbreaking approach to power reduction techniques deploying the LFSR architecture, and thus challenging conventional scan-based testing methods. The proposed LFSR architecture is meticulously designed and rigorously tested using Cadence DFT Modus solution on ISCAS'89 benchmarking circuits. Coverage was unequivocally evaluated for Quality of Results (QoR) metrics, such as fault coverage, memory usage, pattern counts, switching activity, fault testing, and runtime. The specific evaluation clearly proved the superiority of the LFSR-based approach over the scanbased architecture. Adopting the novel LFSR architecture resulted in a ~5.6X reduction in toggling activity accompanied by a substantial ~10K pattern reduction and a runtime of nearly ~1.5 hours. Notably, the test power was reduced to 50% showcasing superior efficiency. This approach emerges as the ideal solution for industrial designs providing the best QoR for power, performance, and area. This innovative methodology marks a significant leap toward an energy-efficient and cost-effective VLSI circuit especially for stacked 2.5-3D ICs and chiplets poised to revolutionize chip manufacturing.

Strengthening the ownership rights on outsourced relational database is very important in today's internet environment. Especially where sensitive, valuable content is to be outsourced. Let us take an example of university database, weather data, stock market data, power consumption consumer behavior data, and medical and scientific data. The increasing use of databases in applications beyond "behind-the-firewalls data processing" is creating a need for watermarking relational databases. Watermarking for relational data is made possible by fact that real data can very often tolerate a small amount of errors without any significant degradation with respect to their usability. In this paper, we present a mechanism that will overcome the additive attacks, how to embed and detect watermark in relational database. In additive attack the attacker simply inserts his/her own watermark in original data. In our proposed system we can restrict the additive attack by embedding multiple watermarks in original data. In multiple watermarking the owner of the data first inserts the watermarks and again applies the watermarks by choosing the function g which restricts the percentage of watermarks. If attacker inserts very small amount of watermark the data goes useless.

Primeiramente, meus agradecimentos aos que me apoiaram diretamente na realização desse trabalho: ao Prof. Altamiro Susin pelo apoio constante e por sempre acreditar nas minhas idéias e no meu potencial de trabalho e; ao Prof. André Borin pelo seu apoio com o desenvolvimento do projeto, a escrita dos artigos e com a constante troca de idéias e de informações. Em segundo lugar, é prioritário agradecer àqueles que participaram indiretamente na realização desse trabalho, os colegas de laboratório: Negreiros, Letícia, Márlon, Fábio e Vinícius. Também gostaria de agradecer aos professores da pós-graduação, que compartilharam seus conhecimentos entre salas de aulas e conversas nos corredores: Luigi, Luba, Gilson e Schuck. Em especial, gostaria de agradecer à Gabriela pelo seu carinho e companheirismo durante esses dois anos de mestrado.

Primeiramente, meus agradecimentos aos que me apoiaram diretamente na realização desse trabalho: ao Prof. Altamiro Susin pelo apoio constante e por sempre acreditar nas minhas idéias e no meu potencial de trabalho e; ao Prof. André Borin pelo seu apoio com o desenvolvimento do projeto, a escrita dos artigos e com a constante troca de idéias e de informações. Em segundo lugar, é prioritário agradecer àqueles que participaram indiretamente na realização desse trabalho, os colegas de laboratório: Negreiros, Letícia, Márlon, Fábio e Vinícius. Também gostaria de agradecer aos professores da pós-graduação, que compartilharam seus conhecimentos entre salas de aulas e conversas nos corredores: Luigi, Luba, Gilson e Schuck. Em especial, gostaria de agradecer à Gabriela pelo seu carinho e companheirismo durante esses dois anos de mestrado.

Current processes validation methods rely on diverse input states and exponential applications of state tomography. Through generalization of classical test theory exceptions to this rule are found. Instead of expanding a complete operator basis to validate a process, the objective is to utilize quantum effects making each gate realized in the process act on a complete set of characteristic states and next extract functional information. Random noise, systematic errors, initialization inaccuracies and measurement faults must also be detected. This concept is applied to the switching class comprising the search oracle. In a first approach, the test set cardinality is held constant to six; both testability and added depth complexity of an additional "design-for-test" circuit are related to the function realized in the oracle. Oracles realizing affine functions are shown to generate no net entanglement and are thus the easiest to test, where oracles realizing bent functions are the most difficult to test. A second approach replaces extraction complexity with a linear growth in experiment count. An interesting corollary of this study is the success found when addressing the classical test problem quantum mechanically. The validation of all classical degrees of freedom in a quantum switching network were found to necessitate exponentially fewer averaged observables than the number of tests in the classical lower bound.

This paper shows how to adapt the P1500 Design-For-Test standard through network management protocols to make the testing problem of System-On-Chips (SoCs) easier and cost-effective. For this purpose, a SoC is analyzed as a distributed system in which its own basic components or IP Cores (Intellectual Proprieties) are considered as network agents according to SNMP (Simple Network Management Protocol) protocol. An experimental study was carried out to show the effectiveness of such an approach.

This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (DFT) architectures and network management protocols to take full benefits from existing networking infrastructures. By running intensive experimentation on ITC'99 and ITC'02 design benchmarks, the efficiency of the proposed testing and diagnosis methodology is analyzed..

This paper shows how to adapt the P1500 Design-For-Test standard through network management protocols to make the testing problem of System-On-Chips (SoCs) easier and cost-effective. For this purpose, a SoC is analyzed as a distributed system in which its own basic components or IP Cores (Intellectual Proprieties) are considered as network agents according to SNMP (Simple Network Management Protocol) protocol. An experimental study was carried out to show the effectiveness of such an approach.

This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (DFT) architectures and network management protocols to take full benefits from existing networking infrastructures. By running intensive experimentation on ITC'99 and ITC'02 design benchmarks, the efficiency of the proposed testing and diagnosis methodology is analyzed..

Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reducedcode technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a lowresolution Incremental Σ∆ converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.

In this manuscript, we leverage the power of machine learning algorithms to propose a test methodology for mmwave integrated circuits. The proposed test strategy is based on identifying the main process degradation mechanisms in a particular Device Under Test (DUT) and then designing dedicated process monitor circuits to characterize this degradation and infer the DUT performance. The resulting process monitors do not load or couple to any of the DUT nodes and the methodology can be adapted to any mm-wave device without complex co-design. The proposed test methodology is illustrated on a set of 21 fabricated samples of a 65 GHz PA designed in STMicroelectronics 55 nm CMOS technology.

A set of tools ("interactive modules") targeted to e-learning is presented for teaching test generation and fault diagnosis in digital circuits. The tools support university courses on digital electronics, testing and design for testability to learn by hands-on excercises test and fault diagnosis related topics. The tasks chosen for hands-on training represent simultaneously real research problems, which allow to foster in students critical thinking, problem solving skills and creativity.

In the present study, a numerical investigation of the catalytic partial oxidation (CPO) of methane to synthesis gas (syngas) using a gliding arc (GlidArc) reactor is presented. A 2D heterogeneous plug-flow model with radial dispersion and no gradients inside the catalyst pellet are used, including the transport equations for the gas and solid phase and reaction rate equations. The governing equations of this model formed a set of stationary differential algebraic equations coupled with the non-linear algebraic equations, and were solved numerically using in-house MATLAB® code. Model results of CPO of methane were compared to previous experimental data with the GlidArc reactor found in the literature. A close match between the calculated and experimental results for temperature, reactant (CH 4 and O 2) conversion, H 2 and CO yields and species mole-fraction was obtained. The developed model was extended to predict and quantify the influence of the gas hour space velocity (GHSV) as well as determine the influence of the reactor energy density (RED), the O 2 /CH 4 molar ratio and the O 2 /N 2 molar ratio. The predicted behaviors for the species mole-fraction, reactants conversion, H 2 and CO yields and temperature along the length of the reactor have been analyzed.

Mais l'utilisation dans des lignes de production à fort volume de nouvelles techniques de test intégré pour des circuits analogiques et mixtes reste marginale comparée aux techniques employées dans le monde numérique. En effet, le remplacement d'une méthode de test éprouvée par une nouvelle technique fait courir le risque de réduire la qualité du test. Cette qualité se détermine principalement par la capacité de différencier correctement les circuits fonctionnels des circuits défectueux. Par conséquent, il est nécessaire d'étudier la qualité d'une technique de test avant son implantation dans le flot de production. Plan du manuscrit Le chapitre suivant cette introduction est consacré au flot industriel de conception de circuits intégrés analogiques et mixtes dont la complexité contraint à respecter une succession d'étapes pour optimiser les rendements de production. Ce flot, dit Top-Down, se base sur la création de plusieurs modèles du circuit, qui permettent de prédire les performances du système complet, de chaque bloc et des circuits électriques élémentaires. Plus précisément, le modèle comportemental sert de description intermédiaire importante pour établir les dimensions des circuits élémentaires, qui sont optimisées en étudiant l'impact des variations des paramètres du procédé technologie sur les performances du circuit grâce à des modèles statistiques. sur les hypothèses et les conditions nécessaires au passage d'une étape à la suivante. Le cinquième chapitre est consacré à une nouvelle technique de test intégré, purement numérique, de modulateurs Σ∆. Le fonctionnement ainsi que les différentes implantations du test numérique de ce type de modulateur sont rappelés dans la première partie. Ensuite, la génération du stimulus de test est détaillée. En particulier, les caractéristiques d'un stimulus ternaire sont comparées à celles du stimulus binaire correspondant. La conclusion de ce chapitre est illustrée par un exemple d'implantation sur une puce de cette nouvelle méthodologie. Dans le sixième chapitre, différentes techniques de test numérique d'un modulateur Σ∆ sont évaluées à partir d'une estimation des métriques de test. Ce chapitre applique la conception Top-Down à un modulateur pour mettre en évidence les étapes permettant d'obtenir les informations nécessaires à la mise en oeuvre de la méthodologie d'évaluation. Enfin, les métriques de test obtenues pour chaque technique sont estimées pour comparer leur efficacité par rapport à un test standard. Le dernier chapitre présente une application attrayante de l'implantation d'une technique de test sur le même silicium que le circuit sous test : le calibrage. Un démonstrateur conçu à partir d'un circuit programmable permet de calibrer un modulateur Σ∆ à partir de l'injection d'un signal de test binaire. Les résultats obtenus montrent la faisabilité du système. La conclusion reprend les principales contributions de ces travaux et propose des lignes directrices pour leur continuité. 2.1. Conception industrielle Chapitre2 2.1 Conception industrielle 2.1.1 Conception et vérification Le cycle de fabrication d'un circuit intégré se divise en 4 phases : la conception, la vérification, la production et le test. La figure 2.1 représente la chronologie de ces phases séparées par le critère validant leur complétion. Le cycle commence par l'élaboration d'un cahier des charges défini avec le client ou en interne suivant le produit ciblé. Un circuit se définit par un nombre de fonctionnalités et de performances correspondantes, les spécifications. Dans les faits, l'équipe de développement travaille à partir d'un cahier des charges plus strict pour anticiper de nouvelles exigences du client ou encore pour développer non pas un seul produit mais une gamme avec différentes options. Vérification Production Test Dessin des masques Respect des spécifications Conforme au cahier des charges Processus de fabrication complété Vente demande Cahier des charges Temps ''Time-to-Market'' Conception

We are investigating decision aids that present potential courses of action available to emergency responders. To determine whether these aids improve decision quality, however, we first developed test scenarios that were challenging in well-understood ways to ensure testing under the full breadth of representative decision-making situations. We devised a three-step method of developing scenarios: define the decision space, determine the cost components of each decision's potential consequences based on the principles of Robust Decision Making, then choose conflicting pairs of cost components (e.g., a small fire, implying low property damage, in a densely inhabited area, which implies high personal injury). In a validation of this approach, experiment participants made decisions faster in non-ambiguous cases versus cases that included this principled introduction of ambiguity. Our Principled Ambiguity Method of scenario design is also appropriate for other domains as long as they can be analyzed in terms of costs of decision alternatives.

Dedicado aos Srs. Drs. Profs. Rui Prior e Sérgio Crisóstomo pelo conhecimento e paciência infindáveis que demonstraram, ao Sr. Dr. Prof. Pedro Brandão por todo o suporte que amavelmente forneceu, aos meus pais e irmão e aos meus colegas com os quais convivo todos os dias.

Some conditions relating to the automata involved in the W-testing method are discussed. It is also shown how to use the method for reduced automata instead of minimal automata. New design test conditions (weak output distinguishable, strong test-complete and output delimited type) are considered for the generalised stream X-machines (stream X-machines with basic functions replaced by relations and having as output strings of symbols rather than single symbols). It is proved that testing methods similar to those already developed for ordinary deterministic stream X-machines may be applied for generalised stream X-machines with output delimited types. A particular case of generalised stream X-machine with output delimited type is the X-machine with output delimiter, which produces outputs having a distinct right end character.

While power reduction during testing is necessary for today's low-power devices, it also lowers test costs. Scan-based methods are the most widely used approach for testing integrated circuits (IC). Test vectors are shifted into and out of scan chains bit by bit during shift operation. The time required for shift operation dominates the test time. With the geometries shrinking (7 nm→5 nm→3 nm→1.8 nm), ICs are required to be tested for newer defects, increasing test time. The most effective way to reduce test time for scan operation is to increase the frequency of the shift operation. Reduction in shift power enables scan operation to be performed with increased frequency, reducing test time, and test cost. This paper presents a survey of techniques proposed recently for shift power reduction. Various techniques, including special flip-flop usage, segmentation, reordering, and low-pass filter, are being reviewed. The techniques are organized based on main attributes to underscore their similarities and differences. Pros and cons in terms of complexities involved in their implementation are discussed. We believe this paper will provide a point of reference for further studies in scan shift power reduction and will be helpful to both industry and academia.

Several designs for test techniques for fully differential circuits have recently been proposed. These techniques are based on the inherent data encoding, the fully differential analog code (FDAC), present in differential circuits. These techniques have not previously been verified experimentally. In this paper, we report results from a fabricated test chip which incorporates design for test structures. The test chip is a fully differential fifth-order filter, and was fabricated on a 2-pm CMOS process. The test techniques implemented are derived from a systemlevel technique developed earlier. The test chip contains fault injection circuitry to emulate faults. Our results demonstrate that the FDAC is a viable design for test technique for analog circuits.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

A special logic synthesis problem is considered for Boolean functions which have large don't care sets and are irregular. Here, a function is considered as irregular if the input assignments mapped to specified values ('1' or '0') are randomly spread over the definition space. Such functions can be encountered in the field of design for test. The proposed method uses ordered BDDs for logic manipulations and generates free BDD-like covers. For the considered benchmark functions, implementations were found with a significant reduction of the node/gate count as compared to SIS or to methods offered by a state-of-the-art BDD package.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

Proyecto de Investigación (Código 1360014) Instituto Tecnológico de Costa Rica. Vicerrectoría de Investigación y Extensión (VIE). Escuela de Ingeniería Electrónica, 2020Los dispositivos médicos implantables (IMDs) son sistemas críticos para la seguridad con requerimientos de potencia muy bajos, los cuales se utilizan para el tratamiento a largo plazo de diferentes condiciones médicas. IMDs utilizan un número de componentes cada vez más elevado (sensores, actuadores, procesadores, bloques de memoria), que tienen que comunicarse entre ellos en un Sistema en Chip (SoC). En este proyecto, diferentes tipos de interconexiones (punto a punto, bus, red en chip) fueron evaluadas considerando su tolerancia a fallas, consumo de potencia y capacidades de comunicación. Como parte de los productos se desarrolló una base de datos escalable sobre sistemas médicos implantables reportados en la literatura hasta el año 2018, con el fin de conocer el estado del arte y las tendencias sobre la incorporac...

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

Dedicado aos Srs. Drs. Profs. Rui Prior e Sérgio Crisóstomo pelo conhecimento e paciência infindáveis que demonstraram, ao Sr. Dr. Prof. Pedro Brandão por todo o suporte que amavelmente forneceu, aos meus pais e irmão e aos meus colegas com os quais convivo todos os dias.

Resumo-Este artigo apresenta os resultados do projecto proposto aos autores (alunos do 4.º ano da LECT) e explica como o problema específico foi resolvido. A descrição do projecto e os requisitos básicos foram considerados anteriormente nos artigos [1, 2].

For Design-For-Test (DFT) purposes, analogue and mixed-signal testing has to cope with the difficulty of test evaluation before production. This paper aims at evaluating test measures for RF components in order to optimize production test sets and thus reduce test cost. For this, we have first developed a statistical model of the performances and possible test measures of the Circuit Under Test (a Low Noise Amplifier). The statistical multi-normal model is derived from data obtained using Monte-Carlo circuit simulation (five hundred iterations). This statistical model is then used to generate a larger circuit population (one million instances) from which test metrics can be estimated with ppm precision at the design stage, considering just process deviations. With the use of this model, a trade-off between defect level and yield loss resulting from process deviations is used to set test limits. After fixing test limits, we have carried out a fault simulation campaign to verify the suitability of the different test measurements, targeting both catastrophic and single parametric faults. Catastrophic faults are modelled by shorts and opens. A parametric fault is defined as the minimum value of a physical parameter that causes a specification to be violated. Test metrics are then evaluated for the LNA case-study. As a result, test metrics for functional measurements such as S-parameters and Noise Figure are compared with low cost test measurements such as RMS and peak-to-peak current consumption and output voltage, input/output impedance, and the correlation between current consumption and output voltage.

This paper presents a novel multifunctional test structure called Analog BuILt-in Block Observer (ABILBO). This structure is based on analog integrators and achieves analog scan, test frequency generation and test response compaction. A high fault coverage was obtained by using a discrete switched-capacitor ABILBO for testing a biquad filter. The ABILBO area overhead and performance penalty can be very low if functional and testing circuitry are shared. This is typically the case of high order filters based on a cascade of biquads.

The large ATLAS toroidal superconducting magnet made of the Barrel and two End-Caps needs extensive testing at the surface of the individual components prior to their final assembly into the underground cavern of LHC. A cryogenic test facility specifically designed for cooling sequentially the eight coils making the Barrel Toroid (BT) has been fully commissioned and is now ready for final acceptance of these magnets. This facility, originally designed for testing individually the 46 tons BT coils, will be upgraded to allow the acceptance tests of the two End-Caps, each of them having a 160 tons cold mass. The integrated system mainly comprises a 1.2 kW@4.5 K refrigerator, a 10 kW liquid-nitrogen precooler, two cryostats housing liquid helium centrifugal pumps of respectively 80 g/s and 600 g/s nominal flow and specific instrumentation to measure the thermal performances of the magnets. This paper describes the overall facility with particular emphasis to the cryogenic features adopted to match the specific requirements of the magnets in the various operating scenarios.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

Dynamic voltage scaling and adaptive body biasing have been shown to reduce dynamic and leakage power consumption effectively. In this paper, we optimally solve the combined supply voltage and body bias selection problem for multi-processor systems with imposed time constraints, explicitly taking into account the transition overheads implied by changing voltage levels. Both energy and time overheads are considered. We investigate the continuous voltage scaling as well as its discrete counterpart, and we prove NP-hardness in the discrete case. Furthermore, the continuous voltage scaling problem is formulated and solved using nonlinear programming with polynomial time complexity, while for the discrete problem we use mixed integer linear programming. Extensive experiments, conducted on several benchmarks and a real-life example, are used to validate the approaches.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

Tese de doutoramento em Física (Pré-Bolonha) , especialidade de Física Tecnológica, apresentada à Faculdade de Ciências e Tecnologia da Universidade de CoimbraOs detetores baseados na tecnologia de câmara de placas resistivas (RPCs, acrónimo do inglês Resistive Plate Chambers) revelam-se muito interessantes para o desenvolvimento de tomógrafos PET (acrónimo do inglês Positron Emission Tomography) de alta resolução, baixo custo de sensibilidade elevada. Estes tomógrafos utilizam a elevada resolução temporal destes detetores para alcançarem uma resolução próxima dos 300 ps FWHM (acrónimo do inglês Full Width at Half Maximum) para os pares de fotões de 511 keV resultantes de uma aniquilação eletrão-positrão. Este facto permite a utilização de janelas temporais de coincidências estreitas, reduzindo o número de coincidências aleatórias. Por outro lado, se a deteção de coincidências for realizada em tempo real, os requisitos do sistema de aquisição e processamento de dados do tomógrafo po...

This document contains the materials for the Training Action (TA) Design for Debug and Test Techniques, a part of the Design for Debug and Test (DfDT) module within workpackage 2 of the Leonardo INSIGHT II project. The objective of this TA consists of presenting several DfDT techniques based on the IEEE 1149.1 Standard. The materials presented in TA2 (Techniques for prototype debugging and validation) and TA3 (Design for test standards and proposed standards) are first resumed and combined to provide an extensive analysis on the potentialities of using both the basic and optional modes of the Boundary Scan Test (BST) infrastructure for implementing the debug operations identified in TA2. The optional modes are covered in two hierarchy levels: the chip level, where optional instructions defined by the standard are considered, and the board level, where commercial available components with enhanced debug and test features are considered. The requirements for additional 1149.1 features for improved prototype debugging are finally discussed, leading to a set of new optional BST instructions.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

This paper presents a test methodology for mixed-signal circuits. The test approach uses a built-in sensor to analyze the dynamic current supply of the circuit under test. This current sensor emphasizes the highest harmonics of the dynamic current of the circuit under test when the current to voltage conversion is done. The goodness of the test method is analyzed first by means of a fault simulation and afterwards through the experimental data obtained from several benchmark circuits.

3D IC technology has demonstrated significant performance and power gains over 2D. However, for technology to be viable yield should be increased. Testing a complete 3D IC after stacking leads to an exponential decay in yield. Pre-bond tests are required to insure correct functionality of the die. In this work we propose a hypergraph based biased netlist partitioning scheme scheme for pre-bond testing of individual dies to reduce extra-hardware (flip-flops) required. Further reduction in hardware is achieved by a logic cone based flip-flop sharing scheme. Simulation results on ISCAS89 benchmark circuits and several industrial benchmarks demonstrate the effectiveness of the proposed approach.

A expansão da Internet e as suas actuais vertentes de utilização têm suportado o desenvolvimento do ensino à distância através deste meio (e-learning). Os sistemas existentes nesta área permitem disponibilizar os mais diversos conteúdos a um vasto leque de utilizadores remotos, bem como facilitar a sua gestão e avaliação (formativa e sumativa). Neste contexto, foram desenvolvidos vários cursos na área de Teste e Medição para leccionação remota através do sistema WebCT*, que constitui uma das ofertas com maior aceitação a nível mundial.info:eu-repo/semantics/publishedVersio

As técnicas de injecção de falhas mais utilizadas podem ser classificadas em técnicas de indução, técnicas de injecão por hardware e técnicas de injecção por software. Dentro das técnicas de injecção por hardware surgem as técnicas de injecção de falhas recorrendo à tecnologia de teste por varrimento periférico. Esta encontra-se fortemente implantada nos processadores mais recentes, fornecendo um método de acesso ao seu interior de forma a permitir operações de teste e depuração. A sua utilização para a injecção de falhas é um passo lógico e tem sido estudada desde os anos 90. Os trabalhos desenvolvidos nesta área são diversos e incluem soluções que não exigem qualquer alteração à infraestrutura normalizada e soluções que modificam as células e a infraestrutura de controlo de forma a suportarem esta funcionalidade. Estas alterações implicam atrasos temporais acrescidos e um aumento da área de silício destinada a funções de teste, tornando-se importante uma preocupação com a optimização para que a inclusão de capacidades de injecção de falhas não afecte significativamente o desempenho e o custo dos componentes onde são implementadas.