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Cortex-R52
The Cortex-R52 is Arm's most advanced processor for safety, implementing the greatest level of safety features delivered within the processor and deve... -
Cortex-R8
The Cortex-R8 processor has the highest performance in its class of real-time processors, delivering twice the performance of the Cortex-R7 processor.... -
Cortex-R7
The Cortex-R7 processor features an upgraded 11-stage, superscalar, out-of-order pipeline with advanced dynamic and static branch prediction, dynamic ... -
Cortex-R5
The Cortex-R5 processor builds on the feature set of the Cortex-R4, with a high priority, Low-Latency Peripheral Port (LLPP) and Accelerator Coherency... -
Cortex-R4
The Arm Cortex-R4 processor is the smallest deeply embedded real-time processor based on the Armv7-R architecture. The Cortex-R4 processor delivers hi...
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Debug of Cortex-R Series Devices
Debug and trace of Cortex-R series processors can be carried out through DS-5 Development Studio, with options for high speed serial trace.
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Functional Safety in Cortex-R
For IEC 61508 and ISO 26262, Arm provides a safety certified compiler, plus hardware features such as memory protection, EDC, dual-core lock-step and fault containment.
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Safety Standards in the Arm Ecosystem
Learn more about functional safety in hardware and software from medical to automotive and IoT applications. This whitepaper aslo covers the Armv8-R architecture.
Read here
Comparing Cortex-R Series Processors
| Arm Cortex-R4 | Arm Cortex-R5 | Arm Cortex-R7 | Arm Cortex-R8 | Arm Cortex-R52 | |
|---|---|---|---|---|---|
| 1.67 / 2.01 / 2.45 DMIPS/MHz* 3.47 CoreMark/MHz** |
1.67 / 2.01 / 2.45 DMIPS/MHz* 3.47 CoreMark/MHz*** |
2.50 / 2.90 / 3.77 DMIPS/MHz* 4.35 CoreMark/MHz**** |
2.50 / 2.90 / 3.77 DMIPS/MHz* 4.35 CoreMark/MHz**** |
2.16 DMIPS/MHz 4.35 CoreMarks/MHz |
|
| Lockstep configuration | Lockstep configuration Dual-core Asymmetric Multi-Processing (AMP) configuration |
Lockstep configuration Dual-core Asymmetric Multi-Processing (AMP) with QoS configuration Dual core Symmetric Multi-Processing (SMP) configuration |
Lockstep configuration Dual, triple or quad-core Asymmetric Multi-Processing (AMP) with QoS configuration Dual, triple or quad-core Symmetric Multi-Processing (SMP) configuration |
Lockstep configuration Dual, triple or quad-core Asymmetric Multi-Processing (AMP) with QoS configuration Dual, triple or quad-core Symmetric Multi-Processing (SMP) configuration |
|
| Tightly Coupled Memory (TCM) | Tightly Coupled Memory Low Latency Peripheral Port Accelerator Coherency Port Micro Snoop Control Unit (µSCU) |
Tightly Coupled Memory Low Latency Peripheral Port Accelerator Coherency Port Snoop Control Unit (SCU) |
Tightly Coupled Memory Low Latency Peripheral Port Accelerator Coherency Port Snoop Control Unit (SCU) |
Tightly Coupled Memory Low Latency Peripheral Port Flash Port |
|
| 8-stage dual issue pipeline with instruction pre-fetch and branch prediction | 8-stage dual issue pipeline with instruction pre-fetch and branch prediction | 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer | 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer |
8-stage dual issue pipeline with instruction pre-fetch and branch prediction | |
| I-Cache and D-Cache | I-Cache and D-Cache | I-Cache and D-Cache | I-Cache and D-Cache |
I-Cache and D-Cache | |
| Hardware divide, SIMD, DSP | Hardware divide, SIMD, DSP | Hardware divide, SIMD, DSP | Hardware divide, SIMD, DSP |
Hardware divide, NEON | |
| IEEE754 Double Precision FPU | IEEE754 Double Precision FPU or optimized SP Floating Point Unit | IEEE754 Double Precision FPU or optimized SP Floating Point Unit | IEEE754 Double Precision FPU or optimized SP Floating Point Unit |
IEEE754 Double Precision FPU or optimized SP Floating Point Unit | |
| Memory Protection Unit (MPU) with 8 or 12 memory regions | Memory Protection Unit (MPU) with 12 or 16 memory regions | Memory Protection Unit (MPU) with 12 or 16 memory regions | Memory Protection Unit (MPU) with 12, 16, 20 or 24 memory regions |
Stage-1 Memory Protection Unit (MPU) with 0 or 16 memory regions Stage-2 Memory Protection Unit (MPU) with 0 or 16 memory regions |
|
| ECC and Parity protection on L1 memories | ECC and Parity protection on L1 memories and AXI bus ports | ECC and Parity protection on L1 memories and AXI bus ports. Error Management with error bank |
ECC and Parity protection on L1 memories and AXI bus ports. Error Management with error bank |
ECC and Parity protection on L1 memories and AXI bus ports Bus interconnect protection |
|
| Vectored Interrupt Controller (VIC) Port or Generic Interrupt Controller (GIC) | Vectored Interrupt Controller (VIC) or Generic Interrupt Controller (GIC) | Integrated Generic Interrupt Controller (GIC) | Integrated Generic Interrupt Controller (GIC) |
Integrated Generic Interrupt Controller (GIC), 32-960 interrupts |
* The first result abides by all of the 'ground rules' laid out in the Dhrystone documentation, the second permits inlining of functions (not just the permitted C string libraries) while the third additionally permits simultaneous multifile complilation. All are with the original (K&R) v2.1 of Dhrystone.
** CFLAGS ="--cpu cortex-r4 -O3 -Otime --fpu softvfp -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"
*** CFLAGS ="--cpu cortex-r5 -O3 -Otime --fpu softvfp -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"
**** CFLAGS ="--cpu cortex-r5f -O3 -Otime -Ono_inline -Ono_multifile --fpmode=fast --loop_optimization_level=2"
Cortex-R series processors are all binary compatible, enabling software reuse and a seamless progression from one Cortex-R processor to another as functionality and/or additional processing power is required.
| 11-stage superscalar pipeline with out-of-order execution and register renaming and advanced dynamic and static branch prediction with instruction loop buffer |
| Hardware divide, SIMD, DSP |