Conmputer architecture

In this paper we present a specific CORDIC processor for variable-precision coordinates. This system allows us to specify the precision to perform the CORDIC operation, and control the accuracy of the result, in such a way that re-computation of inaccurate results can be carried out with higher precision. It permits a reliable and accurate evaluation of a wide range of elementary functions. The specific architecture designed greatly improves the computational time of previous solutions based on classic polynomial approximation. For controlling error in numerical computation (where intervals are normally narrow) the proposed design performs an interval operation in a time close to that of a point operation.

Range reduction is a crucial step for the accuracy in trigonometric functions evaluation. A new pipelined architecture to deal with range reduction for floating point representation is presented in this paper. The algorithm is based on a look-up table storing the corresponding powers of 2 mod A. The overall design has been optimized for a modulo equal to 2π , which is the most widely used due to trigonometric functions requirements. We provide an evaluation of different configurations and a full error propagation study which ensures an accuracy of one unit in the last place. Keywords pipelined architecture • range reduction • modular arithmetic • floating-point • redundant arithmetic 1 Introduction Range reduction is the first step in the computation of many elementary functions. In practice, two kinds of reduction are usual: additive reduction and multiplicative

Block-based motion estimation is one of the critical tasks in today's video compression standards such as H.26x, MPEG-1,-2 and-4. Most of the block-based motion estimation algorithms are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference blocks. In this paper, an field-programmable gate-array (FPGA) design is proposed for rapidly computing the minimum SAD. Two goals are achieved due to the use of online arithmetic (OLA): it is possible to implement a full 16!16 macroblock SAD in a single FPGA device; and it allows us to speed up computation by early termination of the SAD calculation when the candidate involved is bigger than the current reference SAD. Reconfigurable devices enable us to change 8!8 or 16!16 pixels per block quickly and easily. For a 16!16 SAD unit 1945 look-up tables (LUTs) are required at 425 MHz. A comparison with other related works is provided.

We propose a floating-point representation to deal efficiently with arithmetic operations in codes with a balanced number of additions and multiplications for FPGA devices. The variable shift operation is very slow in these devices. We propose a format that reduces the variable shifter penalty. It is based on a radix-64 representation such that the number of the possible shifts is considerably reduced. Thus, the execution time of the floating-point addition is highly optimized when it is performed in an FPGA device, which compensates for the multiplication penalty when a high radix is used, as experimental results have shown. Consequently, the main problem of previous specific highradix FPGA designs (no speedup for codes with a balanced number of multiplications and additions) is overcome with our proposal. The inherent architecture supporting the new format works with greater bit precision than the corresponding single precision (SP) IEEE-754 standard.

This paper presents a new pipelined architecture to deal with range reduction for floating point representation. It is based on Horner's scheme and a look-up table. The overall design has been optimized for a module equal to 2π, which is the most widely used due to trigonometric functions requirements. To ensure an accuracy of one unit in the last place (ULP), a complete error propagation study has been carried out.

Block matching motion estimation takes a great part of the processing time for video encoding. To accelerate this process is must to reach real time video coding. The best motion vector is obtained by full-search block matching algorithm which has to be usually implemented by hardware. In recent years, several FPGA based designs have been proposed since these devices support high number of process elements in parallel mode. In this paper a survey of recent architectures to perform the full-search block matching algorithm in FPGAs is presented. A further comparison on terms of frames per second reached, hardware cost in CLB slices and system frequency is presented.

Block based motion estimation is one of the critical task in today video compression standards such as H.26x, MPEG-1,-2 and-4 standards. Most of the block based motion estimation algorithm are based on computing the sum of absolute differences (SAD) between corresponding elements in the candidate and reference block. In this paper a FPGA design for fast computing of the minimum SAD is proposed. The hardware unit proposed is intended to augment a general-purpose core. Thanks to the use of the on-line arithmetic (OLA) two goal are achieved: it is possible to implement a full 16 × 16 macroblock SAD in a single FPGA device and it permits us to speed up the computation by early truncation of the SAD calculation when the involved candidate is bigger than the current reference SAD. Reconfigurable devices allows us to change 8 × 8 or 16 × 16 pixels per block models quickly and easily. For a 16 × 16 SAD unit 1945 look-up tables (LUTs) are required at the frequency of 425 MHz. Comparison with other related works are provided.

In this article, we present some architectures to carry out the convolution computation based on carry-save adders and circular buffers implemented on FPGAs. Carry-save adders are not frequent in the implementation in FPGA devices, since these have a fast carry propagation path. We make use of the specific structure of the FPGA to design an optimized accumulator which is able to deal with carry-save additions as well as carrypropagate additions using the same hardware. On the other hand, this structure of circular buffers allows the convolution computation of two signals with two algorithms of calculation: the input side algorithm and the output side algorithm, in a more efficient way.

In this paper we present two new methods for texture segmentation and analysis using local spectral methods. The first approach to the problem is to use a modular pattern detection in textured images based on the use of a Pseudo-Wigner Distribution (PWD) followed by a decorrelation procedure that consists of a principal component analyzer (for texture segmentation). The goal is to combine the advantages of a high spectral resolution of a joint representation given by the Pseudo-Wigner distribution (PWD) with an effective adaptive principal component analysis. The second approach is based on a modular procedure that encompasses a region of interest extraction procedure followed by a logprolate filtering scheme (for texture classification). Performance of both methods is evaluated in different application domains: fabric defective textures, epithelial cell cultures and a diatom's classification scenario yielding excellent results over other conventional spatial or spectral methods. 1. SPECTRAL METHODS: PWD DISTRIBUTION AND LOG-PROLATE REPRESENTATION 1.1. The 2D Pseudo-Wigner Distribution (PWD) The Wigner distribution (WD) was introduced in Ref. [11] as a phase space representation in Quantum Mechanics. It gives a simultaneous representation of a signal in space and spatial frequency variables. The WD presents a set of desirable mathematical properties as was formulated in [1] including high signal concentration (maximum auto-component concentration in space/spatial frequency). However, the presence of cross-terms has limited its use in some practical applications. Cross-terms can have a peak value as high as twice that of the auto-components. It is generally accepted that smoothing the WD will reduce the presence of crossterms but at the expense of smearing the auto-component ¡ This work has been partially supported by the following grants: TIC2001-3697-C03-02; III Pricit of the Comunidad Autonoma de Madrid and the IM3 medical imaging thematic network.

In this paper we deal with the throughput of on-line addition for a stream of data. This throughput is directly related to the initiation interval between two successive instances. The on-line delay for the addition of two signed-digit (or carry-save) numbers is two, and N+2 cycles are classically used to compute a new pair of Ndigit data (initiation interval: N+2). In this paper we present some techniques to reduce the initiation interval to N (which is the theoretical minimum value) with a very small amount of hardware or N+1 with no hardware cost. For short operands, this might have a significant effect on the throughput.

Constant multipliers are widely used in signal processing applications to implement the multiplication of signals by a constant coefficient. However, in some applications, this coefficient remains invariable only during an interval of time, and then, its value changes to adapt to new circumstances. In this article, we present a self-reconfigurable constant multiplier suitable for LUT-based FPGAs able to reload the constant in runtime. The pipelined architecture presented is easily scalable to any multiplicand and constant sizes, for unsigned and signed representations. It can be reprogrammed in 16 clock cycles, equivalent to less than 100 ns in current FPGAs. This value is significantly smaller than FPGA partial configuration times. The presented approach is more efficient in terms of area and speed when compared to generic multipliers, achieving up to 91% area reduction and up to 102% speed improvement for the case-study circuits tested. The power consumption of the proposed multipliers are in the range of those of slice-based multipliers provided by the vendor.

This paper presents an e cient hardware algorithm for variable-precision division. The algorithm is based on a well-known convergence algorithm, however, modi cations are made to allow it to e ciently handle variable-precision operands. The proposed algorithm reduces the number of xed-precision operation by only computing signi cant words in intermediate results. Compared to previous variable-precision division algorithms, this algorithm requires signi cantly fewer xed-point arithmetic operations.

This paper presents an e cient hardware algorithm for variable-precision logarithm. The algorithm uses an iterative technique that employs table lookups and polynomial approximations. Compared to similar algorithms, it reduces the number of xed-precision operations by avoiding full precision computations and dynamically varying the precision of intermediate results. It also uses signi cantly smaller tables than related algorithms. For a speci ed hardware implementation, the algorithm requires fewer than 2L 2 xed-precision multiplications to evaluate the logarithm to L words of precision. An error analysis for the algorithm is also presented.

In this paper we design a CORDIC architecture for variable{precision, and a new algorithm is proposed to perform the interval sine and cosine functions. This system allows us to specify the precision to perform the sine and cosine functions, and control the accuracy of the result, in such a way that recomputation of inaccurate results can be carried out with higher precision. An important reduction in the number of iterations is obtained by taking advantage of the di erential angle, and the number of cycles per iteration is reduced by avoiding the additions of the leading all zero words. As a consequence, the computation time of the interval function evaluation obtained is close to that of a point function evaluation. The problem of the large table of angles and the scale factor compensation involved in a high precision CORDIC has been solved e ciently.

A new family of arithmetic operators to optimize the implementation of circuits for digital signal processing is presented. Thanks to use of a new technique which reduces the quantification errors, the proposed operators may decrease significantly the size of the circuits required for most applications. That means a simultaneous reduction of area, delay and power consumption.

This brief presents a hardware design to achieve high-throughput QR decomposition, using Givens Rotation Method. It utilizes a new two-dimensional systolic array architecture with pipelined processing elements, which are based on the COordinate Rotation DIgital Computer (CORDIC) algorithm. CORDIC computes vector rotations through shifts and additions. This approach allows a continuous computation of QR factorizations with simple hardware. A fixed-point FPGA architecture for 4 × 4 matrices has been optimized by balancing the number of CORDIC iterations with the final error. As a result, compared to other previous proposals for FPGA, our design achieves at least 50% more throughput, and much less resource utilization.

In this paper we present the FPGA implementation of a new word--serial CORDIC processor working with variable precision. It has been designed in such a way that it allows us to take advantage of the successive shifts in the coordinates involved in the CORDIC algorithm. This significatively reduces the total number of cycles required. Special attention has been paid to the design of the critical path to obtain an acceptable cycle time. The resulting FPGA device is able to work with a word length of 16 bits through 128 bits. 1 Introduction The variable precision technique is normally used to improve the accuracy and reliability of numerical computation. It solves the problems produced by roundoff errors and catastrophic cancelation [10][6]. Several software tools have been developed to manage this problem but their main disadvantage is their long execution time for numerically intensive applications [13]. Some hardware designs exist that attempt to overcome the large overhead of these...