Daigneault et al., 2018 - Google Patents

Automated synthesis of streaming transfer level hardware designs

Daigneault et al., 2018

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Document ID
8792222124006636796
Author
Daigneault M
David J
Publication year
Publication venue
ACM Transactions on Reconfigurable Technology and Systems (TRETS)

External Links

Snippet

As modern field-programmable gate arrays (FPGA) enable high computing performance and efficiency, their programming with low-level hardware description languages is time- consuming and remains a major obstacle to their adoption. High-level synthesis compilers …
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Classifications

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    • G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
    • G—PHYSICS
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