Zhang et al., 2015 - Google Patents
CMOST: A system-level FPGA compilation frameworkZhang et al., 2015
View PDF- Document ID
- 6852065885007841463
- Author
- Zhang P
- Huang M
- Xiao B
- Huang H
- Cong J
- Publication year
- Publication venue
- Proceedings of the 52nd Annual Design Automation Conference
External Links
Snippet
Programming difficulty is a key challenge to the adoption of FPGAs as a general high- performance computing platform. In this paper we present CMOST, an open-source automated compilation flow that maps C-code to FPGAs for acceleration. CMOST …
- 230000001131 transforming 0 abstract description 17
Classifications
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- G06F9/00—Arrangements for programme control, e.g. control unit
- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
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- G06—COMPUTING; CALCULATING; COUNTING
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- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G06F9/44—Arrangements for executing specific programmes
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- G06F17/50—Computer-aided design
- G06F17/5045—Circuit design
- G06F17/5054—Circuit design for user-programmable logic devices, e.g. field programmable gate arrays [FPGA]
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