Tenentes et al., 2016 - Google Patents

Coarse-grained online monitoring of BTI aging by reusing power-gating infrastructure

Tenentes et al., 2016

View PDF
Document ID
4416728065360930918
Author
Tenentes V
Rossi D
Yang S
Khursheed S
Al-Hashimi B
Gunn S
Publication year
Publication venue
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

External Links

Snippet

In this paper, we present a novel coarse-grained technique for monitoring online the bias temperature instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power …
Continue reading at ieeexplore.ieee.org (PDF) (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3237Power saving by disabling clock generation or distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3296Power saving by lowering supply or operating voltage
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power Management, i.e. event-based initiation of power-saving mode
    • G06F1/3234Action, measure or step performed to reduce power consumption
    • G06F1/3287Power saving by switching off individual functional units in a computer system, i.e. selective power distribution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/30Monitoring
    • G06F11/34Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation; Recording or statistical evaluation of user activity, e.g. usability assessment
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F1/00Details of data-processing equipment not covered by groups G06F3/00 - G06F13/00, e.g. cooling, packaging or power supply specially adapted for computer application
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2217/00Indexing scheme relating to computer aided design [CAD]
    • G06F2217/78Power analysis and optimization
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2201/00Indexing scheme relating to error detection, to error correction, and to monitoring

Similar Documents

Publication Publication Date Title
Tenentes et al. Coarse-grained online monitoring of BTI aging by reusing power-gating infrastructure
Zick et al. Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
Bull et al. A power-efficient 32 bit ARM processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation
Sengupta et al. Estimating circuit aging due to BTI and HCI using ring-oscillator-based sensors
Kim et al. Use it or lose it: Wear-out and lifetime in future chip multiprocessors
Huang et al. On task allocation and scheduling for lifetime extension of platform-based MPSoC designs
Wang et al. Variation tolerant on-chip degradation sensors for dynamic reliability management systems
Bowman et al. All-digital circuit-level dynamic variation monitor for silicon debug and adaptive clock control
Kim et al. Adaptive delay monitoring for wide voltage-range operation
Gupta et al. Employing circadian rhythms to enhance power and reliability
Priya et al. Early register transfer level (rtl) power estimation in real-time system-on-chips (socs)
Lak et al. On using on-chip clock tuning elements to address delay degradation due to circuit aging
Yang et al. Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement
Carlo et al. SATTA: A self-adaptive temperature-based TDF awareness methodology for dynamically reconfigurable FPGAs
Chahal et al. BTI aware thermal management for reliable DVFS designs
Oboril et al. Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC EJ McCluskey doctoral thesis award competition finalist
Massari et al. Towards fine-grained DVFS in embedded multi-core CPUs
Shafik et al. Introduction to energy-efficient fault-tolerant systems
Sadeghi-Kohan et al. Self-adjusting monitor for measuring aging rate and advancement
Wang et al. In-field aging measurement and calibration for power-performance optimization
Golanbari et al. Post-fabrication calibration of near-threshold circuits for energy efficiency
Subramanian et al. Managing the impact of on-chip temperature on the lifetime reliability of reliably overclocked systems
Tenentes et al. Leakage current analysis for diagnosis of bridge defects in power-gating designs
Guo et al. Circuit techniques for BTI and EM accelerated and active recovery
Laurenciu et al. A direct measurement scheme of amalgamated aging effects with novel on-chip sensor