Yim et al., 2007 - Google Patents

52 Gb/s 16: 1 transmitter in 0.13 µm SiGe BiCMOS technology

Yim et al., 2007

Document ID
4157539419658233123
Author
Yim Y
Curran P
Chu M
McDonald J
Kraft R
Publication year
Publication venue
IET circuits, devices & systems

External Links

Snippet

A 52-Gb/s 16: 1 quarter-rate clocking transmitter for high-speed serial data transmission is designed to utilise 0.13-µm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) technology. The quarter-rate transmitter consists of a 16: 1 multiplexer (MUX), a …
Continue reading at digital-library.theiet.org (other versions)

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/03Astable circuits
    • H03K3/0315Ring oscillators
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00Generation of oscillations using amplifier with regenerative feedback from output to input
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03BGENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass

Similar Documents

Publication Publication Date Title
Ye et al. A multiple-crystal interface PLL with VCO realignment to reduce phase noise
US7724862B2 (en) Phase locked loop apparatus with adjustable phase shift
US6317008B1 (en) Clock recovery using an injection tuned resonant circuit
Cao et al. OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS
US7286625B2 (en) High-speed clock and data recovery circuit
US6249192B1 (en) Clock injection system
Meghelli et al. A 0.18-μm SiGe BiCMOS receiver and transmitter chipset for SONET OC-768 transmission systems
Toifl et al. A 0.94-ps-RMS-jitter 0.016-mm/sup 2/2.5-GHz multiphase generator PLL with 360/spl deg/digitally programmable phase shift for 10-Gb/s serial links
US6924705B2 (en) Inject synchronous narrowband reproducible phase locked looped
Momtaz et al. A fully integrated SONET OC-48 transceiver in standard CMOS
Farjad-Rad et al. A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os
Lee et al. A 20Gb/s burst-mode CDR circuit using injection-locking technique
Loke et al. An 8.0-Gb/s HyperTransport transceiver for 32-nm SOI-CMOS server processors
Shaeffer et al. A 40/43 Gb/s SONET OC-768 SiGe 4: 1 MUX/CMU
Yim et al. 52 Gb/s 16: 1 transmitter in 0.13 µm SiGe BiCMOS technology
Alhousseiny et al. Delay-locked loop based multiphase clock generator for time-interleaved adcs
Razavi Phase-locking in wireline systems: Present and future
Wong et al. A 2.5 Gbps CMOS data serializer
US11334110B1 (en) Systems and methods for communicating clock signals
Zhan et al. Full-rate injection-locked 10.3 Gb/s clock and data recovery circuit in a 45GHz-f/sub T/SiGe process
Chang et al. A shifted-averaging VCO with precise multiphase outputs and low jitter operation
Kok-Siang et al. Design of high-speed clock and data recovery circuits
Makon et al. 80 Gbit/s monolithically integrated clock and data recovery circuit with 1: 2 DEMUX using InP-based DHBTs
Wang et al. Comparative Analysis of Ring Oscillators Based on Different Feedback Paths
Shaokang Multi-phase Clock Generator for High-speed Wireline Transceiver Systems