Yang et al., 2004 - Google Patents

A chaos-based fully digital 120 MHz pseudo random number generator

Yang et al., 2004

Document ID
2092138335520902200
Author
Yang H
Huang J
Chang T
Publication year
Publication venue
The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

External Links

Snippet

A chaos-based pseudo random number generator (PRNG) is implemented in a fully digital circuit with 120 MHz operation clock frequency. The chaotic equation called logistic equation is applied to the system model of PRNG. Noise can be injected to disturb the iterations with …
Continue reading at ieeexplore.ieee.org (other versions)

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/582Pseudo-random number generators
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58Random or pseudo-random number generators
    • G06F7/588Random number generators, i.e. based on natural stochastic processes
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/50Computer-aided design
    • G06F17/5009Computer-aided design using simulation
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724Finite field arithmetic
    • G06F7/726Inversion; Reciprocal calculation; Division of elements of a finite field
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/84Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Similar Documents

Publication Publication Date Title
Pareschi et al. Implementation and testing of high-speed CMOS true random number generators based on chaotic systems
Tokunaga et al. True random number generator with a metastability-based quality control
Luo et al. A high-performance and secure TRNG based on chaotic cellular automata topology
Tuncer et al. Random number generation with LFSR based stream cipher algorithms
Wang et al. A silicon PUF based entropy pump
Yang et al. A chaos-based fully digital 120 MHz pseudo random number generator
Gupta et al. Efficient hardware implementation of pseudo-random bit generator using dual-CLCG method
Gupta et al. Coupled variable‐input LCG and clock divider‐based large period pseudo‐random bit generator on FPGA
AVAROĞLU et al. A novel S-box-based postprocessing method for true random number generation
Teo et al. Hardware implementation of multi-LFSR pseudo random number generator
Rajski et al. A nonlinear stream cipher for encryption of test patterns in streaming scan networks
Shah Fredkin gate-based feed-forward arbiter PUF design on FPGA
Sadr et al. Physical unclonable function (PUF) based random number generator
Akhila et al. Performance analysis of pseudo random bit generator using modified dual-coupled linear congruential generator
Dang et al. A true random number generator on fpga with jitter-sampling by ring generator
Amsaad et al. A novel security technique to generate truly random and highly reliable reconfigurable ROPUF-based cryptographic keys
Justin et al. FPGA implementation of high quality random number generator using LUT based shift registers
Kumar et al. Design of energy efficient true random number generator using mux-metastable approach
Garipcan et al. Implementation of a digital TRNG using jitter based multiple entropy source on FPGA
Chen et al. A low complexity and long period digital random sequence generator based on residue number system and permutation polynomial
Wijesinghe Hardware implementation of random number generators
Mehra et al. Design of hexagonal oscillator for true random number generation
Devi et al. Design of Hybrid True Random Number Generator for Cryptographic Applications.
Williams et al. Integrated Design of Hybrid Random Number Generators on FPGA: Combining TRNG and PRNG for Enhanced Security
Azhaganantham et al. FPGA implementation of RO-PUF using chaotic maps