Holst et al., 2015 - Google Patents

High-throughput logic timing simulation on GPGPUs

Holst et al., 2015

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Document ID
198081385281749089
Author
Holst S
Imhof M
Wunderlich H
Publication year
Publication venue
ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Snippet

Many EDA tasks such as test set characterization or the precise estimation of power consumption, power droop and temperature development, require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been …
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Classifications

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    • G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
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    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
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