YUEN, 2001 - Google Patents
Architecture Inclusive ParallelYUEN, 2001
- Document ID
- 11883495670320503095
- Author
- YUEN C
- Publication year
- Publication venue
- Annual Review of Scalable Computing
External Links
Snippet
Since the very early days of parallel processing, architecture independence has been the ultimate goal of system designers. Why is this problem so important, and at the same time, so difficult to solve? Architecture independence means programs are portable between …
Classifications
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- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
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- G06F9/46—Multiprogramming arrangements
- G06F9/48—Programme initiating; Programme switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
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- G—PHYSICS
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- G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
- G06F9/30—Arrangements for executing machine-instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
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- G06F9/46—Multiprogramming arrangements
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- G06F9/524—Deadlock detection or avoidance
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- G—PHYSICS
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- G06F9/00—Arrangements for programme control, e.g. control unit
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- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
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- G—PHYSICS
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- G—PHYSICS
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- G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
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- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
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- G—PHYSICS
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- G06F11/00—Error detection; Error correction; Monitoring
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